src/gallium/winsys/amdgpu/drm/amdgpu_cs.h

   1 /*
   2  * Copyright © 2011 Marek Olšák <maraeo@gmail.com>
   3  * Copyright © 2015 Advanced Micro Devices, Inc.
   4  * All Rights Reserved.
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining
   7  * a copy of this software and associated documentation files (the
   8  * "Software"), to deal in the Software without restriction, including
   9  * without limitation the rights to use, copy, modify, merge, publish,
  10  * distribute, sub license, and/or sell copies of the Software, and to
  11  * permit persons to whom the Software is furnished to do so, subject to
  12  * the following conditions:
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  15  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
  16  * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  17  * NON-INFRINGEMENT. IN NO EVENT SHALL THE COPYRIGHT HOLDERS, AUTHORS
  18  * AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  20  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
  21  * USE OR OTHER DEALINGS IN THE SOFTWARE.
  22  *
  23  * The above copyright notice and this permission notice (including the
  24  * next paragraph) shall be included in all copies or substantial portions
  25  * of the Software.
  26  */
  27 /*
  28  * Authors:
  29  *      Marek Olšák <maraeo@gmail.com>
  30  */
  31
  32 #ifndef AMDGPU_CS_H
  33 #define AMDGPU_CS_H
  34
  35 #include "amdgpu_bo.h"
  36 #include "util/u_memory.h"
  37
  38 struct amdgpu_ctx {
  39    struct amdgpu_winsys *ws;
  40    amdgpu_context_handle ctx;
  41    amdgpu_bo_handle user_fence_bo;
  42    uint64_t *user_fence_cpu_address_base;
  43    int refcount;
  44 };
  45
  46 struct amdgpu_cs_buffer {
  47    struct amdgpu_winsys_bo *bo;
  48    uint64_t priority_usage;
  49    enum radeon_bo_usage usage;
  50    enum radeon_bo_domain domains;
  51 };
  52
  53 enum ib_type {
  54    IB_CONST_PREAMBLE = 0,
  55    IB_CONST = 1, /* the const IB must be first */
  56    IB_MAIN = 2,
  57    IB_NUM
  58 };
  59
  60 struct amdgpu_ib {
  61    struct radeon_winsys_cs base;
  62
  63    /* A buffer out of which new IBs are allocated. */
  64    struct pb_buffer        *big_ib_buffer;
  65    uint8_t                 *ib_mapped;
  66    unsigned                used_ib_space;
  67    unsigned                max_ib_size;
  68    uint32_t                *ptr_ib_size;
  69    enum ib_type            ib_type;
  70 };
  71
  72 struct amdgpu_cs_context {
  73    struct amdgpu_cs_request    request;
  74    struct amdgpu_cs_ib_info    ib[IB_NUM];
  75
  76    /* Buffers. */
  77    unsigned                    max_num_buffers;
  78    unsigned                    num_buffers;
  79    amdgpu_bo_handle            *handles;
  80    uint8_t                     *flags;
  81    struct amdgpu_cs_buffer     *buffers;
  82
  83    int                         buffer_indices_hashlist[4096];
  84
  85
  86    unsigned                    max_dependencies;
  87
  88    struct pipe_fence_handle    *fence;
  89
  90    /* the error returned from cs_flush for non-async submissions */
  91    int                         error_code;
  92 };
  93
  94 struct amdgpu_cs {
  95    struct amdgpu_ib main; /* must be first because this is inherited */
  96    struct amdgpu_ib const_ib; /* optional constant engine IB */
  97    struct amdgpu_ib const_preamble_ib;
  98    struct amdgpu_ctx *ctx;
  99    enum ring_type ring_type;
 100
 101    /* We flip between these two CS. While one is being consumed
 102     * by the kernel in another thread, the other one is being filled
 103     * by the pipe driver. */
 104    struct amdgpu_cs_context csc1;
 105    struct amdgpu_cs_context csc2;
 106    /* The currently-used CS. */
 107    struct amdgpu_cs_context *csc;
 108    /* The CS being currently-owned by the other thread. */
 109    struct amdgpu_cs_context *cst;
 110
 111    /* Flush CS. */
 112    void (*flush_cs)(void *ctx, unsigned flags, struct pipe_fence_handle **fence);
 113    void *flush_data;
 114
 115    struct util_queue_fence flush_completed;
 116 };
 117
 118 struct amdgpu_fence {
 119    struct pipe_reference reference;
 120
 121    struct amdgpu_ctx *ctx;  /* submission context */
 122    struct amdgpu_cs_fence fence;
 123    uint64_t *user_fence_cpu_address;
 124
 125    /* If the fence is unknown due to an IB still being submitted
 126     * in the other thread. */
 127    volatile int submission_in_progress; /* bool (int for atomicity) */
 128    volatile int signalled;              /* bool (int for atomicity) */
 129 };
 130
 131 static inline void amdgpu_ctx_unref(struct amdgpu_ctx *ctx)
 132 {
 133    if (p_atomic_dec_zero(&ctx->refcount)) {
 134       amdgpu_cs_ctx_free(ctx->ctx);
 135       amdgpu_bo_free(ctx->user_fence_bo);
 136       FREE(ctx);
 137    }
 138 }
 139
 140 static inline void amdgpu_fence_reference(struct pipe_fence_handle **dst,
 141                                           struct pipe_fence_handle *src)
 142 {
 143    struct amdgpu_fence **rdst = (struct amdgpu_fence **)dst;
 144    struct amdgpu_fence *rsrc = (struct amdgpu_fence *)src;
 145
 146    if (pipe_reference(&(*rdst)->reference, &rsrc->reference)) {
 147       amdgpu_ctx_unref((*rdst)->ctx);
 148       FREE(*rdst);
 149    }
 150    *rdst = rsrc;
 151 }
 152
 153 int amdgpu_lookup_buffer(struct amdgpu_cs_context *cs, struct amdgpu_winsys_bo *bo);
 154
 155 static inline struct amdgpu_ib *
 156 amdgpu_ib(struct radeon_winsys_cs *base)
 157 {
 158    return (struct amdgpu_ib *)base;
 159 }
 160
 161 static inline struct amdgpu_cs *
 162 amdgpu_cs(struct radeon_winsys_cs *base)
 163 {
 164    assert(amdgpu_ib(base)->ib_type == IB_MAIN);
 165    return (struct amdgpu_cs*)base;
 166 }
 167
 168 #define get_container(member_ptr, container_type, container_member) \
 169    (container_type *)((char *)(member_ptr) - offsetof(container_type, container_member))
 170
 171 static inline struct amdgpu_cs *
 172 amdgpu_cs_from_ib(struct amdgpu_ib *ib)
 173 {
 174    switch (ib->ib_type) {
 175    case IB_MAIN:
 176       return get_container(ib, struct amdgpu_cs, main);
 177    case IB_CONST:
 178       return get_container(ib, struct amdgpu_cs, const_ib);
 179    case IB_CONST_PREAMBLE:
 180       return get_container(ib, struct amdgpu_cs, const_preamble_ib);
 181    default:
 182       unreachable("bad ib_type");
 183    }
 184 }
 185
 186 static inline bool
 187 amdgpu_bo_is_referenced_by_cs(struct amdgpu_cs *cs,
 188                               struct amdgpu_winsys_bo *bo)
 189 {
 190    int num_refs = bo->num_cs_references;
 191    return num_refs == bo->ws->num_cs ||
 192          (num_refs && amdgpu_lookup_buffer(cs->csc, bo) != -1);
 193 }
 194
 195 static inline bool
 196 amdgpu_bo_is_referenced_by_cs_with_usage(struct amdgpu_cs *cs,
 197                                          struct amdgpu_winsys_bo *bo,
 198                                          enum radeon_bo_usage usage)
 199 {
 200    int index;
 201
 202    if (!bo->num_cs_references)
 203       return false;
 204
 205    index = amdgpu_lookup_buffer(cs->csc, bo);
 206    if (index == -1)
 207       return false;
 208
 209    return (cs->csc->buffers[index].usage & usage) != 0;
 210 }
 211
 212 static inline bool
 213 amdgpu_bo_is_referenced_by_any_cs(struct amdgpu_winsys_bo *bo)
 214 {
 215    return bo->num_cs_references != 0;
 216 }
 217
 218 bool amdgpu_fence_wait(struct pipe_fence_handle *fence, uint64_t timeout,
 219                        bool absolute);
 220 void amdgpu_cs_sync_flush(struct radeon_winsys_cs *rcs);
 221 void amdgpu_cs_init_functions(struct amdgpu_winsys *ws);
 222 void amdgpu_cs_submit_ib(void *job, int thread_index);
 223
 224 #endif