src/gallium/winsys/amdgpu/drm/amdgpu_cs.h

   1 /*
   2  * Copyright © 2011 Marek Olšák <maraeo@gmail.com>
   3  * Copyright © 2015 Advanced Micro Devices, Inc.
   4  * All Rights Reserved.
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining
   7  * a copy of this software and associated documentation files (the
   8  * "Software"), to deal in the Software without restriction, including
   9  * without limitation the rights to use, copy, modify, merge, publish,
  10  * distribute, sub license, and/or sell copies of the Software, and to
  11  * permit persons to whom the Software is furnished to do so, subject to
  12  * the following conditions:
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  15  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
  16  * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  17  * NON-INFRINGEMENT. IN NO EVENT SHALL THE COPYRIGHT HOLDERS, AUTHORS
  18  * AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  20  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
  21  * USE OR OTHER DEALINGS IN THE SOFTWARE.
  22  *
  23  * The above copyright notice and this permission notice (including the
  24  * next paragraph) shall be included in all copies or substantial portions
  25  * of the Software.
  26  */
  27
  28 #ifndef AMDGPU_CS_H
  29 #define AMDGPU_CS_H
  30
  31 #include "amdgpu_bo.h"
  32 #include "util/u_memory.h"
  33 #include <amdgpu_drm.h>
  34
  35 struct amdgpu_ctx {
  36    struct amdgpu_winsys *ws;
  37    amdgpu_context_handle ctx;
  38    amdgpu_bo_handle user_fence_bo;
  39    uint64_t *user_fence_cpu_address_base;
  40    int refcount;
  41    unsigned initial_num_total_rejected_cs;
  42    unsigned num_rejected_cs;
  43 };
  44
  45 struct amdgpu_cs_buffer {
  46    struct amdgpu_winsys_bo *bo;
  47    union {
  48       struct {
  49          uint64_t priority_usage;
  50       } real;
  51       struct {
  52          uint32_t real_idx; /* index of underlying real BO */
  53       } slab;
  54    } u;
  55    enum radeon_bo_usage usage;
  56 };
  57
  58 enum ib_type {
  59    IB_MAIN,
  60    IB_NUM,
  61 };
  62
  63 struct amdgpu_ib {
  64    struct radeon_winsys_cs base;
  65
  66    /* A buffer out of which new IBs are allocated. */
  67    struct pb_buffer        *big_ib_buffer;
  68    uint8_t                 *ib_mapped;
  69    unsigned                used_ib_space;
  70    unsigned                max_ib_size;
  71    uint32_t                *ptr_ib_size;
  72    bool                    ptr_ib_size_inside_ib;
  73    enum ib_type            ib_type;
  74 };
  75
  76 struct amdgpu_cs_context {
  77    struct drm_amdgpu_cs_chunk_ib ib[IB_NUM];
  78
  79    /* Buffers. */
  80    unsigned                    max_real_buffers;
  81    unsigned                    num_real_buffers;
  82    struct amdgpu_cs_buffer     *real_buffers;
  83
  84    unsigned                    max_real_submit;
  85    amdgpu_bo_handle            *handles;
  86    uint8_t                     *flags;
  87
  88    unsigned                    num_slab_buffers;
  89    unsigned                    max_slab_buffers;
  90    struct amdgpu_cs_buffer     *slab_buffers;
  91
  92    unsigned                    num_sparse_buffers;
  93    unsigned                    max_sparse_buffers;
  94    struct amdgpu_cs_buffer     *sparse_buffers;
  95
  96    int                         buffer_indices_hashlist[4096];
  97
  98    struct amdgpu_winsys_bo     *last_added_bo;
  99    unsigned                    last_added_bo_index;
 100    unsigned                    last_added_bo_usage;
 101    uint64_t                    last_added_bo_priority_usage;
 102
 103    struct pipe_fence_handle    **fence_dependencies;
 104    unsigned                    num_fence_dependencies;
 105    unsigned                    max_fence_dependencies;
 106
 107    struct pipe_fence_handle    **syncobj_to_signal;
 108    unsigned                    num_syncobj_to_signal;
 109    unsigned                    max_syncobj_to_signal;
 110
 111    struct pipe_fence_handle    *fence;
 112
 113    /* the error returned from cs_flush for non-async submissions */
 114    int                         error_code;
 115 };
 116
 117 struct amdgpu_cs {
 118    struct amdgpu_ib main; /* must be first because this is inherited */
 119    struct amdgpu_ctx *ctx;
 120    enum ring_type ring_type;
 121    struct drm_amdgpu_cs_chunk_fence fence_chunk;
 122
 123    /* We flip between these two CS. While one is being consumed
 124     * by the kernel in another thread, the other one is being filled
 125     * by the pipe driver. */
 126    struct amdgpu_cs_context csc1;
 127    struct amdgpu_cs_context csc2;
 128    /* The currently-used CS. */
 129    struct amdgpu_cs_context *csc;
 130    /* The CS being currently-owned by the other thread. */
 131    struct amdgpu_cs_context *cst;
 132
 133    /* Flush CS. */
 134    void (*flush_cs)(void *ctx, unsigned flags, struct pipe_fence_handle **fence);
 135    void *flush_data;
 136
 137    struct util_queue_fence flush_completed;
 138    struct pipe_fence_handle *next_fence;
 139 };
 140
 141 struct amdgpu_fence {
 142    struct pipe_reference reference;
 143    /* If ctx == NULL, this fence is syncobj-based. */
 144    uint32_t syncobj;
 145
 146    struct amdgpu_winsys *ws;
 147    struct amdgpu_ctx *ctx;  /* submission context */
 148    struct amdgpu_cs_fence fence;
 149    uint64_t *user_fence_cpu_address;
 150
 151    /* If the fence has been submitted. This is unsignalled for deferred fences
 152     * (cs->next_fence) and while an IB is still being submitted in the submit
 153     * thread. */
 154    struct util_queue_fence submitted;
 155
 156    volatile int signalled;              /* bool (int for atomicity) */
 157 };
 158
 159 static inline bool amdgpu_fence_is_syncobj(struct amdgpu_fence *fence)
 160 {
 161    return fence->ctx == NULL;
 162 }
 163
 164 static inline void amdgpu_ctx_unref(struct amdgpu_ctx *ctx)
 165 {
 166    if (p_atomic_dec_zero(&ctx->refcount)) {
 167       amdgpu_cs_ctx_free(ctx->ctx);
 168       amdgpu_bo_free(ctx->user_fence_bo);
 169       FREE(ctx);
 170    }
 171 }
 172
 173 static inline void amdgpu_fence_reference(struct pipe_fence_handle **dst,
 174                                           struct pipe_fence_handle *src)
 175 {
 176    struct amdgpu_fence **rdst = (struct amdgpu_fence **)dst;
 177    struct amdgpu_fence *rsrc = (struct amdgpu_fence *)src;
 178
 179    if (pipe_reference(&(*rdst)->reference, &rsrc->reference)) {
 180       struct amdgpu_fence *fence = *rdst;
 181
 182       if (amdgpu_fence_is_syncobj(fence))
 183          amdgpu_cs_destroy_syncobj(fence->ws->dev, fence->syncobj);
 184       else
 185          amdgpu_ctx_unref(fence->ctx);
 186
 187       util_queue_fence_destroy(&fence->submitted);
 188       FREE(fence);
 189    }
 190    *rdst = rsrc;
 191 }
 192
 193 int amdgpu_lookup_buffer(struct amdgpu_cs_context *cs, struct amdgpu_winsys_bo *bo);
 194
 195 static inline struct amdgpu_ib *
 196 amdgpu_ib(struct radeon_winsys_cs *base)
 197 {
 198    return (struct amdgpu_ib *)base;
 199 }
 200
 201 static inline struct amdgpu_cs *
 202 amdgpu_cs(struct radeon_winsys_cs *base)
 203 {
 204    assert(amdgpu_ib(base)->ib_type == IB_MAIN);
 205    return (struct amdgpu_cs*)base;
 206 }
 207
 208 #define get_container(member_ptr, container_type, container_member) \
 209    (container_type *)((char *)(member_ptr) - offsetof(container_type, container_member))
 210
 211 static inline struct amdgpu_cs *
 212 amdgpu_cs_from_ib(struct amdgpu_ib *ib)
 213 {
 214    switch (ib->ib_type) {
 215    case IB_MAIN:
 216       return get_container(ib, struct amdgpu_cs, main);
 217    default:
 218       unreachable("bad ib_type");
 219    }
 220 }
 221
 222 static inline bool
 223 amdgpu_bo_is_referenced_by_cs(struct amdgpu_cs *cs,
 224                               struct amdgpu_winsys_bo *bo)
 225 {
 226    int num_refs = bo->num_cs_references;
 227    return num_refs == bo->ws->num_cs ||
 228          (num_refs && amdgpu_lookup_buffer(cs->csc, bo) != -1);
 229 }
 230
 231 static inline bool
 232 amdgpu_bo_is_referenced_by_cs_with_usage(struct amdgpu_cs *cs,
 233                                          struct amdgpu_winsys_bo *bo,
 234                                          enum radeon_bo_usage usage)
 235 {
 236    int index;
 237    struct amdgpu_cs_buffer *buffer;
 238
 239    if (!bo->num_cs_references)
 240       return false;
 241
 242    index = amdgpu_lookup_buffer(cs->csc, bo);
 243    if (index == -1)
 244       return false;
 245
 246    buffer = bo->bo ? &cs->csc->real_buffers[index] :
 247             bo->sparse ? &cs->csc->sparse_buffers[index] :
 248             &cs->csc->slab_buffers[index];
 249
 250    return (buffer->usage & usage) != 0;
 251 }
 252
 253 static inline bool
 254 amdgpu_bo_is_referenced_by_any_cs(struct amdgpu_winsys_bo *bo)
 255 {
 256    return bo->num_cs_references != 0;
 257 }
 258
 259 bool amdgpu_fence_wait(struct pipe_fence_handle *fence, uint64_t timeout,
 260                        bool absolute);
 261 void amdgpu_add_fences(struct amdgpu_winsys_bo *bo,
 262                        unsigned num_fences,
 263                        struct pipe_fence_handle **fences);
 264 void amdgpu_cs_sync_flush(struct radeon_winsys_cs *rcs);
 265 void amdgpu_cs_init_functions(struct amdgpu_winsys *ws);
 266 void amdgpu_cs_submit_ib(void *job, int thread_index);
 267
 268 #endif