src/gallium/winsys/amdgpu/drm/amdgpu_cs.h

   1 /*
   2  * Copyright © 2011 Marek Olšák <maraeo@gmail.com>
   3  * Copyright © 2015 Advanced Micro Devices, Inc.
   4  * All Rights Reserved.
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining
   7  * a copy of this software and associated documentation files (the
   8  * "Software"), to deal in the Software without restriction, including
   9  * without limitation the rights to use, copy, modify, merge, publish,
  10  * distribute, sub license, and/or sell copies of the Software, and to
  11  * permit persons to whom the Software is furnished to do so, subject to
  12  * the following conditions:
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  15  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
  16  * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  17  * NON-INFRINGEMENT. IN NO EVENT SHALL THE COPYRIGHT HOLDERS, AUTHORS
  18  * AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  20  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
  21  * USE OR OTHER DEALINGS IN THE SOFTWARE.
  22  *
  23  * The above copyright notice and this permission notice (including the
  24  * next paragraph) shall be included in all copies or substantial portions
  25  * of the Software.
  26  */
  27 /*
  28  * Authors:
  29  *      Marek Olšák <maraeo@gmail.com>
  30  */
  31
  32 #ifndef AMDGPU_CS_H
  33 #define AMDGPU_CS_H
  34
  35 #include "amdgpu_bo.h"
  36 #include "util/u_memory.h"
  37
  38 struct amdgpu_ctx {
  39    struct amdgpu_winsys *ws;
  40    amdgpu_context_handle ctx;
  41    amdgpu_bo_handle user_fence_bo;
  42    uint64_t *user_fence_cpu_address_base;
  43    int refcount;
  44 };
  45
  46 struct amdgpu_cs_buffer {
  47    struct amdgpu_winsys_bo *bo;
  48    uint64_t priority_usage;
  49    enum radeon_bo_usage usage;
  50    enum radeon_bo_domain domains;
  51 };
  52
  53 enum ib_type {
  54    IB_CONST_PREAMBLE = 0,
  55    IB_CONST = 1, /* the const IB must be first */
  56    IB_MAIN = 2,
  57    IB_NUM
  58 };
  59
  60 struct amdgpu_ib {
  61    struct radeon_winsys_cs base;
  62
  63    /* A buffer out of which new IBs are allocated. */
  64    struct pb_buffer        *big_ib_buffer;
  65    uint8_t                 *ib_mapped;
  66    unsigned                used_ib_space;
  67    enum ib_type            ib_type;
  68 };
  69
  70 struct amdgpu_cs_context {
  71    struct amdgpu_cs_request    request;
  72    struct amdgpu_cs_ib_info    ib[IB_NUM];
  73
  74    /* Buffers. */
  75    unsigned                    max_num_buffers;
  76    unsigned                    num_buffers;
  77    amdgpu_bo_handle            *handles;
  78    uint8_t                     *flags;
  79    struct amdgpu_cs_buffer     *buffers;
  80
  81    int                         buffer_indices_hashlist[4096];
  82
  83    uint64_t                    used_vram;
  84    uint64_t                    used_gart;
  85
  86    unsigned                    max_dependencies;
  87
  88    struct pipe_fence_handle    *fence;
  89 };
  90
  91 struct amdgpu_cs {
  92    struct amdgpu_ib main; /* must be first because this is inherited */
  93    struct amdgpu_ib const_ib; /* optional constant engine IB */
  94    struct amdgpu_ib const_preamble_ib;
  95    struct amdgpu_ctx *ctx;
  96    enum ring_type ring_type;
  97
  98    /* We flip between these two CS. While one is being consumed
  99     * by the kernel in another thread, the other one is being filled
 100     * by the pipe driver. */
 101    struct amdgpu_cs_context csc1;
 102    struct amdgpu_cs_context csc2;
 103    /* The currently-used CS. */
 104    struct amdgpu_cs_context *csc;
 105    /* The CS being currently-owned by the other thread. */
 106    struct amdgpu_cs_context *cst;
 107
 108    /* Flush CS. */
 109    void (*flush_cs)(void *ctx, unsigned flags, struct pipe_fence_handle **fence);
 110    void *flush_data;
 111
 112    pipe_semaphore flush_completed;
 113 };
 114
 115 struct amdgpu_fence {
 116    struct pipe_reference reference;
 117
 118    struct amdgpu_ctx *ctx;  /* submission context */
 119    struct amdgpu_cs_fence fence;
 120    uint64_t *user_fence_cpu_address;
 121
 122    /* If the fence is unknown due to an IB still being submitted
 123     * in the other thread. */
 124    volatile int submission_in_progress; /* bool (int for atomicity) */
 125    volatile int signalled;              /* bool (int for atomicity) */
 126 };
 127
 128 static inline void amdgpu_ctx_unref(struct amdgpu_ctx *ctx)
 129 {
 130    if (p_atomic_dec_zero(&ctx->refcount)) {
 131       amdgpu_cs_ctx_free(ctx->ctx);
 132       amdgpu_bo_free(ctx->user_fence_bo);
 133       FREE(ctx);
 134    }
 135 }
 136
 137 static inline void amdgpu_fence_reference(struct pipe_fence_handle **dst,
 138                                           struct pipe_fence_handle *src)
 139 {
 140    struct amdgpu_fence **rdst = (struct amdgpu_fence **)dst;
 141    struct amdgpu_fence *rsrc = (struct amdgpu_fence *)src;
 142
 143    if (pipe_reference(&(*rdst)->reference, &rsrc->reference)) {
 144       amdgpu_ctx_unref((*rdst)->ctx);
 145       FREE(*rdst);
 146    }
 147    *rdst = rsrc;
 148 }
 149
 150 int amdgpu_lookup_buffer(struct amdgpu_cs_context *cs, struct amdgpu_winsys_bo *bo);
 151
 152 static inline struct amdgpu_ib *
 153 amdgpu_ib(struct radeon_winsys_cs *base)
 154 {
 155    return (struct amdgpu_ib *)base;
 156 }
 157
 158 static inline struct amdgpu_cs *
 159 amdgpu_cs(struct radeon_winsys_cs *base)
 160 {
 161    assert(amdgpu_ib(base)->ib_type == IB_MAIN);
 162    return (struct amdgpu_cs*)base;
 163 }
 164
 165 #define get_container(member_ptr, container_type, container_member) \
 166    (container_type *)((char *)(member_ptr) - offsetof(container_type, container_member))
 167
 168 static inline struct amdgpu_cs *
 169 amdgpu_cs_from_ib(struct amdgpu_ib *ib)
 170 {
 171    switch (ib->ib_type) {
 172    case IB_MAIN:
 173       return get_container(ib, struct amdgpu_cs, main);
 174    case IB_CONST:
 175       return get_container(ib, struct amdgpu_cs, const_ib);
 176    case IB_CONST_PREAMBLE:
 177       return get_container(ib, struct amdgpu_cs, const_preamble_ib);
 178    default:
 179       unreachable("bad ib_type");
 180    }
 181 }
 182
 183 static inline boolean
 184 amdgpu_bo_is_referenced_by_cs(struct amdgpu_cs *cs,
 185                               struct amdgpu_winsys_bo *bo)
 186 {
 187    int num_refs = bo->num_cs_references;
 188    return num_refs == bo->ws->num_cs ||
 189          (num_refs && amdgpu_lookup_buffer(cs->csc, bo) != -1);
 190 }
 191
 192 static inline boolean
 193 amdgpu_bo_is_referenced_by_cs_with_usage(struct amdgpu_cs *cs,
 194                                          struct amdgpu_winsys_bo *bo,
 195                                          enum radeon_bo_usage usage)
 196 {
 197    int index;
 198
 199    if (!bo->num_cs_references)
 200       return FALSE;
 201
 202    index = amdgpu_lookup_buffer(cs->csc, bo);
 203    if (index == -1)
 204       return FALSE;
 205
 206    return (cs->csc->buffers[index].usage & usage) != 0;
 207 }
 208
 209 static inline boolean
 210 amdgpu_bo_is_referenced_by_any_cs(struct amdgpu_winsys_bo *bo)
 211 {
 212    return bo->num_cs_references != 0;
 213 }
 214
 215 bool amdgpu_fence_wait(struct pipe_fence_handle *fence, uint64_t timeout,
 216                        bool absolute);
 217 void amdgpu_cs_sync_flush(struct radeon_winsys_cs *rcs);
 218 void amdgpu_cs_init_functions(struct amdgpu_winsys *ws);
 219 void amdgpu_cs_submit_ib(struct amdgpu_cs *cs);
 220
 221 #endif