src/gallium/winsys/amdgpu/drm/amdgpu_surface.c

   1 /*
   2  * Copyright © 2011 Red Hat All Rights Reserved.
   3  * Copyright © 2014 Advanced Micro Devices, Inc.
   4  * All Rights Reserved.
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining
   7  * a copy of this software and associated documentation files (the
   8  * "Software"), to deal in the Software without restriction, including
   9  * without limitation the rights to use, copy, modify, merge, publish,
  10  * distribute, sub license, and/or sell copies of the Software, and to
  11  * permit persons to whom the Software is furnished to do so, subject to
  12  * the following conditions:
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  15  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
  16  * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  17  * NON-INFRINGEMENT. IN NO EVENT SHALL THE COPYRIGHT HOLDERS, AUTHORS
  18  * AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  20  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
  21  * USE OR OTHER DEALINGS IN THE SOFTWARE.
  22  *
  23  * The above copyright notice and this permission notice (including the
  24  * next paragraph) shall be included in all copies or substantial portions
  25  * of the Software.
  26  */
  27
  28 /* Contact:
  29  *     Marek Olšák <maraeo@gmail.com>
  30  */
  31
  32 #include "amdgpu_winsys.h"
  33
  34 #ifndef NO_ENTRIES
  35 #define NO_ENTRIES 32
  36 #endif
  37
  38 #ifndef NO_MACRO_ENTRIES
  39 #define NO_MACRO_ENTRIES 16
  40 #endif
  41
  42 #ifndef CIASICIDGFXENGINE_SOUTHERNISLAND
  43 #define CIASICIDGFXENGINE_SOUTHERNISLAND 0x0000000A
  44 #endif
  45
  46
  47 static int amdgpu_surface_sanity(const struct radeon_surf *surf)
  48 {
  49    unsigned type = RADEON_SURF_GET(surf->flags, TYPE);
  50
  51    if (!(surf->flags & RADEON_SURF_HAS_TILE_MODE_INDEX))
  52       return -EINVAL;
  53
  54    /* all dimension must be at least 1 ! */
  55    if (!surf->npix_x || !surf->npix_y || !surf->npix_z ||
  56        !surf->array_size)
  57       return -EINVAL;
  58
  59    if (!surf->blk_w || !surf->blk_h || !surf->blk_d)
  60       return -EINVAL;
  61
  62    switch (surf->nsamples) {
  63    case 1:
  64    case 2:
  65    case 4:
  66    case 8:
  67       break;
  68    default:
  69       return -EINVAL;
  70    }
  71
  72    switch (type) {
  73    case RADEON_SURF_TYPE_1D:
  74       if (surf->npix_y > 1)
  75          return -EINVAL;
  76       /* fall through */
  77    case RADEON_SURF_TYPE_2D:
  78    case RADEON_SURF_TYPE_CUBEMAP:
  79       if (surf->npix_z > 1 || surf->array_size > 1)
  80          return -EINVAL;
  81       break;
  82    case RADEON_SURF_TYPE_3D:
  83       if (surf->array_size > 1)
  84          return -EINVAL;
  85       break;
  86    case RADEON_SURF_TYPE_1D_ARRAY:
  87       if (surf->npix_y > 1)
  88          return -EINVAL;
  89       /* fall through */
  90    case RADEON_SURF_TYPE_2D_ARRAY:
  91       if (surf->npix_z > 1)
  92          return -EINVAL;
  93       break;
  94    default:
  95       return -EINVAL;
  96    }
  97    return 0;
  98 }
  99
 100 static void *ADDR_API allocSysMem(const ADDR_ALLOCSYSMEM_INPUT * pInput)
 101 {
 102    return malloc(pInput->sizeInBytes);
 103 }
 104
 105 static ADDR_E_RETURNCODE ADDR_API freeSysMem(const ADDR_FREESYSMEM_INPUT * pInput)
 106 {
 107    free(pInput->pVirtAddr);
 108    return ADDR_OK;
 109 }
 110
 111 ADDR_HANDLE amdgpu_addr_create(struct amdgpu_winsys *ws)
 112 {
 113    ADDR_CREATE_INPUT addrCreateInput = {0};
 114    ADDR_CREATE_OUTPUT addrCreateOutput = {0};
 115    ADDR_REGISTER_VALUE regValue = {0};
 116    ADDR_CREATE_FLAGS createFlags = {{0}};
 117    ADDR_E_RETURNCODE addrRet;
 118
 119    addrCreateInput.size = sizeof(ADDR_CREATE_INPUT);
 120    addrCreateOutput.size = sizeof(ADDR_CREATE_OUTPUT);
 121
 122    regValue.noOfBanks = ws->amdinfo.mc_arb_ramcfg & 0x3;
 123    regValue.gbAddrConfig = ws->amdinfo.gb_addr_cfg;
 124    regValue.noOfRanks = (ws->amdinfo.mc_arb_ramcfg & 0x4) >> 2;
 125
 126    regValue.backendDisables = ws->amdinfo.backend_disable[0];
 127    regValue.pTileConfig = ws->amdinfo.gb_tile_mode;
 128    regValue.noOfEntries = ARRAY_SIZE(ws->amdinfo.gb_tile_mode);
 129    if (ws->info.chip_class == SI) {
 130       regValue.pMacroTileConfig = NULL;
 131       regValue.noOfMacroEntries = 0;
 132    } else {
 133       regValue.pMacroTileConfig = ws->amdinfo.gb_macro_tile_mode;
 134       regValue.noOfMacroEntries = ARRAY_SIZE(ws->amdinfo.gb_macro_tile_mode);
 135    }
 136
 137    createFlags.value = 0;
 138    createFlags.useTileIndex = 1;
 139    createFlags.degradeBaseLevel = 1;
 140
 141    addrCreateInput.chipEngine = CIASICIDGFXENGINE_SOUTHERNISLAND;
 142    addrCreateInput.chipFamily = ws->family;
 143    addrCreateInput.chipRevision = ws->rev_id;
 144    addrCreateInput.createFlags = createFlags;
 145    addrCreateInput.callbacks.allocSysMem = allocSysMem;
 146    addrCreateInput.callbacks.freeSysMem = freeSysMem;
 147    addrCreateInput.callbacks.debugPrint = 0;
 148    addrCreateInput.regValue = regValue;
 149
 150    addrRet = AddrCreate(&addrCreateInput, &addrCreateOutput);
 151    if (addrRet != ADDR_OK)
 152       return NULL;
 153
 154    return addrCreateOutput.hLib;
 155 }
 156
 157 static int compute_level(struct amdgpu_winsys *ws,
 158                          struct radeon_surf *surf, bool is_stencil,
 159                          unsigned level, unsigned type, bool compressed,
 160                          ADDR_COMPUTE_SURFACE_INFO_INPUT *AddrSurfInfoIn,
 161                          ADDR_COMPUTE_SURFACE_INFO_OUTPUT *AddrSurfInfoOut,
 162                          ADDR_COMPUTE_DCCINFO_INPUT *AddrDccIn,
 163                          ADDR_COMPUTE_DCCINFO_OUTPUT *AddrDccOut)
 164 {
 165    struct radeon_surf_level *surf_level;
 166    ADDR_E_RETURNCODE ret;
 167
 168    AddrSurfInfoIn->mipLevel = level;
 169    AddrSurfInfoIn->width = u_minify(surf->npix_x, level);
 170    AddrSurfInfoIn->height = u_minify(surf->npix_y, level);
 171
 172    if (type == RADEON_SURF_TYPE_3D)
 173       AddrSurfInfoIn->numSlices = u_minify(surf->npix_z, level);
 174    else if (type == RADEON_SURF_TYPE_CUBEMAP)
 175       AddrSurfInfoIn->numSlices = 6;
 176    else
 177       AddrSurfInfoIn->numSlices = surf->array_size;
 178
 179    if (level > 0) {
 180       /* Set the base level pitch. This is needed for calculation
 181        * of non-zero levels. */
 182       if (is_stencil)
 183          AddrSurfInfoIn->basePitch = surf->stencil_level[0].nblk_x;
 184       else
 185          AddrSurfInfoIn->basePitch = surf->level[0].nblk_x;
 186
 187       /* Convert blocks to pixels for compressed formats. */
 188       if (compressed)
 189          AddrSurfInfoIn->basePitch *= surf->blk_w;
 190    }
 191
 192    ret = AddrComputeSurfaceInfo(ws->addrlib,
 193                                 AddrSurfInfoIn,
 194                                 AddrSurfInfoOut);
 195    if (ret != ADDR_OK) {
 196       return ret;
 197    }
 198
 199    surf_level = is_stencil ? &surf->stencil_level[level] : &surf->level[level];
 200    surf_level->offset = align64(surf->bo_size, AddrSurfInfoOut->baseAlign);
 201    surf_level->slice_size = AddrSurfInfoOut->sliceSize;
 202    surf_level->pitch_bytes = AddrSurfInfoOut->pitch * (is_stencil ? 1 : surf->bpe);
 203    surf_level->npix_x = u_minify(surf->npix_x, level);
 204    surf_level->npix_y = u_minify(surf->npix_y, level);
 205    surf_level->npix_z = u_minify(surf->npix_z, level);
 206    surf_level->nblk_x = AddrSurfInfoOut->pitch;
 207    surf_level->nblk_y = AddrSurfInfoOut->height;
 208    if (type == RADEON_SURF_TYPE_3D)
 209       surf_level->nblk_z = AddrSurfInfoOut->depth;
 210    else
 211       surf_level->nblk_z = 1;
 212
 213    switch (AddrSurfInfoOut->tileMode) {
 214    case ADDR_TM_LINEAR_ALIGNED:
 215       surf_level->mode = RADEON_SURF_MODE_LINEAR_ALIGNED;
 216       break;
 217    case ADDR_TM_1D_TILED_THIN1:
 218       surf_level->mode = RADEON_SURF_MODE_1D;
 219       break;
 220    case ADDR_TM_2D_TILED_THIN1:
 221       surf_level->mode = RADEON_SURF_MODE_2D;
 222       break;
 223    default:
 224       assert(0);
 225    }
 226
 227    if (is_stencil)
 228       surf->stencil_tiling_index[level] = AddrSurfInfoOut->tileIndex;
 229    else
 230       surf->tiling_index[level] = AddrSurfInfoOut->tileIndex;
 231
 232    surf->bo_size = surf_level->offset + AddrSurfInfoOut->surfSize;
 233
 234    /* Clear DCC fields at the beginning. */
 235    surf_level->dcc_offset = 0;
 236    surf_level->dcc_enabled = false;
 237
 238    /* The previous level's flag tells us if we can use DCC for this level. */
 239    if (AddrSurfInfoIn->flags.dccCompatible &&
 240        (level == 0 || AddrDccOut->subLvlCompressible)) {
 241       AddrDccIn->colorSurfSize = AddrSurfInfoOut->surfSize;
 242       AddrDccIn->tileMode = AddrSurfInfoOut->tileMode;
 243       AddrDccIn->tileInfo = *AddrSurfInfoOut->pTileInfo;
 244       AddrDccIn->tileIndex = AddrSurfInfoOut->tileIndex;
 245       AddrDccIn->macroModeIndex = AddrSurfInfoOut->macroModeIndex;
 246
 247       ret = AddrComputeDccInfo(ws->addrlib,
 248                                AddrDccIn,
 249                                AddrDccOut);
 250
 251       if (ret == ADDR_OK) {
 252          surf_level->dcc_offset = surf->dcc_size;
 253          surf_level->dcc_fast_clear_size = AddrDccOut->dccFastClearSize;
 254          surf_level->dcc_enabled = true;
 255          surf->dcc_size = surf_level->dcc_offset + AddrDccOut->dccRamSize;
 256          surf->dcc_alignment = MAX2(surf->dcc_alignment, AddrDccOut->dccRamBaseAlign);
 257       }
 258    }
 259
 260    return 0;
 261 }
 262
 263 #define   G_009910_MICRO_TILE_MODE(x)          (((x) >> 0) & 0x03)
 264 #define   G_009910_MICRO_TILE_MODE_NEW(x)      (((x) >> 22) & 0x07)
 265
 266 static void set_micro_tile_mode(struct radeon_surf *surf,
 267                                 struct radeon_info *info)
 268 {
 269    uint32_t tile_mode = info->si_tile_mode_array[surf->tiling_index[0]];
 270
 271    if (info->chip_class >= CIK)
 272       surf->micro_tile_mode = G_009910_MICRO_TILE_MODE_NEW(tile_mode);
 273    else
 274       surf->micro_tile_mode = G_009910_MICRO_TILE_MODE(tile_mode);
 275 }
 276
 277 static int amdgpu_surface_init(struct radeon_winsys *rws,
 278                                struct radeon_surf *surf)
 279 {
 280    struct amdgpu_winsys *ws = (struct amdgpu_winsys*)rws;
 281    unsigned level, mode, type;
 282    bool compressed;
 283    ADDR_COMPUTE_SURFACE_INFO_INPUT AddrSurfInfoIn = {0};
 284    ADDR_COMPUTE_SURFACE_INFO_OUTPUT AddrSurfInfoOut = {0};
 285    ADDR_COMPUTE_DCCINFO_INPUT AddrDccIn = {0};
 286    ADDR_COMPUTE_DCCINFO_OUTPUT AddrDccOut = {0};
 287    ADDR_TILEINFO AddrTileInfoIn = {0};
 288    ADDR_TILEINFO AddrTileInfoOut = {0};
 289    int r;
 290
 291    r = amdgpu_surface_sanity(surf);
 292    if (r)
 293       return r;
 294
 295    AddrSurfInfoIn.size = sizeof(ADDR_COMPUTE_SURFACE_INFO_INPUT);
 296    AddrSurfInfoOut.size = sizeof(ADDR_COMPUTE_SURFACE_INFO_OUTPUT);
 297    AddrDccIn.size = sizeof(ADDR_COMPUTE_DCCINFO_INPUT);
 298    AddrDccOut.size = sizeof(ADDR_COMPUTE_DCCINFO_OUTPUT);
 299    AddrSurfInfoOut.pTileInfo = &AddrTileInfoOut;
 300
 301    type = RADEON_SURF_GET(surf->flags, TYPE);
 302    mode = RADEON_SURF_GET(surf->flags, MODE);
 303    compressed = surf->blk_w == 4 && surf->blk_h == 4;
 304
 305    /* MSAA and FMASK require 2D tiling. */
 306    if (surf->nsamples > 1 ||
 307        (surf->flags & RADEON_SURF_FMASK))
 308       mode = RADEON_SURF_MODE_2D;
 309
 310    /* DB doesn't support linear layouts. */
 311    if (surf->flags & (RADEON_SURF_Z_OR_SBUFFER) &&
 312        mode < RADEON_SURF_MODE_1D)
 313       mode = RADEON_SURF_MODE_1D;
 314
 315    /* Set the requested tiling mode. */
 316    switch (mode) {
 317    case RADEON_SURF_MODE_LINEAR_ALIGNED:
 318       AddrSurfInfoIn.tileMode = ADDR_TM_LINEAR_ALIGNED;
 319       break;
 320    case RADEON_SURF_MODE_1D:
 321       AddrSurfInfoIn.tileMode = ADDR_TM_1D_TILED_THIN1;
 322       break;
 323    case RADEON_SURF_MODE_2D:
 324       AddrSurfInfoIn.tileMode = ADDR_TM_2D_TILED_THIN1;
 325       break;
 326    default:
 327       assert(0);
 328    }
 329
 330    /* The format must be set correctly for the allocation of compressed
 331     * textures to work. In other cases, setting the bpp is sufficient. */
 332    if (compressed) {
 333       switch (surf->bpe) {
 334       case 8:
 335          AddrSurfInfoIn.format = ADDR_FMT_BC1;
 336          break;
 337       case 16:
 338          AddrSurfInfoIn.format = ADDR_FMT_BC3;
 339          break;
 340       default:
 341          assert(0);
 342       }
 343    }
 344    else {
 345       AddrDccIn.bpp = AddrSurfInfoIn.bpp = surf->bpe * 8;
 346    }
 347
 348    AddrDccIn.numSamples = AddrSurfInfoIn.numSamples = surf->nsamples;
 349    AddrSurfInfoIn.tileIndex = -1;
 350
 351    /* Set the micro tile type. */
 352    if (surf->flags & RADEON_SURF_SCANOUT)
 353       AddrSurfInfoIn.tileType = ADDR_DISPLAYABLE;
 354    else if (surf->flags & RADEON_SURF_Z_OR_SBUFFER)
 355       AddrSurfInfoIn.tileType = ADDR_DEPTH_SAMPLE_ORDER;
 356    else
 357       AddrSurfInfoIn.tileType = ADDR_NON_DISPLAYABLE;
 358
 359    AddrSurfInfoIn.flags.color = !(surf->flags & RADEON_SURF_Z_OR_SBUFFER);
 360    AddrSurfInfoIn.flags.depth = (surf->flags & RADEON_SURF_ZBUFFER) != 0;
 361    AddrSurfInfoIn.flags.cube = type == RADEON_SURF_TYPE_CUBEMAP;
 362    AddrSurfInfoIn.flags.display = (surf->flags & RADEON_SURF_SCANOUT) != 0;
 363    AddrSurfInfoIn.flags.pow2Pad = surf->last_level > 0;
 364    AddrSurfInfoIn.flags.degrade4Space = 1;
 365
 366    /* DCC notes:
 367     * - If we add MSAA support, keep in mind that CB can't decompress 8bpp
 368     *   with samples >= 4.
 369     * - Mipmapped array textures have low performance (discovered by a closed
 370     *   driver team).
 371     */
 372    AddrSurfInfoIn.flags.dccCompatible = ws->info.chip_class >= VI &&
 373                                         !(surf->flags & RADEON_SURF_Z_OR_SBUFFER) &&
 374                                         !(surf->flags & RADEON_SURF_DISABLE_DCC) &&
 375                                         !compressed && AddrDccIn.numSamples <= 1 &&
 376                                         ((surf->array_size == 1 && surf->npix_z == 1) ||
 377                                          surf->last_level == 0);
 378
 379    AddrSurfInfoIn.flags.noStencil = (surf->flags & RADEON_SURF_SBUFFER) == 0;
 380    AddrSurfInfoIn.flags.compressZ = AddrSurfInfoIn.flags.depth;
 381
 382    /* noStencil = 0 can result in a depth part that is incompatible with
 383     * mipmapped texturing. So set noStencil = 1 when mipmaps are requested (in
 384     * this case, we may end up setting stencil_adjusted).
 385     *
 386     * TODO: update addrlib to a newer version, remove this, and
 387     * use flags.matchStencilTileCfg = 1 as an alternative fix.
 388     */
 389   if (surf->last_level > 0)
 390       AddrSurfInfoIn.flags.noStencil = 1;
 391
 392    /* Set preferred macrotile parameters. This is usually required
 393     * for shared resources. This is for 2D tiling only. */
 394    if (AddrSurfInfoIn.tileMode >= ADDR_TM_2D_TILED_THIN1 &&
 395        surf->bankw && surf->bankh && surf->mtilea && surf->tile_split) {
 396       /* If any of these parameters are incorrect, the calculation
 397        * will fail. */
 398       AddrTileInfoIn.banks = surf->num_banks;
 399       AddrTileInfoIn.bankWidth = surf->bankw;
 400       AddrTileInfoIn.bankHeight = surf->bankh;
 401       AddrTileInfoIn.macroAspectRatio = surf->mtilea;
 402       AddrTileInfoIn.tileSplitBytes = surf->tile_split;
 403       AddrTileInfoIn.pipeConfig = surf->pipe_config + 1; /* +1 compared to GB_TILE_MODE */
 404       AddrSurfInfoIn.flags.degrade4Space = 0;
 405       AddrSurfInfoIn.pTileInfo = &AddrTileInfoIn;
 406
 407       /* If AddrSurfInfoIn.pTileInfo is set, Addrlib doesn't set
 408        * the tile index, because we are expected to know it if
 409        * we know the other parameters.
 410        *
 411        * This is something that can easily be fixed in Addrlib.
 412        * For now, just figure it out here.
 413        * Note that only 2D_TILE_THIN1 is handled here.
 414        */
 415       assert(!(surf->flags & RADEON_SURF_Z_OR_SBUFFER));
 416       assert(AddrSurfInfoIn.tileMode == ADDR_TM_2D_TILED_THIN1);
 417
 418       if (ws->info.chip_class == SI) {
 419          if (AddrSurfInfoIn.tileType == ADDR_DISPLAYABLE) {
 420             if (surf->bpe == 2)
 421                AddrSurfInfoIn.tileIndex = 11; /* 16bpp */
 422             else
 423                AddrSurfInfoIn.tileIndex = 12; /* 32bpp */
 424          } else {
 425             if (surf->bpe == 1)
 426                AddrSurfInfoIn.tileIndex = 14; /* 8bpp */
 427             else if (surf->bpe == 2)
 428                AddrSurfInfoIn.tileIndex = 15; /* 16bpp */
 429             else if (surf->bpe == 4)
 430                AddrSurfInfoIn.tileIndex = 16; /* 32bpp */
 431             else
 432                AddrSurfInfoIn.tileIndex = 17; /* 64bpp (and 128bpp) */
 433          }
 434       } else {
 435          /* CIK - VI */
 436          if (AddrSurfInfoIn.tileType == ADDR_DISPLAYABLE)
 437             AddrSurfInfoIn.tileIndex = 10; /* 2D displayable */
 438          else
 439             AddrSurfInfoIn.tileIndex = 14; /* 2D non-displayable */
 440       }
 441    }
 442
 443    surf->bo_size = 0;
 444    surf->dcc_size = 0;
 445    surf->dcc_alignment = 1;
 446
 447    /* Calculate texture layout information. */
 448    for (level = 0; level <= surf->last_level; level++) {
 449       r = compute_level(ws, surf, false, level, type, compressed,
 450                         &AddrSurfInfoIn, &AddrSurfInfoOut, &AddrDccIn, &AddrDccOut);
 451       if (r)
 452          return r;
 453
 454       if (level == 0) {
 455          surf->bo_alignment = AddrSurfInfoOut.baseAlign;
 456          surf->pipe_config = AddrSurfInfoOut.pTileInfo->pipeConfig - 1;
 457          set_micro_tile_mode(surf, &ws->info);
 458
 459          /* For 2D modes only. */
 460          if (AddrSurfInfoOut.tileMode >= ADDR_TM_2D_TILED_THIN1) {
 461             surf->bankw = AddrSurfInfoOut.pTileInfo->bankWidth;
 462             surf->bankh = AddrSurfInfoOut.pTileInfo->bankHeight;
 463             surf->mtilea = AddrSurfInfoOut.pTileInfo->macroAspectRatio;
 464             surf->tile_split = AddrSurfInfoOut.pTileInfo->tileSplitBytes;
 465             surf->num_banks = AddrSurfInfoOut.pTileInfo->banks;
 466             surf->macro_tile_index = AddrSurfInfoOut.macroModeIndex;
 467          } else {
 468             surf->macro_tile_index = 0;
 469          }
 470       }
 471    }
 472
 473    /* Calculate texture layout information for stencil. */
 474    if (surf->flags & RADEON_SURF_SBUFFER) {
 475       AddrSurfInfoIn.bpp = 8;
 476       AddrSurfInfoIn.flags.depth = 0;
 477       AddrSurfInfoIn.flags.stencil = 1;
 478       /* This will be ignored if AddrSurfInfoIn.pTileInfo is NULL. */
 479       AddrTileInfoIn.tileSplitBytes = surf->stencil_tile_split;
 480
 481       for (level = 0; level <= surf->last_level; level++) {
 482          r = compute_level(ws, surf, true, level, type, compressed,
 483                            &AddrSurfInfoIn, &AddrSurfInfoOut, &AddrDccIn, &AddrDccOut);
 484          if (r)
 485             return r;
 486
 487          /* DB uses the depth pitch for both stencil and depth. */
 488          if (surf->stencil_level[level].nblk_x != surf->level[level].nblk_x)
 489             surf->stencil_adjusted = true;
 490
 491          if (level == 0) {
 492             /* For 2D modes only. */
 493             if (AddrSurfInfoOut.tileMode >= ADDR_TM_2D_TILED_THIN1) {
 494                surf->stencil_tile_split =
 495                      AddrSurfInfoOut.pTileInfo->tileSplitBytes;
 496             }
 497          }
 498       }
 499    }
 500
 501    /* Recalculate the whole DCC miptree size including disabled levels.
 502     * This is what addrlib does, but calling addrlib would be a lot more
 503     * complicated.
 504     */
 505    if (surf->dcc_size && surf->last_level > 0) {
 506       surf->dcc_size = align64(surf->bo_size >> 8,
 507                                ws->info.pipe_interleave_bytes *
 508                                ws->info.num_tile_pipes);
 509    }
 510
 511    return 0;
 512 }
 513
 514 static int amdgpu_surface_best(struct radeon_winsys *rws,
 515                                struct radeon_surf *surf)
 516 {
 517    return 0;
 518 }
 519
 520 void amdgpu_surface_init_functions(struct amdgpu_winsys *ws)
 521 {
 522    ws->base.surface_init = amdgpu_surface_init;
 523    ws->base.surface_best = amdgpu_surface_best;
 524 }