src/gallium/winsys/amdgpu/drm/amdgpu_surface.c

   1 /*
   2  * Copyright © 2011 Red Hat All Rights Reserved.
   3  * Copyright © 2014 Advanced Micro Devices, Inc.
   4  * All Rights Reserved.
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining
   7  * a copy of this software and associated documentation files (the
   8  * "Software"), to deal in the Software without restriction, including
   9  * without limitation the rights to use, copy, modify, merge, publish,
  10  * distribute, sub license, and/or sell copies of the Software, and to
  11  * permit persons to whom the Software is furnished to do so, subject to
  12  * the following conditions:
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  15  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
  16  * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  17  * NON-INFRINGEMENT. IN NO EVENT SHALL THE COPYRIGHT HOLDERS, AUTHORS
  18  * AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  20  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
  21  * USE OR OTHER DEALINGS IN THE SOFTWARE.
  22  *
  23  * The above copyright notice and this permission notice (including the
  24  * next paragraph) shall be included in all copies or substantial portions
  25  * of the Software.
  26  */
  27
  28 /* Contact:
  29  *     Marek Olšák <maraeo@gmail.com>
  30  */
  31
  32 #include "amdgpu_winsys.h"
  33 #include "util/u_format.h"
  34
  35 #ifndef CIASICIDGFXENGINE_SOUTHERNISLAND
  36 #define CIASICIDGFXENGINE_SOUTHERNISLAND 0x0000000A
  37 #endif
  38
  39
  40 static int amdgpu_surface_sanity(const struct pipe_resource *tex)
  41 {
  42    /* all dimension must be at least 1 ! */
  43    if (!tex->width0 || !tex->height0 || !tex->depth0 ||
  44        !tex->array_size)
  45       return -EINVAL;
  46
  47    switch (tex->nr_samples) {
  48    case 0:
  49    case 1:
  50    case 2:
  51    case 4:
  52    case 8:
  53       break;
  54    default:
  55       return -EINVAL;
  56    }
  57
  58    switch (tex->target) {
  59    case PIPE_TEXTURE_1D:
  60       if (tex->height0 > 1)
  61          return -EINVAL;
  62       /* fall through */
  63    case PIPE_TEXTURE_2D:
  64    case PIPE_TEXTURE_RECT:
  65       if (tex->depth0 > 1 || tex->array_size > 1)
  66          return -EINVAL;
  67       break;
  68    case PIPE_TEXTURE_3D:
  69       if (tex->array_size > 1)
  70          return -EINVAL;
  71       break;
  72    case PIPE_TEXTURE_1D_ARRAY:
  73       if (tex->height0 > 1)
  74          return -EINVAL;
  75       /* fall through */
  76    case PIPE_TEXTURE_CUBE:
  77    case PIPE_TEXTURE_2D_ARRAY:
  78    case PIPE_TEXTURE_CUBE_ARRAY:
  79       if (tex->depth0 > 1)
  80          return -EINVAL;
  81       break;
  82    default:
  83       return -EINVAL;
  84    }
  85    return 0;
  86 }
  87
  88 static void *ADDR_API allocSysMem(const ADDR_ALLOCSYSMEM_INPUT * pInput)
  89 {
  90    return malloc(pInput->sizeInBytes);
  91 }
  92
  93 static ADDR_E_RETURNCODE ADDR_API freeSysMem(const ADDR_FREESYSMEM_INPUT * pInput)
  94 {
  95    free(pInput->pVirtAddr);
  96    return ADDR_OK;
  97 }
  98
  99 ADDR_HANDLE amdgpu_addr_create(struct amdgpu_winsys *ws)
 100 {
 101    ADDR_CREATE_INPUT addrCreateInput = {0};
 102    ADDR_CREATE_OUTPUT addrCreateOutput = {0};
 103    ADDR_REGISTER_VALUE regValue = {0};
 104    ADDR_CREATE_FLAGS createFlags = {{0}};
 105    ADDR_E_RETURNCODE addrRet;
 106
 107    addrCreateInput.size = sizeof(ADDR_CREATE_INPUT);
 108    addrCreateOutput.size = sizeof(ADDR_CREATE_OUTPUT);
 109
 110    regValue.noOfBanks = ws->amdinfo.mc_arb_ramcfg & 0x3;
 111    regValue.gbAddrConfig = ws->amdinfo.gb_addr_cfg;
 112    regValue.noOfRanks = (ws->amdinfo.mc_arb_ramcfg & 0x4) >> 2;
 113
 114    regValue.backendDisables = ws->amdinfo.backend_disable[0];
 115    regValue.pTileConfig = ws->amdinfo.gb_tile_mode;
 116    regValue.noOfEntries = ARRAY_SIZE(ws->amdinfo.gb_tile_mode);
 117    if (ws->info.chip_class == SI) {
 118       regValue.pMacroTileConfig = NULL;
 119       regValue.noOfMacroEntries = 0;
 120    } else {
 121       regValue.pMacroTileConfig = ws->amdinfo.gb_macro_tile_mode;
 122       regValue.noOfMacroEntries = ARRAY_SIZE(ws->amdinfo.gb_macro_tile_mode);
 123    }
 124
 125    createFlags.value = 0;
 126    createFlags.useTileIndex = 1;
 127    createFlags.degradeBaseLevel = 1;
 128    createFlags.useHtileSliceAlign = 1;
 129
 130    addrCreateInput.chipEngine = CIASICIDGFXENGINE_SOUTHERNISLAND;
 131    addrCreateInput.chipFamily = ws->family;
 132    addrCreateInput.chipRevision = ws->rev_id;
 133    addrCreateInput.createFlags = createFlags;
 134    addrCreateInput.callbacks.allocSysMem = allocSysMem;
 135    addrCreateInput.callbacks.freeSysMem = freeSysMem;
 136    addrCreateInput.callbacks.debugPrint = 0;
 137    addrCreateInput.regValue = regValue;
 138
 139    addrRet = AddrCreate(&addrCreateInput, &addrCreateOutput);
 140    if (addrRet != ADDR_OK)
 141       return NULL;
 142
 143    return addrCreateOutput.hLib;
 144 }
 145
 146 static int compute_level(struct amdgpu_winsys *ws,
 147                          const struct pipe_resource *tex,
 148                          struct radeon_surf *surf, bool is_stencil,
 149                          unsigned level, bool compressed,
 150                          ADDR_COMPUTE_SURFACE_INFO_INPUT *AddrSurfInfoIn,
 151                          ADDR_COMPUTE_SURFACE_INFO_OUTPUT *AddrSurfInfoOut,
 152                          ADDR_COMPUTE_DCCINFO_INPUT *AddrDccIn,
 153                          ADDR_COMPUTE_DCCINFO_OUTPUT *AddrDccOut,
 154                          ADDR_COMPUTE_HTILE_INFO_INPUT *AddrHtileIn,
 155                          ADDR_COMPUTE_HTILE_INFO_OUTPUT *AddrHtileOut)
 156 {
 157    struct radeon_surf_level *surf_level;
 158    ADDR_E_RETURNCODE ret;
 159
 160    AddrSurfInfoIn->mipLevel = level;
 161    AddrSurfInfoIn->width = u_minify(tex->width0, level);
 162    AddrSurfInfoIn->height = u_minify(tex->height0, level);
 163
 164    if (tex->target == PIPE_TEXTURE_3D)
 165       AddrSurfInfoIn->numSlices = u_minify(tex->depth0, level);
 166    else if (tex->target == PIPE_TEXTURE_CUBE)
 167       AddrSurfInfoIn->numSlices = 6;
 168    else
 169       AddrSurfInfoIn->numSlices = tex->array_size;
 170
 171    if (level > 0) {
 172       /* Set the base level pitch. This is needed for calculation
 173        * of non-zero levels. */
 174       if (is_stencil)
 175          AddrSurfInfoIn->basePitch = surf->stencil_level[0].nblk_x;
 176       else
 177          AddrSurfInfoIn->basePitch = surf->level[0].nblk_x;
 178
 179       /* Convert blocks to pixels for compressed formats. */
 180       if (compressed)
 181          AddrSurfInfoIn->basePitch *= surf->blk_w;
 182    }
 183
 184    ret = AddrComputeSurfaceInfo(ws->addrlib,
 185                                 AddrSurfInfoIn,
 186                                 AddrSurfInfoOut);
 187    if (ret != ADDR_OK) {
 188       return ret;
 189    }
 190
 191    surf_level = is_stencil ? &surf->stencil_level[level] : &surf->level[level];
 192    surf_level->offset = align64(surf->surf_size, AddrSurfInfoOut->baseAlign);
 193    surf_level->slice_size = AddrSurfInfoOut->sliceSize;
 194    surf_level->pitch_bytes = AddrSurfInfoOut->pitch * (is_stencil ? 1 : surf->bpe);
 195    surf_level->nblk_x = AddrSurfInfoOut->pitch;
 196    surf_level->nblk_y = AddrSurfInfoOut->height;
 197
 198    switch (AddrSurfInfoOut->tileMode) {
 199    case ADDR_TM_LINEAR_ALIGNED:
 200       surf_level->mode = RADEON_SURF_MODE_LINEAR_ALIGNED;
 201       break;
 202    case ADDR_TM_1D_TILED_THIN1:
 203       surf_level->mode = RADEON_SURF_MODE_1D;
 204       break;
 205    case ADDR_TM_2D_TILED_THIN1:
 206       surf_level->mode = RADEON_SURF_MODE_2D;
 207       break;
 208    default:
 209       assert(0);
 210    }
 211
 212    if (is_stencil)
 213       surf->stencil_tiling_index[level] = AddrSurfInfoOut->tileIndex;
 214    else
 215       surf->tiling_index[level] = AddrSurfInfoOut->tileIndex;
 216
 217    surf->surf_size = surf_level->offset + AddrSurfInfoOut->surfSize;
 218
 219    /* Clear DCC fields at the beginning. */
 220    surf_level->dcc_offset = 0;
 221
 222    /* The previous level's flag tells us if we can use DCC for this level. */
 223    if (AddrSurfInfoIn->flags.dccCompatible &&
 224        (level == 0 || AddrDccOut->subLvlCompressible)) {
 225       AddrDccIn->colorSurfSize = AddrSurfInfoOut->surfSize;
 226       AddrDccIn->tileMode = AddrSurfInfoOut->tileMode;
 227       AddrDccIn->tileInfo = *AddrSurfInfoOut->pTileInfo;
 228       AddrDccIn->tileIndex = AddrSurfInfoOut->tileIndex;
 229       AddrDccIn->macroModeIndex = AddrSurfInfoOut->macroModeIndex;
 230
 231       ret = AddrComputeDccInfo(ws->addrlib,
 232                                AddrDccIn,
 233                                AddrDccOut);
 234
 235       if (ret == ADDR_OK) {
 236          surf_level->dcc_offset = surf->dcc_size;
 237          surf_level->dcc_fast_clear_size = AddrDccOut->dccFastClearSize;
 238          surf->num_dcc_levels = level + 1;
 239          surf->dcc_size = surf_level->dcc_offset + AddrDccOut->dccRamSize;
 240          surf->dcc_alignment = MAX2(surf->dcc_alignment, AddrDccOut->dccRamBaseAlign);
 241       }
 242    }
 243
 244    /* TC-compatible HTILE. */
 245    if (!is_stencil &&
 246        AddrSurfInfoIn->flags.depth &&
 247        AddrSurfInfoIn->flags.tcCompatible &&
 248        surf_level->mode == RADEON_SURF_MODE_2D &&
 249        level == 0) {
 250       AddrHtileIn->flags.tcCompatible = 1;
 251       AddrHtileIn->pitch = AddrSurfInfoOut->pitch;
 252       AddrHtileIn->height = AddrSurfInfoOut->height;
 253       AddrHtileIn->numSlices = AddrSurfInfoOut->depth;
 254       AddrHtileIn->blockWidth = ADDR_HTILE_BLOCKSIZE_8;
 255       AddrHtileIn->blockHeight = ADDR_HTILE_BLOCKSIZE_8;
 256       AddrHtileIn->pTileInfo = AddrSurfInfoOut->pTileInfo;
 257       AddrHtileIn->tileIndex = AddrSurfInfoOut->tileIndex;
 258       AddrHtileIn->macroModeIndex = AddrSurfInfoOut->macroModeIndex;
 259
 260       ret = AddrComputeHtileInfo(ws->addrlib,
 261                                  AddrHtileIn,
 262                                  AddrHtileOut);
 263
 264       if (ret == ADDR_OK) {
 265          surf->htile_size = AddrHtileOut->htileBytes;
 266          surf->htile_alignment = AddrHtileOut->baseAlign;
 267       }
 268    }
 269
 270    return 0;
 271 }
 272
 273 #define   G_009910_MICRO_TILE_MODE(x)          (((x) >> 0) & 0x03)
 274 #define   G_009910_MICRO_TILE_MODE_NEW(x)      (((x) >> 22) & 0x07)
 275
 276 static void set_micro_tile_mode(struct radeon_surf *surf,
 277                                 struct radeon_info *info)
 278 {
 279    uint32_t tile_mode = info->si_tile_mode_array[surf->tiling_index[0]];
 280
 281    if (info->chip_class >= CIK)
 282       surf->micro_tile_mode = G_009910_MICRO_TILE_MODE_NEW(tile_mode);
 283    else
 284       surf->micro_tile_mode = G_009910_MICRO_TILE_MODE(tile_mode);
 285 }
 286
 287 static unsigned cik_get_macro_tile_index(struct radeon_surf *surf)
 288 {
 289         unsigned index, tileb;
 290
 291         tileb = 8 * 8 * surf->bpe;
 292         tileb = MIN2(surf->tile_split, tileb);
 293
 294         for (index = 0; tileb > 64; index++)
 295                 tileb >>= 1;
 296
 297         assert(index < 16);
 298         return index;
 299 }
 300
 301 static int amdgpu_surface_init(struct radeon_winsys *rws,
 302                                const struct pipe_resource *tex,
 303                                unsigned flags, unsigned bpe,
 304                                enum radeon_surf_mode mode,
 305                                struct radeon_surf *surf)
 306 {
 307    struct amdgpu_winsys *ws = (struct amdgpu_winsys*)rws;
 308    unsigned level;
 309    bool compressed;
 310    ADDR_COMPUTE_SURFACE_INFO_INPUT AddrSurfInfoIn = {0};
 311    ADDR_COMPUTE_SURFACE_INFO_OUTPUT AddrSurfInfoOut = {0};
 312    ADDR_COMPUTE_DCCINFO_INPUT AddrDccIn = {0};
 313    ADDR_COMPUTE_DCCINFO_OUTPUT AddrDccOut = {0};
 314    ADDR_COMPUTE_HTILE_INFO_INPUT AddrHtileIn = {0};
 315    ADDR_COMPUTE_HTILE_INFO_OUTPUT AddrHtileOut = {0};
 316    ADDR_TILEINFO AddrTileInfoIn = {0};
 317    ADDR_TILEINFO AddrTileInfoOut = {0};
 318    int r;
 319
 320    r = amdgpu_surface_sanity(tex);
 321    if (r)
 322       return r;
 323
 324    AddrSurfInfoIn.size = sizeof(ADDR_COMPUTE_SURFACE_INFO_INPUT);
 325    AddrSurfInfoOut.size = sizeof(ADDR_COMPUTE_SURFACE_INFO_OUTPUT);
 326    AddrDccIn.size = sizeof(ADDR_COMPUTE_DCCINFO_INPUT);
 327    AddrDccOut.size = sizeof(ADDR_COMPUTE_DCCINFO_OUTPUT);
 328    AddrHtileIn.size = sizeof(ADDR_COMPUTE_HTILE_INFO_INPUT);
 329    AddrHtileOut.size = sizeof(ADDR_COMPUTE_HTILE_INFO_OUTPUT);
 330    AddrSurfInfoOut.pTileInfo = &AddrTileInfoOut;
 331
 332    surf->blk_w = util_format_get_blockwidth(tex->format);
 333    surf->blk_h = util_format_get_blockheight(tex->format);
 334    surf->bpe = bpe;
 335    surf->flags = flags;
 336
 337    compressed = surf->blk_w == 4 && surf->blk_h == 4;
 338
 339    /* MSAA and FMASK require 2D tiling. */
 340    if (tex->nr_samples > 1 ||
 341        (flags & RADEON_SURF_FMASK))
 342       mode = RADEON_SURF_MODE_2D;
 343
 344    /* DB doesn't support linear layouts. */
 345    if (flags & (RADEON_SURF_Z_OR_SBUFFER) &&
 346        mode < RADEON_SURF_MODE_1D)
 347       mode = RADEON_SURF_MODE_1D;
 348
 349    /* Set the requested tiling mode. */
 350    switch (mode) {
 351    case RADEON_SURF_MODE_LINEAR_ALIGNED:
 352       AddrSurfInfoIn.tileMode = ADDR_TM_LINEAR_ALIGNED;
 353       break;
 354    case RADEON_SURF_MODE_1D:
 355       AddrSurfInfoIn.tileMode = ADDR_TM_1D_TILED_THIN1;
 356       break;
 357    case RADEON_SURF_MODE_2D:
 358       AddrSurfInfoIn.tileMode = ADDR_TM_2D_TILED_THIN1;
 359       break;
 360    default:
 361       assert(0);
 362    }
 363
 364    /* The format must be set correctly for the allocation of compressed
 365     * textures to work. In other cases, setting the bpp is sufficient. */
 366    if (compressed) {
 367       switch (bpe) {
 368       case 8:
 369          AddrSurfInfoIn.format = ADDR_FMT_BC1;
 370          break;
 371       case 16:
 372          AddrSurfInfoIn.format = ADDR_FMT_BC3;
 373          break;
 374       default:
 375          assert(0);
 376       }
 377    }
 378    else {
 379       AddrDccIn.bpp = AddrSurfInfoIn.bpp = bpe * 8;
 380    }
 381
 382    AddrDccIn.numSamples = AddrSurfInfoIn.numSamples =
 383       tex->nr_samples ? tex->nr_samples : 1;
 384    AddrSurfInfoIn.tileIndex = -1;
 385
 386    /* Set the micro tile type. */
 387    if (flags & RADEON_SURF_SCANOUT)
 388       AddrSurfInfoIn.tileType = ADDR_DISPLAYABLE;
 389    else if (flags & (RADEON_SURF_Z_OR_SBUFFER | RADEON_SURF_FMASK))
 390       AddrSurfInfoIn.tileType = ADDR_DEPTH_SAMPLE_ORDER;
 391    else
 392       AddrSurfInfoIn.tileType = ADDR_NON_DISPLAYABLE;
 393
 394    AddrSurfInfoIn.flags.color = !(flags & RADEON_SURF_Z_OR_SBUFFER);
 395    AddrSurfInfoIn.flags.depth = (flags & RADEON_SURF_ZBUFFER) != 0;
 396    AddrSurfInfoIn.flags.cube = tex->target == PIPE_TEXTURE_CUBE;
 397    AddrSurfInfoIn.flags.fmask = (flags & RADEON_SURF_FMASK) != 0;
 398    AddrSurfInfoIn.flags.display = (flags & RADEON_SURF_SCANOUT) != 0;
 399    AddrSurfInfoIn.flags.pow2Pad = tex->last_level > 0;
 400    AddrSurfInfoIn.flags.tcCompatible = (flags & RADEON_SURF_TC_COMPATIBLE_HTILE) != 0;
 401
 402    /* Only degrade the tile mode for space if TC-compatible HTILE hasn't been
 403     * requested, because TC-compatible HTILE requires 2D tiling.
 404     */
 405    AddrSurfInfoIn.flags.degrade4Space = !AddrSurfInfoIn.flags.tcCompatible &&
 406                                         !(flags & RADEON_SURF_FMASK);
 407
 408    /* DCC notes:
 409     * - If we add MSAA support, keep in mind that CB can't decompress 8bpp
 410     *   with samples >= 4.
 411     * - Mipmapped array textures have low performance (discovered by a closed
 412     *   driver team).
 413     */
 414    AddrSurfInfoIn.flags.dccCompatible = ws->info.chip_class >= VI &&
 415                                         !(flags & RADEON_SURF_Z_OR_SBUFFER) &&
 416                                         !(flags & RADEON_SURF_DISABLE_DCC) &&
 417                                         !compressed && AddrDccIn.numSamples <= 1 &&
 418                                         ((tex->array_size == 1 && tex->depth0 == 1) ||
 419                                          tex->last_level == 0);
 420
 421    AddrSurfInfoIn.flags.noStencil = (flags & RADEON_SURF_SBUFFER) == 0;
 422    AddrSurfInfoIn.flags.compressZ = AddrSurfInfoIn.flags.depth;
 423
 424    /* noStencil = 0 can result in a depth part that is incompatible with
 425     * mipmapped texturing. So set noStencil = 1 when mipmaps are requested (in
 426     * this case, we may end up setting stencil_adjusted).
 427     *
 428     * TODO: update addrlib to a newer version, remove this, and
 429     * use flags.matchStencilTileCfg = 1 as an alternative fix.
 430     */
 431   if (tex->last_level > 0)
 432       AddrSurfInfoIn.flags.noStencil = 1;
 433
 434    /* Set preferred macrotile parameters. This is usually required
 435     * for shared resources. This is for 2D tiling only. */
 436    if (AddrSurfInfoIn.tileMode >= ADDR_TM_2D_TILED_THIN1 &&
 437        surf->bankw && surf->bankh && surf->mtilea && surf->tile_split) {
 438       assert(!(flags & RADEON_SURF_FMASK));
 439
 440       /* If any of these parameters are incorrect, the calculation
 441        * will fail. */
 442       AddrTileInfoIn.banks = surf->num_banks;
 443       AddrTileInfoIn.bankWidth = surf->bankw;
 444       AddrTileInfoIn.bankHeight = surf->bankh;
 445       AddrTileInfoIn.macroAspectRatio = surf->mtilea;
 446       AddrTileInfoIn.tileSplitBytes = surf->tile_split;
 447       AddrTileInfoIn.pipeConfig = surf->pipe_config + 1; /* +1 compared to GB_TILE_MODE */
 448       AddrSurfInfoIn.flags.degrade4Space = 0;
 449       AddrSurfInfoIn.pTileInfo = &AddrTileInfoIn;
 450
 451       /* If AddrSurfInfoIn.pTileInfo is set, Addrlib doesn't set
 452        * the tile index, because we are expected to know it if
 453        * we know the other parameters.
 454        *
 455        * This is something that can easily be fixed in Addrlib.
 456        * For now, just figure it out here.
 457        * Note that only 2D_TILE_THIN1 is handled here.
 458        */
 459       assert(!(flags & RADEON_SURF_Z_OR_SBUFFER));
 460       assert(AddrSurfInfoIn.tileMode == ADDR_TM_2D_TILED_THIN1);
 461
 462       if (ws->info.chip_class == SI) {
 463          if (AddrSurfInfoIn.tileType == ADDR_DISPLAYABLE) {
 464             if (bpe == 2)
 465                AddrSurfInfoIn.tileIndex = 11; /* 16bpp */
 466             else
 467                AddrSurfInfoIn.tileIndex = 12; /* 32bpp */
 468          } else {
 469             if (bpe == 1)
 470                AddrSurfInfoIn.tileIndex = 14; /* 8bpp */
 471             else if (bpe == 2)
 472                AddrSurfInfoIn.tileIndex = 15; /* 16bpp */
 473             else if (bpe == 4)
 474                AddrSurfInfoIn.tileIndex = 16; /* 32bpp */
 475             else
 476                AddrSurfInfoIn.tileIndex = 17; /* 64bpp (and 128bpp) */
 477          }
 478       } else {
 479          /* CIK - VI */
 480          if (AddrSurfInfoIn.tileType == ADDR_DISPLAYABLE)
 481             AddrSurfInfoIn.tileIndex = 10; /* 2D displayable */
 482          else
 483             AddrSurfInfoIn.tileIndex = 14; /* 2D non-displayable */
 484
 485          /* Addrlib doesn't set this if tileIndex is forced like above. */
 486          AddrSurfInfoOut.macroModeIndex = cik_get_macro_tile_index(surf);
 487       }
 488    }
 489
 490    surf->num_dcc_levels = 0;
 491    surf->surf_size = 0;
 492    surf->dcc_size = 0;
 493    surf->dcc_alignment = 1;
 494    surf->htile_size = 0;
 495    surf->htile_alignment = 1;
 496
 497    /* Calculate texture layout information. */
 498    for (level = 0; level <= tex->last_level; level++) {
 499       r = compute_level(ws, tex, surf, false, level, compressed,
 500                         &AddrSurfInfoIn, &AddrSurfInfoOut,
 501                         &AddrDccIn, &AddrDccOut, &AddrHtileIn, &AddrHtileOut);
 502       if (r)
 503          return r;
 504
 505       if (level == 0) {
 506          surf->surf_alignment = AddrSurfInfoOut.baseAlign;
 507          surf->pipe_config = AddrSurfInfoOut.pTileInfo->pipeConfig - 1;
 508          set_micro_tile_mode(surf, &ws->info);
 509
 510          /* For 2D modes only. */
 511          if (AddrSurfInfoOut.tileMode >= ADDR_TM_2D_TILED_THIN1) {
 512             surf->bankw = AddrSurfInfoOut.pTileInfo->bankWidth;
 513             surf->bankh = AddrSurfInfoOut.pTileInfo->bankHeight;
 514             surf->mtilea = AddrSurfInfoOut.pTileInfo->macroAspectRatio;
 515             surf->tile_split = AddrSurfInfoOut.pTileInfo->tileSplitBytes;
 516             surf->num_banks = AddrSurfInfoOut.pTileInfo->banks;
 517             surf->macro_tile_index = AddrSurfInfoOut.macroModeIndex;
 518          } else {
 519             surf->macro_tile_index = 0;
 520          }
 521       }
 522    }
 523
 524    /* Calculate texture layout information for stencil. */
 525    if (flags & RADEON_SURF_SBUFFER) {
 526       AddrSurfInfoIn.bpp = 8;
 527       AddrSurfInfoIn.flags.depth = 0;
 528       AddrSurfInfoIn.flags.stencil = 1;
 529       AddrSurfInfoIn.flags.tcCompatible = 0;
 530       /* This will be ignored if AddrSurfInfoIn.pTileInfo is NULL. */
 531       AddrTileInfoIn.tileSplitBytes = surf->stencil_tile_split;
 532
 533       for (level = 0; level <= tex->last_level; level++) {
 534          r = compute_level(ws, tex, surf, true, level, compressed,
 535                            &AddrSurfInfoIn, &AddrSurfInfoOut, &AddrDccIn, &AddrDccOut,
 536                            NULL, NULL);
 537          if (r)
 538             return r;
 539
 540          /* DB uses the depth pitch for both stencil and depth. */
 541          if (surf->stencil_level[level].nblk_x != surf->level[level].nblk_x)
 542             surf->stencil_adjusted = true;
 543
 544          if (level == 0) {
 545             /* For 2D modes only. */
 546             if (AddrSurfInfoOut.tileMode >= ADDR_TM_2D_TILED_THIN1) {
 547                surf->stencil_tile_split =
 548                      AddrSurfInfoOut.pTileInfo->tileSplitBytes;
 549             }
 550          }
 551       }
 552    }
 553
 554    /* Recalculate the whole DCC miptree size including disabled levels.
 555     * This is what addrlib does, but calling addrlib would be a lot more
 556     * complicated.
 557     */
 558    if (surf->dcc_size && tex->last_level > 0) {
 559       surf->dcc_size = align64(surf->surf_size >> 8,
 560                                ws->info.pipe_interleave_bytes *
 561                                ws->info.num_tile_pipes);
 562    }
 563
 564    /* Make sure HTILE covers the whole miptree, because the shader reads
 565     * TC-compatible HTILE even for levels where it's disabled by DB.
 566     */
 567    if (surf->htile_size && tex->last_level)
 568            surf->htile_size *= 2;
 569
 570    return 0;
 571 }
 572
 573 void amdgpu_surface_init_functions(struct amdgpu_winsys *ws)
 574 {
 575    ws->base.surface_init = amdgpu_surface_init;
 576 }