d5fa37bb6d916f032473e0c7299f699dd7d804fc
2 * Copyright © 2011 Red Hat All Rights Reserved.
3 * Copyright © 2014 Advanced Micro Devices, Inc.
6 * Permission is hereby granted, free of charge, to any person obtaining
7 * a copy of this software and associated documentation files (the
8 * "Software"), to deal in the Software without restriction, including
9 * without limitation the rights to use, copy, modify, merge, publish,
10 * distribute, sub license, and/or sell copies of the Software, and to
11 * permit persons to whom the Software is furnished to do so, subject to
12 * the following conditions:
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
15 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
16 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
17 * NON-INFRINGEMENT. IN NO EVENT SHALL THE COPYRIGHT HOLDERS, AUTHORS
18 * AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
20 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
23 * The above copyright notice and this permission notice (including the
24 * next paragraph) shall be included in all copies or substantial portions
28 #include "amdgpu_winsys.h"
29 #include "util/u_format.h"
31 static int amdgpu_surface_sanity(const struct pipe_resource
*tex
)
33 switch (tex
->target
) {
39 case PIPE_TEXTURE_RECT
:
40 if (tex
->depth0
> 1 || tex
->array_size
> 1)
44 if (tex
->array_size
> 1)
47 case PIPE_TEXTURE_1D_ARRAY
:
51 case PIPE_TEXTURE_CUBE
:
52 case PIPE_TEXTURE_2D_ARRAY
:
53 case PIPE_TEXTURE_CUBE_ARRAY
:
63 static int amdgpu_surface_init(struct radeon_winsys
*rws
,
64 const struct pipe_resource
*tex
,
65 unsigned num_color_samples
,
66 unsigned flags
, unsigned bpe
,
67 enum radeon_surf_mode mode
,
68 struct radeon_surf
*surf
)
70 struct amdgpu_winsys
*ws
= (struct amdgpu_winsys
*)rws
;
73 r
= amdgpu_surface_sanity(tex
);
77 surf
->blk_w
= util_format_get_blockwidth(tex
->format
);
78 surf
->blk_h
= util_format_get_blockheight(tex
->format
);
82 struct ac_surf_config config
;
84 config
.info
.width
= tex
->width0
;
85 config
.info
.height
= tex
->height0
;
86 config
.info
.depth
= tex
->depth0
;
87 config
.info
.array_size
= tex
->array_size
;
88 config
.info
.samples
= tex
->nr_samples
;
89 config
.info
.color_samples
= num_color_samples
;
90 config
.info
.levels
= tex
->last_level
+ 1;
91 config
.info
.num_channels
= util_format_get_nr_components(tex
->format
);
92 config
.is_3d
= !!(tex
->target
== PIPE_TEXTURE_3D
);
93 config
.is_cube
= !!(tex
->target
== PIPE_TEXTURE_CUBE
);
95 /* Use different surface counters for color and FMASK, so that MSAA MRTs
96 * always use consecutive surface indices when FMASK is allocated between
99 if (flags
& RADEON_SURF_FMASK
)
100 config
.info
.surf_index
= &ws
->surf_index_fmask
;
101 else if (!(flags
& RADEON_SURF_Z_OR_SBUFFER
))
102 config
.info
.surf_index
= &ws
->surf_index_color
;
104 config
.info
.surf_index
= NULL
;
106 config
.info
.fmask_surf_index
= &ws
->surf_index_fmask
;
108 return ac_compute_surface(ws
->addrlib
, &ws
->info
, &config
, mode
, surf
);
111 void amdgpu_surface_init_functions(struct amdgpu_winsys
*ws
)
113 ws
->base
.surface_init
= amdgpu_surface_init
;