src/gallium/winsys/amdgpu/drm/amdgpu_surface.c

   1 /*
   2  * Copyright © 2011 Red Hat All Rights Reserved.
   3  * Copyright © 2014 Advanced Micro Devices, Inc.
   4  * All Rights Reserved.
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining
   7  * a copy of this software and associated documentation files (the
   8  * "Software"), to deal in the Software without restriction, including
   9  * without limitation the rights to use, copy, modify, merge, publish,
  10  * distribute, sub license, and/or sell copies of the Software, and to
  11  * permit persons to whom the Software is furnished to do so, subject to
  12  * the following conditions:
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  15  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
  16  * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  17  * NON-INFRINGEMENT. IN NO EVENT SHALL THE COPYRIGHT HOLDERS, AUTHORS
  18  * AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  20  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
  21  * USE OR OTHER DEALINGS IN THE SOFTWARE.
  22  *
  23  * The above copyright notice and this permission notice (including the
  24  * next paragraph) shall be included in all copies or substantial portions
  25  * of the Software.
  26  */
  27
  28 /* Contact:
  29  *     Marek Olšák <maraeo@gmail.com>
  30  */
  31
  32 #include "amdgpu_winsys.h"
  33
  34 #ifndef NO_ENTRIES
  35 #define NO_ENTRIES 32
  36 #endif
  37
  38 #ifndef NO_MACRO_ENTRIES
  39 #define NO_MACRO_ENTRIES 16
  40 #endif
  41
  42 #ifndef CIASICIDGFXENGINE_SOUTHERNISLAND
  43 #define CIASICIDGFXENGINE_SOUTHERNISLAND 0x0000000A
  44 #endif
  45
  46
  47 static int amdgpu_surface_sanity(const struct radeon_surf *surf)
  48 {
  49    unsigned type = RADEON_SURF_GET(surf->flags, TYPE);
  50
  51    if (!(surf->flags & RADEON_SURF_HAS_TILE_MODE_INDEX))
  52       return -EINVAL;
  53
  54    /* all dimension must be at least 1 ! */
  55    if (!surf->npix_x || !surf->npix_y || !surf->npix_z ||
  56        !surf->array_size)
  57       return -EINVAL;
  58
  59    if (!surf->blk_w || !surf->blk_h || !surf->blk_d)
  60       return -EINVAL;
  61
  62    switch (surf->nsamples) {
  63    case 1:
  64    case 2:
  65    case 4:
  66    case 8:
  67       break;
  68    default:
  69       return -EINVAL;
  70    }
  71
  72    switch (type) {
  73    case RADEON_SURF_TYPE_1D:
  74       if (surf->npix_y > 1)
  75          return -EINVAL;
  76       /* fall through */
  77    case RADEON_SURF_TYPE_2D:
  78    case RADEON_SURF_TYPE_CUBEMAP:
  79       if (surf->npix_z > 1 || surf->array_size > 1)
  80          return -EINVAL;
  81       break;
  82    case RADEON_SURF_TYPE_3D:
  83       if (surf->array_size > 1)
  84          return -EINVAL;
  85       break;
  86    case RADEON_SURF_TYPE_1D_ARRAY:
  87       if (surf->npix_y > 1)
  88          return -EINVAL;
  89       /* fall through */
  90    case RADEON_SURF_TYPE_2D_ARRAY:
  91       if (surf->npix_z > 1)
  92          return -EINVAL;
  93       break;
  94    default:
  95       return -EINVAL;
  96    }
  97    return 0;
  98 }
  99
 100 static void *ADDR_API allocSysMem(const ADDR_ALLOCSYSMEM_INPUT * pInput)
 101 {
 102    return malloc(pInput->sizeInBytes);
 103 }
 104
 105 static ADDR_E_RETURNCODE ADDR_API freeSysMem(const ADDR_FREESYSMEM_INPUT * pInput)
 106 {
 107    free(pInput->pVirtAddr);
 108    return ADDR_OK;
 109 }
 110
 111 ADDR_HANDLE amdgpu_addr_create(struct amdgpu_winsys *ws)
 112 {
 113    ADDR_CREATE_INPUT addrCreateInput = {0};
 114    ADDR_CREATE_OUTPUT addrCreateOutput = {0};
 115    ADDR_REGISTER_VALUE regValue = {0};
 116    ADDR_CREATE_FLAGS createFlags = {{0}};
 117    ADDR_E_RETURNCODE addrRet;
 118
 119    addrCreateInput.size = sizeof(ADDR_CREATE_INPUT);
 120    addrCreateOutput.size = sizeof(ADDR_CREATE_OUTPUT);
 121
 122    regValue.noOfBanks = ws->amdinfo.mc_arb_ramcfg & 0x3;
 123    regValue.gbAddrConfig = ws->amdinfo.gb_addr_cfg;
 124    regValue.noOfRanks = (ws->amdinfo.mc_arb_ramcfg & 0x4) >> 2;
 125
 126    regValue.backendDisables = ws->amdinfo.backend_disable[0];
 127    regValue.pTileConfig = ws->amdinfo.gb_tile_mode;
 128    regValue.noOfEntries = ARRAY_SIZE(ws->amdinfo.gb_tile_mode);
 129    if (ws->info.chip_class == SI) {
 130       regValue.pMacroTileConfig = NULL;
 131       regValue.noOfMacroEntries = 0;
 132    } else {
 133       regValue.pMacroTileConfig = ws->amdinfo.gb_macro_tile_mode;
 134       regValue.noOfMacroEntries = ARRAY_SIZE(ws->amdinfo.gb_macro_tile_mode);
 135    }
 136
 137    createFlags.value = 0;
 138    createFlags.useTileIndex = 1;
 139    createFlags.degradeBaseLevel = 1;
 140    createFlags.useHtileSliceAlign = 1;
 141
 142    addrCreateInput.chipEngine = CIASICIDGFXENGINE_SOUTHERNISLAND;
 143    addrCreateInput.chipFamily = ws->family;
 144    addrCreateInput.chipRevision = ws->rev_id;
 145    addrCreateInput.createFlags = createFlags;
 146    addrCreateInput.callbacks.allocSysMem = allocSysMem;
 147    addrCreateInput.callbacks.freeSysMem = freeSysMem;
 148    addrCreateInput.callbacks.debugPrint = 0;
 149    addrCreateInput.regValue = regValue;
 150
 151    addrRet = AddrCreate(&addrCreateInput, &addrCreateOutput);
 152    if (addrRet != ADDR_OK)
 153       return NULL;
 154
 155    return addrCreateOutput.hLib;
 156 }
 157
 158 static int compute_level(struct amdgpu_winsys *ws,
 159                          struct radeon_surf *surf, bool is_stencil,
 160                          unsigned level, unsigned type, bool compressed,
 161                          ADDR_COMPUTE_SURFACE_INFO_INPUT *AddrSurfInfoIn,
 162                          ADDR_COMPUTE_SURFACE_INFO_OUTPUT *AddrSurfInfoOut,
 163                          ADDR_COMPUTE_DCCINFO_INPUT *AddrDccIn,
 164                          ADDR_COMPUTE_DCCINFO_OUTPUT *AddrDccOut,
 165                          ADDR_COMPUTE_HTILE_INFO_INPUT *AddrHtileIn,
 166                          ADDR_COMPUTE_HTILE_INFO_OUTPUT *AddrHtileOut)
 167 {
 168    struct radeon_surf_level *surf_level;
 169    ADDR_E_RETURNCODE ret;
 170
 171    AddrSurfInfoIn->mipLevel = level;
 172    AddrSurfInfoIn->width = u_minify(surf->npix_x, level);
 173    AddrSurfInfoIn->height = u_minify(surf->npix_y, level);
 174
 175    if (type == RADEON_SURF_TYPE_3D)
 176       AddrSurfInfoIn->numSlices = u_minify(surf->npix_z, level);
 177    else if (type == RADEON_SURF_TYPE_CUBEMAP)
 178       AddrSurfInfoIn->numSlices = 6;
 179    else
 180       AddrSurfInfoIn->numSlices = surf->array_size;
 181
 182    if (level > 0) {
 183       /* Set the base level pitch. This is needed for calculation
 184        * of non-zero levels. */
 185       if (is_stencil)
 186          AddrSurfInfoIn->basePitch = surf->stencil_level[0].nblk_x;
 187       else
 188          AddrSurfInfoIn->basePitch = surf->level[0].nblk_x;
 189
 190       /* Convert blocks to pixels for compressed formats. */
 191       if (compressed)
 192          AddrSurfInfoIn->basePitch *= surf->blk_w;
 193    }
 194
 195    ret = AddrComputeSurfaceInfo(ws->addrlib,
 196                                 AddrSurfInfoIn,
 197                                 AddrSurfInfoOut);
 198    if (ret != ADDR_OK) {
 199       return ret;
 200    }
 201
 202    surf_level = is_stencil ? &surf->stencil_level[level] : &surf->level[level];
 203    surf_level->offset = align64(surf->bo_size, AddrSurfInfoOut->baseAlign);
 204    surf_level->slice_size = AddrSurfInfoOut->sliceSize;
 205    surf_level->pitch_bytes = AddrSurfInfoOut->pitch * (is_stencil ? 1 : surf->bpe);
 206    surf_level->npix_x = u_minify(surf->npix_x, level);
 207    surf_level->npix_y = u_minify(surf->npix_y, level);
 208    surf_level->npix_z = u_minify(surf->npix_z, level);
 209    surf_level->nblk_x = AddrSurfInfoOut->pitch;
 210    surf_level->nblk_y = AddrSurfInfoOut->height;
 211    if (type == RADEON_SURF_TYPE_3D)
 212       surf_level->nblk_z = AddrSurfInfoOut->depth;
 213    else
 214       surf_level->nblk_z = 1;
 215
 216    switch (AddrSurfInfoOut->tileMode) {
 217    case ADDR_TM_LINEAR_ALIGNED:
 218       surf_level->mode = RADEON_SURF_MODE_LINEAR_ALIGNED;
 219       break;
 220    case ADDR_TM_1D_TILED_THIN1:
 221       surf_level->mode = RADEON_SURF_MODE_1D;
 222       break;
 223    case ADDR_TM_2D_TILED_THIN1:
 224       surf_level->mode = RADEON_SURF_MODE_2D;
 225       break;
 226    default:
 227       assert(0);
 228    }
 229
 230    if (is_stencil)
 231       surf->stencil_tiling_index[level] = AddrSurfInfoOut->tileIndex;
 232    else
 233       surf->tiling_index[level] = AddrSurfInfoOut->tileIndex;
 234
 235    surf->bo_size = surf_level->offset + AddrSurfInfoOut->surfSize;
 236
 237    /* Clear DCC fields at the beginning. */
 238    surf_level->dcc_offset = 0;
 239    surf_level->dcc_enabled = false;
 240
 241    /* The previous level's flag tells us if we can use DCC for this level. */
 242    if (AddrSurfInfoIn->flags.dccCompatible &&
 243        (level == 0 || AddrDccOut->subLvlCompressible)) {
 244       AddrDccIn->colorSurfSize = AddrSurfInfoOut->surfSize;
 245       AddrDccIn->tileMode = AddrSurfInfoOut->tileMode;
 246       AddrDccIn->tileInfo = *AddrSurfInfoOut->pTileInfo;
 247       AddrDccIn->tileIndex = AddrSurfInfoOut->tileIndex;
 248       AddrDccIn->macroModeIndex = AddrSurfInfoOut->macroModeIndex;
 249
 250       ret = AddrComputeDccInfo(ws->addrlib,
 251                                AddrDccIn,
 252                                AddrDccOut);
 253
 254       if (ret == ADDR_OK) {
 255          surf_level->dcc_offset = surf->dcc_size;
 256          surf_level->dcc_fast_clear_size = AddrDccOut->dccFastClearSize;
 257          surf_level->dcc_enabled = true;
 258          surf->dcc_size = surf_level->dcc_offset + AddrDccOut->dccRamSize;
 259          surf->dcc_alignment = MAX2(surf->dcc_alignment, AddrDccOut->dccRamBaseAlign);
 260       }
 261    }
 262
 263    /* TC-compatible HTILE. */
 264    if (!is_stencil &&
 265        AddrSurfInfoIn->flags.depth &&
 266        AddrSurfInfoIn->flags.tcCompatible &&
 267        surf_level->mode == RADEON_SURF_MODE_2D &&
 268        level == 0) {
 269       AddrHtileIn->flags.tcCompatible = 1;
 270       AddrHtileIn->pitch = AddrSurfInfoOut->pitch;
 271       AddrHtileIn->height = AddrSurfInfoOut->height;
 272       AddrHtileIn->numSlices = AddrSurfInfoOut->depth;
 273       AddrHtileIn->blockWidth = ADDR_HTILE_BLOCKSIZE_8;
 274       AddrHtileIn->blockHeight = ADDR_HTILE_BLOCKSIZE_8;
 275       AddrHtileIn->pTileInfo = AddrSurfInfoOut->pTileInfo;
 276       AddrHtileIn->tileIndex = AddrSurfInfoOut->tileIndex;
 277       AddrHtileIn->macroModeIndex = AddrSurfInfoOut->macroModeIndex;
 278
 279       ret = AddrComputeHtileInfo(ws->addrlib,
 280                                  AddrHtileIn,
 281                                  AddrHtileOut);
 282
 283       if (ret == ADDR_OK) {
 284          surf->htile_size = AddrHtileOut->htileBytes;
 285          surf->htile_alignment = AddrHtileOut->baseAlign;
 286       }
 287    }
 288
 289    return 0;
 290 }
 291
 292 #define   G_009910_MICRO_TILE_MODE(x)          (((x) >> 0) & 0x03)
 293 #define   G_009910_MICRO_TILE_MODE_NEW(x)      (((x) >> 22) & 0x07)
 294
 295 static void set_micro_tile_mode(struct radeon_surf *surf,
 296                                 struct radeon_info *info)
 297 {
 298    uint32_t tile_mode = info->si_tile_mode_array[surf->tiling_index[0]];
 299
 300    if (info->chip_class >= CIK)
 301       surf->micro_tile_mode = G_009910_MICRO_TILE_MODE_NEW(tile_mode);
 302    else
 303       surf->micro_tile_mode = G_009910_MICRO_TILE_MODE(tile_mode);
 304 }
 305
 306 static unsigned cik_get_macro_tile_index(struct radeon_surf *surf)
 307 {
 308         unsigned index, tileb;
 309
 310         tileb = 8 * 8 * surf->bpe;
 311         tileb = MIN2(surf->tile_split, tileb);
 312
 313         for (index = 0; tileb > 64; index++)
 314                 tileb >>= 1;
 315
 316         assert(index < 16);
 317         return index;
 318 }
 319
 320 static int amdgpu_surface_init(struct radeon_winsys *rws,
 321                                struct radeon_surf *surf)
 322 {
 323    struct amdgpu_winsys *ws = (struct amdgpu_winsys*)rws;
 324    unsigned level, mode, type;
 325    bool compressed;
 326    ADDR_COMPUTE_SURFACE_INFO_INPUT AddrSurfInfoIn = {0};
 327    ADDR_COMPUTE_SURFACE_INFO_OUTPUT AddrSurfInfoOut = {0};
 328    ADDR_COMPUTE_DCCINFO_INPUT AddrDccIn = {0};
 329    ADDR_COMPUTE_DCCINFO_OUTPUT AddrDccOut = {0};
 330    ADDR_COMPUTE_HTILE_INFO_INPUT AddrHtileIn = {0};
 331    ADDR_COMPUTE_HTILE_INFO_OUTPUT AddrHtileOut = {0};
 332    ADDR_TILEINFO AddrTileInfoIn = {0};
 333    ADDR_TILEINFO AddrTileInfoOut = {0};
 334    int r;
 335
 336    r = amdgpu_surface_sanity(surf);
 337    if (r)
 338       return r;
 339
 340    AddrSurfInfoIn.size = sizeof(ADDR_COMPUTE_SURFACE_INFO_INPUT);
 341    AddrSurfInfoOut.size = sizeof(ADDR_COMPUTE_SURFACE_INFO_OUTPUT);
 342    AddrDccIn.size = sizeof(ADDR_COMPUTE_DCCINFO_INPUT);
 343    AddrDccOut.size = sizeof(ADDR_COMPUTE_DCCINFO_OUTPUT);
 344    AddrHtileIn.size = sizeof(ADDR_COMPUTE_HTILE_INFO_INPUT);
 345    AddrHtileOut.size = sizeof(ADDR_COMPUTE_HTILE_INFO_OUTPUT);
 346    AddrSurfInfoOut.pTileInfo = &AddrTileInfoOut;
 347
 348    type = RADEON_SURF_GET(surf->flags, TYPE);
 349    mode = RADEON_SURF_GET(surf->flags, MODE);
 350    compressed = surf->blk_w == 4 && surf->blk_h == 4;
 351
 352    /* MSAA and FMASK require 2D tiling. */
 353    if (surf->nsamples > 1 ||
 354        (surf->flags & RADEON_SURF_FMASK))
 355       mode = RADEON_SURF_MODE_2D;
 356
 357    /* DB doesn't support linear layouts. */
 358    if (surf->flags & (RADEON_SURF_Z_OR_SBUFFER) &&
 359        mode < RADEON_SURF_MODE_1D)
 360       mode = RADEON_SURF_MODE_1D;
 361
 362    /* Set the requested tiling mode. */
 363    switch (mode) {
 364    case RADEON_SURF_MODE_LINEAR_ALIGNED:
 365       AddrSurfInfoIn.tileMode = ADDR_TM_LINEAR_ALIGNED;
 366       break;
 367    case RADEON_SURF_MODE_1D:
 368       AddrSurfInfoIn.tileMode = ADDR_TM_1D_TILED_THIN1;
 369       break;
 370    case RADEON_SURF_MODE_2D:
 371       AddrSurfInfoIn.tileMode = ADDR_TM_2D_TILED_THIN1;
 372       break;
 373    default:
 374       assert(0);
 375    }
 376
 377    /* The format must be set correctly for the allocation of compressed
 378     * textures to work. In other cases, setting the bpp is sufficient. */
 379    if (compressed) {
 380       switch (surf->bpe) {
 381       case 8:
 382          AddrSurfInfoIn.format = ADDR_FMT_BC1;
 383          break;
 384       case 16:
 385          AddrSurfInfoIn.format = ADDR_FMT_BC3;
 386          break;
 387       default:
 388          assert(0);
 389       }
 390    }
 391    else {
 392       AddrDccIn.bpp = AddrSurfInfoIn.bpp = surf->bpe * 8;
 393    }
 394
 395    AddrDccIn.numSamples = AddrSurfInfoIn.numSamples = surf->nsamples;
 396    AddrSurfInfoIn.tileIndex = -1;
 397
 398    /* Set the micro tile type. */
 399    if (surf->flags & RADEON_SURF_SCANOUT)
 400       AddrSurfInfoIn.tileType = ADDR_DISPLAYABLE;
 401    else if (surf->flags & RADEON_SURF_Z_OR_SBUFFER)
 402       AddrSurfInfoIn.tileType = ADDR_DEPTH_SAMPLE_ORDER;
 403    else
 404       AddrSurfInfoIn.tileType = ADDR_NON_DISPLAYABLE;
 405
 406    AddrSurfInfoIn.flags.color = !(surf->flags & RADEON_SURF_Z_OR_SBUFFER);
 407    AddrSurfInfoIn.flags.depth = (surf->flags & RADEON_SURF_ZBUFFER) != 0;
 408    AddrSurfInfoIn.flags.cube = type == RADEON_SURF_TYPE_CUBEMAP;
 409    AddrSurfInfoIn.flags.display = (surf->flags & RADEON_SURF_SCANOUT) != 0;
 410    AddrSurfInfoIn.flags.pow2Pad = surf->last_level > 0;
 411    AddrSurfInfoIn.flags.tcCompatible = (surf->flags & RADEON_SURF_TC_COMPATIBLE_HTILE) != 0;
 412
 413    /* Only degrade the tile mode for space if TC-compatible HTILE hasn't been
 414     * requested, because TC-compatible HTILE requires 2D tiling.
 415     */
 416    AddrSurfInfoIn.flags.degrade4Space = !AddrSurfInfoIn.flags.tcCompatible;
 417
 418    /* DCC notes:
 419     * - If we add MSAA support, keep in mind that CB can't decompress 8bpp
 420     *   with samples >= 4.
 421     * - Mipmapped array textures have low performance (discovered by a closed
 422     *   driver team).
 423     */
 424    AddrSurfInfoIn.flags.dccCompatible = ws->info.chip_class >= VI &&
 425                                         !(surf->flags & RADEON_SURF_Z_OR_SBUFFER) &&
 426                                         !(surf->flags & RADEON_SURF_DISABLE_DCC) &&
 427                                         !compressed && AddrDccIn.numSamples <= 1 &&
 428                                         ((surf->array_size == 1 && surf->npix_z == 1) ||
 429                                          surf->last_level == 0);
 430
 431    AddrSurfInfoIn.flags.noStencil = (surf->flags & RADEON_SURF_SBUFFER) == 0;
 432    AddrSurfInfoIn.flags.compressZ = AddrSurfInfoIn.flags.depth;
 433
 434    /* noStencil = 0 can result in a depth part that is incompatible with
 435     * mipmapped texturing. So set noStencil = 1 when mipmaps are requested (in
 436     * this case, we may end up setting stencil_adjusted).
 437     *
 438     * TODO: update addrlib to a newer version, remove this, and
 439     * use flags.matchStencilTileCfg = 1 as an alternative fix.
 440     */
 441   if (surf->last_level > 0)
 442       AddrSurfInfoIn.flags.noStencil = 1;
 443
 444    /* Set preferred macrotile parameters. This is usually required
 445     * for shared resources. This is for 2D tiling only. */
 446    if (AddrSurfInfoIn.tileMode >= ADDR_TM_2D_TILED_THIN1 &&
 447        surf->bankw && surf->bankh && surf->mtilea && surf->tile_split) {
 448       /* If any of these parameters are incorrect, the calculation
 449        * will fail. */
 450       AddrTileInfoIn.banks = surf->num_banks;
 451       AddrTileInfoIn.bankWidth = surf->bankw;
 452       AddrTileInfoIn.bankHeight = surf->bankh;
 453       AddrTileInfoIn.macroAspectRatio = surf->mtilea;
 454       AddrTileInfoIn.tileSplitBytes = surf->tile_split;
 455       AddrTileInfoIn.pipeConfig = surf->pipe_config + 1; /* +1 compared to GB_TILE_MODE */
 456       AddrSurfInfoIn.flags.degrade4Space = 0;
 457       AddrSurfInfoIn.pTileInfo = &AddrTileInfoIn;
 458
 459       /* If AddrSurfInfoIn.pTileInfo is set, Addrlib doesn't set
 460        * the tile index, because we are expected to know it if
 461        * we know the other parameters.
 462        *
 463        * This is something that can easily be fixed in Addrlib.
 464        * For now, just figure it out here.
 465        * Note that only 2D_TILE_THIN1 is handled here.
 466        */
 467       assert(!(surf->flags & RADEON_SURF_Z_OR_SBUFFER));
 468       assert(AddrSurfInfoIn.tileMode == ADDR_TM_2D_TILED_THIN1);
 469
 470       if (ws->info.chip_class == SI) {
 471          if (AddrSurfInfoIn.tileType == ADDR_DISPLAYABLE) {
 472             if (surf->bpe == 2)
 473                AddrSurfInfoIn.tileIndex = 11; /* 16bpp */
 474             else
 475                AddrSurfInfoIn.tileIndex = 12; /* 32bpp */
 476          } else {
 477             if (surf->bpe == 1)
 478                AddrSurfInfoIn.tileIndex = 14; /* 8bpp */
 479             else if (surf->bpe == 2)
 480                AddrSurfInfoIn.tileIndex = 15; /* 16bpp */
 481             else if (surf->bpe == 4)
 482                AddrSurfInfoIn.tileIndex = 16; /* 32bpp */
 483             else
 484                AddrSurfInfoIn.tileIndex = 17; /* 64bpp (and 128bpp) */
 485          }
 486       } else {
 487          /* CIK - VI */
 488          if (AddrSurfInfoIn.tileType == ADDR_DISPLAYABLE)
 489             AddrSurfInfoIn.tileIndex = 10; /* 2D displayable */
 490          else
 491             AddrSurfInfoIn.tileIndex = 14; /* 2D non-displayable */
 492
 493          /* Addrlib doesn't set this if tileIndex is forced like above. */
 494          AddrSurfInfoOut.macroModeIndex = cik_get_macro_tile_index(surf);
 495       }
 496    }
 497
 498    surf->bo_size = 0;
 499    surf->dcc_size = 0;
 500    surf->dcc_alignment = 1;
 501    surf->htile_size = 0;
 502    surf->htile_alignment = 1;
 503
 504    /* Calculate texture layout information. */
 505    for (level = 0; level <= surf->last_level; level++) {
 506       r = compute_level(ws, surf, false, level, type, compressed,
 507                         &AddrSurfInfoIn, &AddrSurfInfoOut,
 508                         &AddrDccIn, &AddrDccOut, &AddrHtileIn, &AddrHtileOut);
 509       if (r)
 510          return r;
 511
 512       if (level == 0) {
 513          surf->bo_alignment = AddrSurfInfoOut.baseAlign;
 514          surf->pipe_config = AddrSurfInfoOut.pTileInfo->pipeConfig - 1;
 515          set_micro_tile_mode(surf, &ws->info);
 516
 517          /* For 2D modes only. */
 518          if (AddrSurfInfoOut.tileMode >= ADDR_TM_2D_TILED_THIN1) {
 519             surf->bankw = AddrSurfInfoOut.pTileInfo->bankWidth;
 520             surf->bankh = AddrSurfInfoOut.pTileInfo->bankHeight;
 521             surf->mtilea = AddrSurfInfoOut.pTileInfo->macroAspectRatio;
 522             surf->tile_split = AddrSurfInfoOut.pTileInfo->tileSplitBytes;
 523             surf->num_banks = AddrSurfInfoOut.pTileInfo->banks;
 524             surf->macro_tile_index = AddrSurfInfoOut.macroModeIndex;
 525          } else {
 526             surf->macro_tile_index = 0;
 527          }
 528       }
 529    }
 530
 531    /* Calculate texture layout information for stencil. */
 532    if (surf->flags & RADEON_SURF_SBUFFER) {
 533       AddrSurfInfoIn.bpp = 8;
 534       AddrSurfInfoIn.flags.depth = 0;
 535       AddrSurfInfoIn.flags.stencil = 1;
 536       AddrSurfInfoIn.flags.tcCompatible = 0;
 537       /* This will be ignored if AddrSurfInfoIn.pTileInfo is NULL. */
 538       AddrTileInfoIn.tileSplitBytes = surf->stencil_tile_split;
 539
 540       for (level = 0; level <= surf->last_level; level++) {
 541          r = compute_level(ws, surf, true, level, type, compressed,
 542                            &AddrSurfInfoIn, &AddrSurfInfoOut, &AddrDccIn, &AddrDccOut,
 543                            NULL, NULL);
 544          if (r)
 545             return r;
 546
 547          /* DB uses the depth pitch for both stencil and depth. */
 548          if (surf->stencil_level[level].nblk_x != surf->level[level].nblk_x)
 549             surf->stencil_adjusted = true;
 550
 551          if (level == 0) {
 552             /* For 2D modes only. */
 553             if (AddrSurfInfoOut.tileMode >= ADDR_TM_2D_TILED_THIN1) {
 554                surf->stencil_tile_split =
 555                      AddrSurfInfoOut.pTileInfo->tileSplitBytes;
 556             }
 557          }
 558       }
 559    }
 560
 561    /* Recalculate the whole DCC miptree size including disabled levels.
 562     * This is what addrlib does, but calling addrlib would be a lot more
 563     * complicated.
 564     */
 565    if (surf->dcc_size && surf->last_level > 0) {
 566       surf->dcc_size = align64(surf->bo_size >> 8,
 567                                ws->info.pipe_interleave_bytes *
 568                                ws->info.num_tile_pipes);
 569    }
 570
 571    /* Make sure HTILE covers the whole miptree, because the shader reads
 572     * TC-compatible HTILE even for levels where it's disabled by DB.
 573     */
 574    if (surf->htile_size && surf->last_level)
 575            surf->htile_size *= 2;
 576
 577    return 0;
 578 }
 579
 580 static int amdgpu_surface_best(struct radeon_winsys *rws,
 581                                struct radeon_surf *surf)
 582 {
 583    return 0;
 584 }
 585
 586 void amdgpu_surface_init_functions(struct amdgpu_winsys *ws)
 587 {
 588    ws->base.surface_init = amdgpu_surface_init;
 589    ws->base.surface_best = amdgpu_surface_best;
 590 }