src/gallium/winsys/amdgpu/drm/amdgpu_surface.c

   1 /*
   2  * Copyright © 2011 Red Hat All Rights Reserved.
   3  * Copyright © 2014 Advanced Micro Devices, Inc.
   4  * All Rights Reserved.
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining
   7  * a copy of this software and associated documentation files (the
   8  * "Software"), to deal in the Software without restriction, including
   9  * without limitation the rights to use, copy, modify, merge, publish,
  10  * distribute, sub license, and/or sell copies of the Software, and to
  11  * permit persons to whom the Software is furnished to do so, subject to
  12  * the following conditions:
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  15  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
  16  * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  17  * NON-INFRINGEMENT. IN NO EVENT SHALL THE COPYRIGHT HOLDERS, AUTHORS
  18  * AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  20  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
  21  * USE OR OTHER DEALINGS IN THE SOFTWARE.
  22  *
  23  * The above copyright notice and this permission notice (including the
  24  * next paragraph) shall be included in all copies or substantial portions
  25  * of the Software.
  26  */
  27
  28 /* Contact:
  29  *     Marek Olšák <maraeo@gmail.com>
  30  */
  31
  32 #include "amdgpu_winsys.h"
  33
  34 #ifndef NO_ENTRIES
  35 #define NO_ENTRIES 32
  36 #endif
  37
  38 #ifndef NO_MACRO_ENTRIES
  39 #define NO_MACRO_ENTRIES 16
  40 #endif
  41
  42 #ifndef CIASICIDGFXENGINE_SOUTHERNISLAND
  43 #define CIASICIDGFXENGINE_SOUTHERNISLAND 0x0000000A
  44 #endif
  45
  46
  47 static int amdgpu_surface_sanity(const struct radeon_surf *surf)
  48 {
  49    unsigned type = RADEON_SURF_GET(surf->flags, TYPE);
  50
  51    if (!(surf->flags & RADEON_SURF_HAS_TILE_MODE_INDEX))
  52       return -EINVAL;
  53
  54    /* all dimension must be at least 1 ! */
  55    if (!surf->npix_x || !surf->npix_y || !surf->npix_z ||
  56        !surf->array_size)
  57       return -EINVAL;
  58
  59    if (!surf->blk_w || !surf->blk_h || !surf->blk_d)
  60       return -EINVAL;
  61
  62    switch (surf->nsamples) {
  63    case 1:
  64    case 2:
  65    case 4:
  66    case 8:
  67       break;
  68    default:
  69       return -EINVAL;
  70    }
  71
  72    switch (type) {
  73    case RADEON_SURF_TYPE_1D:
  74       if (surf->npix_y > 1)
  75          return -EINVAL;
  76       /* fall through */
  77    case RADEON_SURF_TYPE_2D:
  78    case RADEON_SURF_TYPE_CUBEMAP:
  79       if (surf->npix_z > 1 || surf->array_size > 1)
  80          return -EINVAL;
  81       break;
  82    case RADEON_SURF_TYPE_3D:
  83       if (surf->array_size > 1)
  84          return -EINVAL;
  85       break;
  86    case RADEON_SURF_TYPE_1D_ARRAY:
  87       if (surf->npix_y > 1)
  88          return -EINVAL;
  89       /* fall through */
  90    case RADEON_SURF_TYPE_2D_ARRAY:
  91       if (surf->npix_z > 1)
  92          return -EINVAL;
  93       break;
  94    default:
  95       return -EINVAL;
  96    }
  97    return 0;
  98 }
  99
 100 static void *ADDR_API allocSysMem(const ADDR_ALLOCSYSMEM_INPUT * pInput)
 101 {
 102    return malloc(pInput->sizeInBytes);
 103 }
 104
 105 static ADDR_E_RETURNCODE ADDR_API freeSysMem(const ADDR_FREESYSMEM_INPUT * pInput)
 106 {
 107    free(pInput->pVirtAddr);
 108    return ADDR_OK;
 109 }
 110
 111 /**
 112  * This returns the number of banks for the surface.
 113  * Possible values: 2, 4, 8, 16.
 114  */
 115 static uint32_t cik_num_banks(struct amdgpu_winsys *ws,
 116                               struct radeon_surf *surf)
 117 {
 118    unsigned index, tileb;
 119
 120    tileb = 8 * 8 * surf->bpe;
 121    tileb = MIN2(surf->tile_split, tileb);
 122
 123    for (index = 0; tileb > 64; index++) {
 124       tileb >>= 1;
 125    }
 126    assert(index < 16);
 127
 128    return 2 << ((ws->amdinfo.gb_macro_tile_mode[index] >> 6) & 0x3);
 129 }
 130
 131 ADDR_HANDLE amdgpu_addr_create(struct amdgpu_winsys *ws)
 132 {
 133    ADDR_CREATE_INPUT addrCreateInput = {0};
 134    ADDR_CREATE_OUTPUT addrCreateOutput = {0};
 135    ADDR_REGISTER_VALUE regValue = {0};
 136    ADDR_CREATE_FLAGS createFlags = {{0}};
 137    ADDR_E_RETURNCODE addrRet;
 138
 139    addrCreateInput.size = sizeof(ADDR_CREATE_INPUT);
 140    addrCreateOutput.size = sizeof(ADDR_CREATE_OUTPUT);
 141
 142    regValue.noOfBanks = ws->amdinfo.mc_arb_ramcfg & 0x3;
 143    regValue.gbAddrConfig = ws->amdinfo.gb_addr_cfg;
 144    regValue.noOfRanks = (ws->amdinfo.mc_arb_ramcfg & 0x4) >> 2;
 145
 146    regValue.backendDisables = ws->amdinfo.backend_disable[0];
 147    regValue.pTileConfig = ws->amdinfo.gb_tile_mode;
 148    regValue.noOfEntries = sizeof(ws->amdinfo.gb_tile_mode) /
 149                           sizeof(ws->amdinfo.gb_tile_mode[0]);
 150    regValue.pMacroTileConfig = ws->amdinfo.gb_macro_tile_mode;
 151    regValue.noOfMacroEntries = sizeof(ws->amdinfo.gb_macro_tile_mode) /
 152                                sizeof(ws->amdinfo.gb_macro_tile_mode[0]);
 153
 154    createFlags.value = 0;
 155    createFlags.useTileIndex = 1;
 156    createFlags.degradeBaseLevel = 1;
 157
 158    addrCreateInput.chipEngine = CIASICIDGFXENGINE_SOUTHERNISLAND;
 159    addrCreateInput.chipFamily = ws->family;
 160    addrCreateInput.chipRevision = ws->rev_id;
 161    addrCreateInput.createFlags = createFlags;
 162    addrCreateInput.callbacks.allocSysMem = allocSysMem;
 163    addrCreateInput.callbacks.freeSysMem = freeSysMem;
 164    addrCreateInput.callbacks.debugPrint = 0;
 165    addrCreateInput.regValue = regValue;
 166
 167    addrRet = AddrCreate(&addrCreateInput, &addrCreateOutput);
 168    if (addrRet != ADDR_OK)
 169       return NULL;
 170
 171    return addrCreateOutput.hLib;
 172 }
 173
 174 static int compute_level(struct amdgpu_winsys *ws,
 175                          struct radeon_surf *surf, bool is_stencil,
 176                          unsigned level, unsigned type, bool compressed,
 177                          ADDR_COMPUTE_SURFACE_INFO_INPUT *AddrSurfInfoIn,
 178                          ADDR_COMPUTE_SURFACE_INFO_OUTPUT *AddrSurfInfoOut,
 179                          ADDR_COMPUTE_DCCINFO_INPUT *AddrDccIn,
 180                          ADDR_COMPUTE_DCCINFO_OUTPUT *AddrDccOut)
 181 {
 182    struct radeon_surf_level *surf_level;
 183    ADDR_E_RETURNCODE ret;
 184
 185    AddrSurfInfoIn->mipLevel = level;
 186    AddrSurfInfoIn->width = u_minify(surf->npix_x, level);
 187    AddrSurfInfoIn->height = u_minify(surf->npix_y, level);
 188
 189    if (type == RADEON_SURF_TYPE_3D)
 190       AddrSurfInfoIn->numSlices = u_minify(surf->npix_z, level);
 191    else if (type == RADEON_SURF_TYPE_CUBEMAP)
 192       AddrSurfInfoIn->numSlices = 6;
 193    else
 194       AddrSurfInfoIn->numSlices = surf->array_size;
 195
 196    if (level > 0) {
 197       /* Set the base level pitch. This is needed for calculation
 198        * of non-zero levels. */
 199       if (is_stencil)
 200          AddrSurfInfoIn->basePitch = surf->stencil_level[0].nblk_x;
 201       else
 202          AddrSurfInfoIn->basePitch = surf->level[0].nblk_x;
 203
 204       /* Convert blocks to pixels for compressed formats. */
 205       if (compressed)
 206          AddrSurfInfoIn->basePitch *= surf->blk_w;
 207    }
 208
 209    ret = AddrComputeSurfaceInfo(ws->addrlib,
 210                                 AddrSurfInfoIn,
 211                                 AddrSurfInfoOut);
 212    if (ret != ADDR_OK) {
 213       return ret;
 214    }
 215
 216    surf_level = is_stencil ? &surf->stencil_level[level] : &surf->level[level];
 217    surf_level->offset = align(surf->bo_size, AddrSurfInfoOut->baseAlign);
 218    surf_level->slice_size = AddrSurfInfoOut->sliceSize;
 219    surf_level->pitch_bytes = AddrSurfInfoOut->pitch * (is_stencil ? 1 : surf->bpe);
 220    surf_level->npix_x = u_minify(surf->npix_x, level);
 221    surf_level->npix_y = u_minify(surf->npix_y, level);
 222    surf_level->npix_z = u_minify(surf->npix_z, level);
 223    surf_level->nblk_x = AddrSurfInfoOut->pitch;
 224    surf_level->nblk_y = AddrSurfInfoOut->height;
 225    if (type == RADEON_SURF_TYPE_3D)
 226       surf_level->nblk_z = AddrSurfInfoOut->depth;
 227    else
 228       surf_level->nblk_z = 1;
 229
 230    switch (AddrSurfInfoOut->tileMode) {
 231    case ADDR_TM_LINEAR_GENERAL:
 232       surf_level->mode = RADEON_SURF_MODE_LINEAR;
 233       break;
 234    case ADDR_TM_LINEAR_ALIGNED:
 235       surf_level->mode = RADEON_SURF_MODE_LINEAR_ALIGNED;
 236       break;
 237    case ADDR_TM_1D_TILED_THIN1:
 238       surf_level->mode = RADEON_SURF_MODE_1D;
 239       break;
 240    case ADDR_TM_2D_TILED_THIN1:
 241       surf_level->mode = RADEON_SURF_MODE_2D;
 242       break;
 243    default:
 244       assert(0);
 245    }
 246
 247    if (is_stencil)
 248       surf->stencil_tiling_index[level] = AddrSurfInfoOut->tileIndex;
 249    else
 250       surf->tiling_index[level] = AddrSurfInfoOut->tileIndex;
 251
 252    surf->bo_size = surf_level->offset + AddrSurfInfoOut->surfSize;
 253
 254    if (AddrSurfInfoIn->flags.dccCompatible) {
 255       AddrDccIn->colorSurfSize = AddrSurfInfoOut->surfSize;
 256       AddrDccIn->tileMode = AddrSurfInfoOut->tileMode;
 257       AddrDccIn->tileInfo = *AddrSurfInfoOut->pTileInfo;
 258       AddrDccIn->tileIndex = AddrSurfInfoOut->tileIndex;
 259       AddrDccIn->macroModeIndex = AddrSurfInfoOut->macroModeIndex;
 260
 261       ret = AddrComputeDccInfo(ws->addrlib,
 262                                AddrDccIn,
 263                                AddrDccOut);
 264
 265       if (ret == ADDR_OK) {
 266          surf_level->dcc_offset = surf->dcc_size;
 267          surf->dcc_size = surf_level->dcc_offset + AddrDccOut->dccRamSize;
 268          surf->dcc_alignment = MAX2(surf->dcc_alignment, AddrDccOut->dccRamBaseAlign);
 269       } else {
 270          surf->dcc_size = 0;
 271          surf_level->dcc_offset = 0;
 272       }
 273    } else {
 274       surf->dcc_size = 0;
 275       surf_level->dcc_offset = 0;
 276    }
 277
 278    return 0;
 279 }
 280
 281 static int amdgpu_surface_init(struct radeon_winsys *rws,
 282                                struct radeon_surf *surf)
 283 {
 284    struct amdgpu_winsys *ws = (struct amdgpu_winsys*)rws;
 285    unsigned level, mode, type;
 286    bool compressed;
 287    ADDR_COMPUTE_SURFACE_INFO_INPUT AddrSurfInfoIn = {0};
 288    ADDR_COMPUTE_SURFACE_INFO_OUTPUT AddrSurfInfoOut = {0};
 289    ADDR_COMPUTE_DCCINFO_INPUT AddrDccIn = {0};
 290    ADDR_COMPUTE_DCCINFO_OUTPUT AddrDccOut = {0};
 291    ADDR_TILEINFO AddrTileInfoIn = {0};
 292    ADDR_TILEINFO AddrTileInfoOut = {0};
 293    int r;
 294
 295    r = amdgpu_surface_sanity(surf);
 296    if (r)
 297       return r;
 298
 299    AddrSurfInfoIn.size = sizeof(ADDR_COMPUTE_SURFACE_INFO_INPUT);
 300    AddrSurfInfoOut.size = sizeof(ADDR_COMPUTE_SURFACE_INFO_OUTPUT);
 301    AddrDccIn.size = sizeof(ADDR_COMPUTE_DCCINFO_INPUT);
 302    AddrDccOut.size = sizeof(ADDR_COMPUTE_DCCINFO_OUTPUT);
 303    AddrSurfInfoOut.pTileInfo = &AddrTileInfoOut;
 304
 305    type = RADEON_SURF_GET(surf->flags, TYPE);
 306    mode = RADEON_SURF_GET(surf->flags, MODE);
 307    compressed = surf->blk_w == 4 && surf->blk_h == 4;
 308
 309    /* MSAA and FMASK require 2D tiling. */
 310    if (surf->nsamples > 1 ||
 311        (surf->flags & RADEON_SURF_FMASK))
 312       mode = RADEON_SURF_MODE_2D;
 313
 314    /* DB doesn't support linear layouts. */
 315    if (surf->flags & (RADEON_SURF_Z_OR_SBUFFER) &&
 316        mode < RADEON_SURF_MODE_1D)
 317       mode = RADEON_SURF_MODE_1D;
 318
 319    /* Set the requested tiling mode. */
 320    switch (mode) {
 321    case RADEON_SURF_MODE_LINEAR:
 322       AddrSurfInfoIn.tileMode = ADDR_TM_LINEAR_GENERAL;
 323       break;
 324    case RADEON_SURF_MODE_LINEAR_ALIGNED:
 325       AddrSurfInfoIn.tileMode = ADDR_TM_LINEAR_ALIGNED;
 326       break;
 327    case RADEON_SURF_MODE_1D:
 328       AddrSurfInfoIn.tileMode = ADDR_TM_1D_TILED_THIN1;
 329       break;
 330    case RADEON_SURF_MODE_2D:
 331       AddrSurfInfoIn.tileMode = ADDR_TM_2D_TILED_THIN1;
 332       break;
 333    default:
 334       assert(0);
 335    }
 336
 337    /* The format must be set correctly for the allocation of compressed
 338     * textures to work. In other cases, setting the bpp is sufficient. */
 339    if (compressed) {
 340       switch (surf->bpe) {
 341       case 8:
 342          AddrSurfInfoIn.format = ADDR_FMT_BC1;
 343          break;
 344       case 16:
 345          AddrSurfInfoIn.format = ADDR_FMT_BC3;
 346          break;
 347       default:
 348          assert(0);
 349       }
 350    }
 351    else {
 352       AddrDccIn.bpp = AddrSurfInfoIn.bpp = surf->bpe * 8;
 353    }
 354
 355    AddrDccIn.numSamples = AddrSurfInfoIn.numSamples = surf->nsamples;
 356    AddrSurfInfoIn.tileIndex = -1;
 357
 358    /* Set the micro tile type. */
 359    if (surf->flags & RADEON_SURF_SCANOUT)
 360       AddrSurfInfoIn.tileType = ADDR_DISPLAYABLE;
 361    else if (surf->flags & RADEON_SURF_Z_OR_SBUFFER)
 362       AddrSurfInfoIn.tileType = ADDR_DEPTH_SAMPLE_ORDER;
 363    else
 364       AddrSurfInfoIn.tileType = ADDR_NON_DISPLAYABLE;
 365
 366    AddrSurfInfoIn.flags.color = !(surf->flags & RADEON_SURF_Z_OR_SBUFFER);
 367    AddrSurfInfoIn.flags.depth = (surf->flags & RADEON_SURF_ZBUFFER) != 0;
 368    AddrSurfInfoIn.flags.stencil = (surf->flags & RADEON_SURF_SBUFFER) != 0;
 369    AddrSurfInfoIn.flags.cube = type == RADEON_SURF_TYPE_CUBEMAP;
 370    AddrSurfInfoIn.flags.display = (surf->flags & RADEON_SURF_SCANOUT) != 0;
 371    AddrSurfInfoIn.flags.pow2Pad = surf->last_level > 0;
 372    AddrSurfInfoIn.flags.degrade4Space = 1;
 373    AddrSurfInfoIn.flags.dccCompatible = !(surf->flags & RADEON_SURF_Z_OR_SBUFFER) &&
 374                                         !(surf->flags & RADEON_SURF_SCANOUT) &&
 375                                         !compressed && AddrDccIn.numSamples <= 1;
 376
 377    /* This disables incorrect calculations (hacks) in addrlib. */
 378    AddrSurfInfoIn.flags.noStencil = 1;
 379
 380    /* Set preferred macrotile parameters. This is usually required
 381     * for shared resources. This is for 2D tiling only. */
 382    if (AddrSurfInfoIn.tileMode >= ADDR_TM_2D_TILED_THIN1 &&
 383        surf->bankw && surf->bankh && surf->mtilea && surf->tile_split) {
 384       /* If any of these parameters are incorrect, the calculation
 385        * will fail. */
 386       AddrTileInfoIn.banks = cik_num_banks(ws, surf);
 387       AddrTileInfoIn.bankWidth = surf->bankw;
 388       AddrTileInfoIn.bankHeight = surf->bankh;
 389       AddrTileInfoIn.macroAspectRatio = surf->mtilea;
 390       AddrTileInfoIn.tileSplitBytes = surf->tile_split;
 391       AddrSurfInfoIn.flags.degrade4Space = 0;
 392       AddrSurfInfoIn.pTileInfo = &AddrTileInfoIn;
 393
 394       /* If AddrSurfInfoIn.pTileInfo is set, Addrlib doesn't set
 395        * the tile index, because we are expected to know it if
 396        * we know the other parameters.
 397        *
 398        * This is something that can easily be fixed in Addrlib.
 399        * For now, just figure it out here.
 400        * Note that only 2D_TILE_THIN1 is handled here.
 401        */
 402       assert(!(surf->flags & RADEON_SURF_Z_OR_SBUFFER));
 403       assert(AddrSurfInfoIn.tileMode == ADDR_TM_2D_TILED_THIN1);
 404
 405       if (AddrSurfInfoIn.tileType == ADDR_DISPLAYABLE)
 406          AddrSurfInfoIn.tileIndex = 10; /* 2D displayable */
 407       else
 408          AddrSurfInfoIn.tileIndex = 14; /* 2D non-displayable */
 409    }
 410
 411    surf->bo_size = 0;
 412    surf->dcc_size = 0;
 413    surf->dcc_alignment = 1;
 414
 415    /* Calculate texture layout information. */
 416    for (level = 0; level <= surf->last_level; level++) {
 417       r = compute_level(ws, surf, false, level, type, compressed,
 418                         &AddrSurfInfoIn, &AddrSurfInfoOut, &AddrDccIn, &AddrDccOut);
 419       if (r)
 420          return r;
 421
 422       if (level == 0) {
 423          surf->bo_alignment = AddrSurfInfoOut.baseAlign;
 424          surf->pipe_config = AddrSurfInfoOut.pTileInfo->pipeConfig - 1;
 425
 426          /* For 2D modes only. */
 427          if (AddrSurfInfoOut.tileMode >= ADDR_TM_2D_TILED_THIN1) {
 428             surf->bankw = AddrSurfInfoOut.pTileInfo->bankWidth;
 429             surf->bankh = AddrSurfInfoOut.pTileInfo->bankHeight;
 430             surf->mtilea = AddrSurfInfoOut.pTileInfo->macroAspectRatio;
 431             surf->tile_split = AddrSurfInfoOut.pTileInfo->tileSplitBytes;
 432             surf->num_banks = AddrSurfInfoOut.pTileInfo->banks;
 433          }
 434       }
 435    }
 436
 437    /* Calculate texture layout information for stencil. */
 438    if (surf->flags & RADEON_SURF_SBUFFER) {
 439       AddrSurfInfoIn.bpp = 8;
 440       /* This will be ignored if AddrSurfInfoIn.pTileInfo is NULL. */
 441       AddrTileInfoIn.tileSplitBytes = surf->stencil_tile_split;
 442
 443       for (level = 0; level <= surf->last_level; level++) {
 444          r = compute_level(ws, surf, true, level, type, compressed,
 445                            &AddrSurfInfoIn, &AddrSurfInfoOut, &AddrDccIn, &AddrDccOut);
 446          if (r)
 447             return r;
 448
 449          if (level == 0) {
 450             surf->stencil_offset = surf->stencil_level[0].offset;
 451
 452             /* For 2D modes only. */
 453             if (AddrSurfInfoOut.tileMode >= ADDR_TM_2D_TILED_THIN1) {
 454                surf->stencil_tile_split =
 455                      AddrSurfInfoOut.pTileInfo->tileSplitBytes;
 456             }
 457          }
 458       }
 459    }
 460
 461    return 0;
 462 }
 463
 464 static int amdgpu_surface_best(struct radeon_winsys *rws,
 465                                struct radeon_surf *surf)
 466 {
 467    return 0;
 468 }
 469
 470 void amdgpu_surface_init_functions(struct amdgpu_winsys *ws)
 471 {
 472    ws->base.surface_init = amdgpu_surface_init;
 473    ws->base.surface_best = amdgpu_surface_best;
 474 }