src/gallium/winsys/amdgpu/drm/amdgpu_winsys.c

   1 /*
   2  * Copyright © 2009 Corbin Simpson <MostAwesomeDude@gmail.com>
   3  * Copyright © 2009 Joakim Sindholt <opensource@zhasha.com>
   4  * Copyright © 2011 Marek Olšák <maraeo@gmail.com>
   5  * Copyright © 2015 Advanced Micro Devices, Inc.
   6  * All Rights Reserved.
   7  *
   8  * Permission is hereby granted, free of charge, to any person obtaining
   9  * a copy of this software and associated documentation files (the
  10  * "Software"), to deal in the Software without restriction, including
  11  * without limitation the rights to use, copy, modify, merge, publish,
  12  * distribute, sub license, and/or sell copies of the Software, and to
  13  * permit persons to whom the Software is furnished to do so, subject to
  14  * the following conditions:
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  17  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
  18  * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  19  * NON-INFRINGEMENT. IN NO EVENT SHALL THE COPYRIGHT HOLDERS, AUTHORS
  20  * AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  21  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  22  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
  23  * USE OR OTHER DEALINGS IN THE SOFTWARE.
  24  *
  25  * The above copyright notice and this permission notice (including the
  26  * next paragraph) shall be included in all copies or substantial portions
  27  * of the Software.
  28  */
  29 /*
  30  * Authors:
  31  *      Marek Olšák <maraeo@gmail.com>
  32  */
  33
  34 #include "amdgpu_cs.h"
  35 #include "amdgpu_public.h"
  36
  37 #include "util/u_hash_table.h"
  38 #include <amdgpu_drm.h>
  39 #include <xf86drm.h>
  40 #include <stdio.h>
  41 #include <sys/stat.h>
  42 #include "amd/common/amdgpu_id.h"
  43 #include "amd/common/sid.h"
  44 #include "amd/common/gfx9d.h"
  45
  46 #ifndef AMDGPU_INFO_NUM_VRAM_CPU_PAGE_FAULTS
  47 #define AMDGPU_INFO_NUM_VRAM_CPU_PAGE_FAULTS    0x1E
  48 #endif
  49
  50 static struct util_hash_table *dev_tab = NULL;
  51 static mtx_t dev_tab_mutex = _MTX_INITIALIZER_NP;
  52
  53 DEBUG_GET_ONCE_BOOL_OPTION(all_bos, "RADEON_ALL_BOS", false)
  54
  55 /* Helper function to do the ioctls needed for setup and init. */
  56 static bool do_winsys_init(struct amdgpu_winsys *ws, int fd)
  57 {
  58    if (!ac_query_gpu_info(fd, ws->dev, &ws->info, &ws->amdinfo))
  59       goto fail;
  60
  61    /* LLVM 5.0 is required for GFX9. */
  62    if (ws->info.chip_class >= GFX9 && HAVE_LLVM < 0x0500) {
  63       fprintf(stderr, "amdgpu: LLVM 5.0 is required, got LLVM %i.%i\n",
  64               HAVE_LLVM >> 8, HAVE_LLVM & 255);
  65       goto fail;
  66    }
  67
  68    ws->addrlib = amdgpu_addr_create(&ws->info, &ws->amdinfo, &ws->info.max_alignment);
  69    if (!ws->addrlib) {
  70       fprintf(stderr, "amdgpu: Cannot create addrlib.\n");
  71       goto fail;
  72    }
  73
  74    ws->check_vm = strstr(debug_get_option("R600_DEBUG", ""), "check_vm") != NULL;
  75    ws->debug_all_bos = debug_get_option_all_bos();
  76
  77    return true;
  78
  79 fail:
  80    amdgpu_device_deinitialize(ws->dev);
  81    ws->dev = NULL;
  82    return false;
  83 }
  84
  85 static void do_winsys_deinit(struct amdgpu_winsys *ws)
  86 {
  87    AddrDestroy(ws->addrlib);
  88    amdgpu_device_deinitialize(ws->dev);
  89 }
  90
  91 static void amdgpu_winsys_destroy(struct radeon_winsys *rws)
  92 {
  93    struct amdgpu_winsys *ws = (struct amdgpu_winsys*)rws;
  94
  95    if (util_queue_is_initialized(&ws->cs_queue))
  96       util_queue_destroy(&ws->cs_queue);
  97
  98    mtx_destroy(&ws->bo_fence_lock);
  99    pb_slabs_deinit(&ws->bo_slabs);
 100    pb_cache_deinit(&ws->bo_cache);
 101    mtx_destroy(&ws->global_bo_list_lock);
 102    do_winsys_deinit(ws);
 103    FREE(rws);
 104 }
 105
 106 static void amdgpu_winsys_query_info(struct radeon_winsys *rws,
 107                                      struct radeon_info *info)
 108 {
 109    *info = ((struct amdgpu_winsys *)rws)->info;
 110 }
 111
 112 static bool amdgpu_cs_request_feature(struct radeon_winsys_cs *rcs,
 113                                       enum radeon_feature_id fid,
 114                                       bool enable)
 115 {
 116    return false;
 117 }
 118
 119 static uint64_t amdgpu_query_value(struct radeon_winsys *rws,
 120                                    enum radeon_value_id value)
 121 {
 122    struct amdgpu_winsys *ws = (struct amdgpu_winsys*)rws;
 123    struct amdgpu_heap_info heap;
 124    uint64_t retval = 0;
 125
 126    switch (value) {
 127    case RADEON_REQUESTED_VRAM_MEMORY:
 128       return ws->allocated_vram;
 129    case RADEON_REQUESTED_GTT_MEMORY:
 130       return ws->allocated_gtt;
 131    case RADEON_MAPPED_VRAM:
 132       return ws->mapped_vram;
 133    case RADEON_MAPPED_GTT:
 134       return ws->mapped_gtt;
 135    case RADEON_BUFFER_WAIT_TIME_NS:
 136       return ws->buffer_wait_time;
 137    case RADEON_NUM_MAPPED_BUFFERS:
 138       return ws->num_mapped_buffers;
 139    case RADEON_TIMESTAMP:
 140       amdgpu_query_info(ws->dev, AMDGPU_INFO_TIMESTAMP, 8, &retval);
 141       return retval;
 142    case RADEON_NUM_GFX_IBS:
 143       return ws->num_gfx_IBs;
 144    case RADEON_NUM_SDMA_IBS:
 145       return ws->num_sdma_IBs;
 146    case RADEON_GFX_BO_LIST_COUNTER:
 147       return ws->gfx_bo_list_counter;
 148    case RADEON_NUM_BYTES_MOVED:
 149       amdgpu_query_info(ws->dev, AMDGPU_INFO_NUM_BYTES_MOVED, 8, &retval);
 150       return retval;
 151    case RADEON_NUM_EVICTIONS:
 152       amdgpu_query_info(ws->dev, AMDGPU_INFO_NUM_EVICTIONS, 8, &retval);
 153       return retval;
 154    case RADEON_NUM_VRAM_CPU_PAGE_FAULTS:
 155       amdgpu_query_info(ws->dev, AMDGPU_INFO_NUM_VRAM_CPU_PAGE_FAULTS, 8, &retval);
 156       return retval;
 157    case RADEON_VRAM_USAGE:
 158       amdgpu_query_heap_info(ws->dev, AMDGPU_GEM_DOMAIN_VRAM, 0, &heap);
 159       return heap.heap_usage;
 160    case RADEON_VRAM_VIS_USAGE:
 161       amdgpu_query_heap_info(ws->dev, AMDGPU_GEM_DOMAIN_VRAM,
 162                              AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED, &heap);
 163       return heap.heap_usage;
 164    case RADEON_GTT_USAGE:
 165       amdgpu_query_heap_info(ws->dev, AMDGPU_GEM_DOMAIN_GTT, 0, &heap);
 166       return heap.heap_usage;
 167    case RADEON_GPU_TEMPERATURE:
 168       amdgpu_query_sensor_info(ws->dev, AMDGPU_INFO_SENSOR_GPU_TEMP, 4, &retval);
 169       return retval;
 170    case RADEON_CURRENT_SCLK:
 171       amdgpu_query_sensor_info(ws->dev, AMDGPU_INFO_SENSOR_GFX_SCLK, 4, &retval);
 172       return retval;
 173    case RADEON_CURRENT_MCLK:
 174       amdgpu_query_sensor_info(ws->dev, AMDGPU_INFO_SENSOR_GFX_MCLK, 4, &retval);
 175       return retval;
 176    case RADEON_GPU_RESET_COUNTER:
 177       assert(0);
 178       return 0;
 179    case RADEON_CS_THREAD_TIME:
 180       return util_queue_get_thread_time_nano(&ws->cs_queue, 0);
 181    }
 182    return 0;
 183 }
 184
 185 static bool amdgpu_read_registers(struct radeon_winsys *rws,
 186                                   unsigned reg_offset,
 187                                   unsigned num_registers, uint32_t *out)
 188 {
 189    struct amdgpu_winsys *ws = (struct amdgpu_winsys*)rws;
 190
 191    return amdgpu_read_mm_registers(ws->dev, reg_offset / 4, num_registers,
 192                                    0xffffffff, 0, out) == 0;
 193 }
 194
 195 static unsigned hash_dev(void *key)
 196 {
 197 #if defined(PIPE_ARCH_X86_64)
 198    return pointer_to_intptr(key) ^ (pointer_to_intptr(key) >> 32);
 199 #else
 200    return pointer_to_intptr(key);
 201 #endif
 202 }
 203
 204 static int compare_dev(void *key1, void *key2)
 205 {
 206    return key1 != key2;
 207 }
 208
 209 static bool amdgpu_winsys_unref(struct radeon_winsys *rws)
 210 {
 211    struct amdgpu_winsys *ws = (struct amdgpu_winsys*)rws;
 212    bool destroy;
 213
 214    /* When the reference counter drops to zero, remove the device pointer
 215     * from the table.
 216     * This must happen while the mutex is locked, so that
 217     * amdgpu_winsys_create in another thread doesn't get the winsys
 218     * from the table when the counter drops to 0. */
 219    mtx_lock(&dev_tab_mutex);
 220
 221    destroy = pipe_reference(&ws->reference, NULL);
 222    if (destroy && dev_tab)
 223       util_hash_table_remove(dev_tab, ws->dev);
 224
 225    mtx_unlock(&dev_tab_mutex);
 226    return destroy;
 227 }
 228
 229 static const char* amdgpu_get_chip_name(struct radeon_winsys *ws)
 230 {
 231    amdgpu_device_handle dev = ((struct amdgpu_winsys *)ws)->dev;
 232    return amdgpu_get_marketing_name(dev);
 233 }
 234
 235
 236 PUBLIC struct radeon_winsys *
 237 amdgpu_winsys_create(int fd, const struct pipe_screen_config *config,
 238                      radeon_screen_create_t screen_create)
 239 {
 240    struct amdgpu_winsys *ws;
 241    drmVersionPtr version = drmGetVersion(fd);
 242    amdgpu_device_handle dev;
 243    uint32_t drm_major, drm_minor, r;
 244
 245    /* The DRM driver version of amdgpu is 3.x.x. */
 246    if (version->version_major != 3) {
 247       drmFreeVersion(version);
 248       return NULL;
 249    }
 250    drmFreeVersion(version);
 251
 252    /* Look up the winsys from the dev table. */
 253    mtx_lock(&dev_tab_mutex);
 254    if (!dev_tab)
 255       dev_tab = util_hash_table_create(hash_dev, compare_dev);
 256
 257    /* Initialize the amdgpu device. This should always return the same pointer
 258     * for the same fd. */
 259    r = amdgpu_device_initialize(fd, &drm_major, &drm_minor, &dev);
 260    if (r) {
 261       mtx_unlock(&dev_tab_mutex);
 262       fprintf(stderr, "amdgpu: amdgpu_device_initialize failed.\n");
 263       return NULL;
 264    }
 265
 266    /* Lookup a winsys if we have already created one for this device. */
 267    ws = util_hash_table_get(dev_tab, dev);
 268    if (ws) {
 269       pipe_reference(NULL, &ws->reference);
 270       mtx_unlock(&dev_tab_mutex);
 271       return &ws->base;
 272    }
 273
 274    /* Create a new winsys. */
 275    ws = CALLOC_STRUCT(amdgpu_winsys);
 276    if (!ws)
 277       goto fail;
 278
 279    ws->dev = dev;
 280    ws->info.drm_major = drm_major;
 281    ws->info.drm_minor = drm_minor;
 282
 283    if (!do_winsys_init(ws, fd))
 284       goto fail_alloc;
 285
 286    /* Create managers. */
 287    pb_cache_init(&ws->bo_cache, 500000, ws->check_vm ? 1.0f : 2.0f, 0,
 288                  (ws->info.vram_size + ws->info.gart_size) / 8,
 289                  amdgpu_bo_destroy, amdgpu_bo_can_reclaim);
 290
 291    if (!pb_slabs_init(&ws->bo_slabs,
 292                       AMDGPU_SLAB_MIN_SIZE_LOG2, AMDGPU_SLAB_MAX_SIZE_LOG2,
 293                       RADEON_MAX_SLAB_HEAPS,
 294                       ws,
 295                       amdgpu_bo_can_reclaim_slab,
 296                       amdgpu_bo_slab_alloc,
 297                       amdgpu_bo_slab_free))
 298       goto fail_cache;
 299
 300    ws->info.min_alloc_size = 1 << AMDGPU_SLAB_MIN_SIZE_LOG2;
 301
 302    /* init reference */
 303    pipe_reference_init(&ws->reference, 1);
 304
 305    /* Set functions. */
 306    ws->base.unref = amdgpu_winsys_unref;
 307    ws->base.destroy = amdgpu_winsys_destroy;
 308    ws->base.query_info = amdgpu_winsys_query_info;
 309    ws->base.cs_request_feature = amdgpu_cs_request_feature;
 310    ws->base.query_value = amdgpu_query_value;
 311    ws->base.read_registers = amdgpu_read_registers;
 312    ws->base.get_chip_name = amdgpu_get_chip_name;
 313
 314    amdgpu_bo_init_functions(ws);
 315    amdgpu_cs_init_functions(ws);
 316    amdgpu_surface_init_functions(ws);
 317
 318    LIST_INITHEAD(&ws->global_bo_list);
 319    (void) mtx_init(&ws->global_bo_list_lock, mtx_plain);
 320    (void) mtx_init(&ws->bo_fence_lock, mtx_plain);
 321
 322    if (!util_queue_init(&ws->cs_queue, "amdgpu_cs", 8, 1,
 323                         UTIL_QUEUE_INIT_RESIZE_IF_FULL)) {
 324       amdgpu_winsys_destroy(&ws->base);
 325       mtx_unlock(&dev_tab_mutex);
 326       return NULL;
 327    }
 328
 329    /* Create the screen at the end. The winsys must be initialized
 330     * completely.
 331     *
 332     * Alternatively, we could create the screen based on "ws->gen"
 333     * and link all drivers into one binary blob. */
 334    ws->base.screen = screen_create(&ws->base, config);
 335    if (!ws->base.screen) {
 336       amdgpu_winsys_destroy(&ws->base);
 337       mtx_unlock(&dev_tab_mutex);
 338       return NULL;
 339    }
 340
 341    util_hash_table_set(dev_tab, dev, ws);
 342
 343    /* We must unlock the mutex once the winsys is fully initialized, so that
 344     * other threads attempting to create the winsys from the same fd will
 345     * get a fully initialized winsys and not just half-way initialized. */
 346    mtx_unlock(&dev_tab_mutex);
 347
 348    return &ws->base;
 349
 350 fail_cache:
 351    pb_cache_deinit(&ws->bo_cache);
 352    do_winsys_deinit(ws);
 353 fail_alloc:
 354    FREE(ws);
 355 fail:
 356    mtx_unlock(&dev_tab_mutex);
 357    return NULL;
 358 }