src/gallium/winsys/amdgpu/drm/amdgpu_winsys.c

   1 /*
   2  * Copyright © 2009 Corbin Simpson <MostAwesomeDude@gmail.com>
   3  * Copyright © 2009 Joakim Sindholt <opensource@zhasha.com>
   4  * Copyright © 2011 Marek Olšák <maraeo@gmail.com>
   5  * Copyright © 2015 Advanced Micro Devices, Inc.
   6  * All Rights Reserved.
   7  *
   8  * Permission is hereby granted, free of charge, to any person obtaining
   9  * a copy of this software and associated documentation files (the
  10  * "Software"), to deal in the Software without restriction, including
  11  * without limitation the rights to use, copy, modify, merge, publish,
  12  * distribute, sub license, and/or sell copies of the Software, and to
  13  * permit persons to whom the Software is furnished to do so, subject to
  14  * the following conditions:
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  17  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
  18  * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  19  * NON-INFRINGEMENT. IN NO EVENT SHALL THE COPYRIGHT HOLDERS, AUTHORS
  20  * AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  21  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  22  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
  23  * USE OR OTHER DEALINGS IN THE SOFTWARE.
  24  *
  25  * The above copyright notice and this permission notice (including the
  26  * next paragraph) shall be included in all copies or substantial portions
  27  * of the Software.
  28  */
  29
  30 #include "amdgpu_cs.h"
  31 #include "amdgpu_public.h"
  32
  33 #include "util/u_cpu_detect.h"
  34 #include "util/u_hash_table.h"
  35 #include "util/hash_table.h"
  36 #include "util/xmlconfig.h"
  37 #include <amdgpu_drm.h>
  38 #include <xf86drm.h>
  39 #include <stdio.h>
  40 #include <sys/stat.h>
  41 #include "amd/common/sid.h"
  42 #include "amd/common/gfx9d.h"
  43
  44 #ifndef AMDGPU_INFO_NUM_VRAM_CPU_PAGE_FAULTS
  45 #define AMDGPU_INFO_NUM_VRAM_CPU_PAGE_FAULTS    0x1E
  46 #endif
  47
  48 static struct util_hash_table *dev_tab = NULL;
  49 static simple_mtx_t dev_tab_mutex = _SIMPLE_MTX_INITIALIZER_NP;
  50
  51 DEBUG_GET_ONCE_BOOL_OPTION(all_bos, "RADEON_ALL_BOS", false)
  52
  53 /* Helper function to do the ioctls needed for setup and init. */
  54 static bool do_winsys_init(struct amdgpu_winsys *ws,
  55                            const struct pipe_screen_config *config,
  56                            int fd)
  57 {
  58    if (!ac_query_gpu_info(fd, ws->dev, &ws->info, &ws->amdinfo))
  59       goto fail;
  60
  61    ws->addrlib = amdgpu_addr_create(&ws->info, &ws->amdinfo, &ws->info.max_alignment);
  62    if (!ws->addrlib) {
  63       fprintf(stderr, "amdgpu: Cannot create addrlib.\n");
  64       goto fail;
  65    }
  66
  67    ws->check_vm = strstr(debug_get_option("R600_DEBUG", ""), "check_vm") != NULL;
  68    ws->debug_all_bos = debug_get_option_all_bos();
  69    ws->reserve_vmid = strstr(debug_get_option("R600_DEBUG", ""), "reserve_vmid") != NULL;
  70    ws->zero_all_vram_allocs = strstr(debug_get_option("R600_DEBUG", ""), "zerovram") != NULL ||
  71       driQueryOptionb(config->options, "radeonsi_zerovram");
  72
  73    return true;
  74
  75 fail:
  76    amdgpu_device_deinitialize(ws->dev);
  77    ws->dev = NULL;
  78    return false;
  79 }
  80
  81 static void do_winsys_deinit(struct amdgpu_winsys *ws)
  82 {
  83    AddrDestroy(ws->addrlib);
  84    amdgpu_device_deinitialize(ws->dev);
  85 }
  86
  87 static void amdgpu_winsys_destroy(struct radeon_winsys *rws)
  88 {
  89    struct amdgpu_winsys *ws = (struct amdgpu_winsys*)rws;
  90
  91    if (ws->reserve_vmid)
  92       amdgpu_vm_unreserve_vmid(ws->dev, 0);
  93
  94    if (util_queue_is_initialized(&ws->cs_queue))
  95       util_queue_destroy(&ws->cs_queue);
  96
  97    simple_mtx_destroy(&ws->bo_fence_lock);
  98    for (unsigned i = 0; i < NUM_SLAB_ALLOCATORS; i++) {
  99       if (ws->bo_slabs[i].groups)
 100          pb_slabs_deinit(&ws->bo_slabs[i]);
 101    }
 102    pb_cache_deinit(&ws->bo_cache);
 103    util_hash_table_destroy(ws->bo_export_table);
 104    simple_mtx_destroy(&ws->global_bo_list_lock);
 105    simple_mtx_destroy(&ws->bo_export_table_lock);
 106    do_winsys_deinit(ws);
 107    FREE(rws);
 108 }
 109
 110 static void amdgpu_winsys_query_info(struct radeon_winsys *rws,
 111                                      struct radeon_info *info)
 112 {
 113    *info = ((struct amdgpu_winsys *)rws)->info;
 114 }
 115
 116 static bool amdgpu_cs_request_feature(struct radeon_cmdbuf *rcs,
 117                                       enum radeon_feature_id fid,
 118                                       bool enable)
 119 {
 120    return false;
 121 }
 122
 123 static uint64_t amdgpu_query_value(struct radeon_winsys *rws,
 124                                    enum radeon_value_id value)
 125 {
 126    struct amdgpu_winsys *ws = (struct amdgpu_winsys*)rws;
 127    struct amdgpu_heap_info heap;
 128    uint64_t retval = 0;
 129
 130    switch (value) {
 131    case RADEON_REQUESTED_VRAM_MEMORY:
 132       return ws->allocated_vram;
 133    case RADEON_REQUESTED_GTT_MEMORY:
 134       return ws->allocated_gtt;
 135    case RADEON_MAPPED_VRAM:
 136       return ws->mapped_vram;
 137    case RADEON_MAPPED_GTT:
 138       return ws->mapped_gtt;
 139    case RADEON_BUFFER_WAIT_TIME_NS:
 140       return ws->buffer_wait_time;
 141    case RADEON_NUM_MAPPED_BUFFERS:
 142       return ws->num_mapped_buffers;
 143    case RADEON_TIMESTAMP:
 144       amdgpu_query_info(ws->dev, AMDGPU_INFO_TIMESTAMP, 8, &retval);
 145       return retval;
 146    case RADEON_NUM_GFX_IBS:
 147       return ws->num_gfx_IBs;
 148    case RADEON_NUM_SDMA_IBS:
 149       return ws->num_sdma_IBs;
 150    case RADEON_GFX_BO_LIST_COUNTER:
 151       return ws->gfx_bo_list_counter;
 152    case RADEON_GFX_IB_SIZE_COUNTER:
 153       return ws->gfx_ib_size_counter;
 154    case RADEON_NUM_BYTES_MOVED:
 155       amdgpu_query_info(ws->dev, AMDGPU_INFO_NUM_BYTES_MOVED, 8, &retval);
 156       return retval;
 157    case RADEON_NUM_EVICTIONS:
 158       amdgpu_query_info(ws->dev, AMDGPU_INFO_NUM_EVICTIONS, 8, &retval);
 159       return retval;
 160    case RADEON_NUM_VRAM_CPU_PAGE_FAULTS:
 161       amdgpu_query_info(ws->dev, AMDGPU_INFO_NUM_VRAM_CPU_PAGE_FAULTS, 8, &retval);
 162       return retval;
 163    case RADEON_VRAM_USAGE:
 164       amdgpu_query_heap_info(ws->dev, AMDGPU_GEM_DOMAIN_VRAM, 0, &heap);
 165       return heap.heap_usage;
 166    case RADEON_VRAM_VIS_USAGE:
 167       amdgpu_query_heap_info(ws->dev, AMDGPU_GEM_DOMAIN_VRAM,
 168                              AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED, &heap);
 169       return heap.heap_usage;
 170    case RADEON_GTT_USAGE:
 171       amdgpu_query_heap_info(ws->dev, AMDGPU_GEM_DOMAIN_GTT, 0, &heap);
 172       return heap.heap_usage;
 173    case RADEON_GPU_TEMPERATURE:
 174       amdgpu_query_sensor_info(ws->dev, AMDGPU_INFO_SENSOR_GPU_TEMP, 4, &retval);
 175       return retval;
 176    case RADEON_CURRENT_SCLK:
 177       amdgpu_query_sensor_info(ws->dev, AMDGPU_INFO_SENSOR_GFX_SCLK, 4, &retval);
 178       return retval;
 179    case RADEON_CURRENT_MCLK:
 180       amdgpu_query_sensor_info(ws->dev, AMDGPU_INFO_SENSOR_GFX_MCLK, 4, &retval);
 181       return retval;
 182    case RADEON_GPU_RESET_COUNTER:
 183       assert(0);
 184       return 0;
 185    case RADEON_CS_THREAD_TIME:
 186       return util_queue_get_thread_time_nano(&ws->cs_queue, 0);
 187    }
 188    return 0;
 189 }
 190
 191 static bool amdgpu_read_registers(struct radeon_winsys *rws,
 192                                   unsigned reg_offset,
 193                                   unsigned num_registers, uint32_t *out)
 194 {
 195    struct amdgpu_winsys *ws = (struct amdgpu_winsys*)rws;
 196
 197    return amdgpu_read_mm_registers(ws->dev, reg_offset / 4, num_registers,
 198                                    0xffffffff, 0, out) == 0;
 199 }
 200
 201 static unsigned hash_pointer(void *key)
 202 {
 203    return _mesa_hash_pointer(key);
 204 }
 205
 206 static int compare_pointers(void *key1, void *key2)
 207 {
 208    return key1 != key2;
 209 }
 210
 211 static bool amdgpu_winsys_unref(struct radeon_winsys *rws)
 212 {
 213    struct amdgpu_winsys *ws = (struct amdgpu_winsys*)rws;
 214    bool destroy;
 215
 216    /* When the reference counter drops to zero, remove the device pointer
 217     * from the table.
 218     * This must happen while the mutex is locked, so that
 219     * amdgpu_winsys_create in another thread doesn't get the winsys
 220     * from the table when the counter drops to 0. */
 221    simple_mtx_lock(&dev_tab_mutex);
 222
 223    destroy = pipe_reference(&ws->reference, NULL);
 224    if (destroy && dev_tab) {
 225       util_hash_table_remove(dev_tab, ws->dev);
 226       if (util_hash_table_count(dev_tab) == 0) {
 227          util_hash_table_destroy(dev_tab);
 228          dev_tab = NULL;
 229       }
 230    }
 231
 232    simple_mtx_unlock(&dev_tab_mutex);
 233    return destroy;
 234 }
 235
 236 static const char* amdgpu_get_chip_name(struct radeon_winsys *ws)
 237 {
 238    amdgpu_device_handle dev = ((struct amdgpu_winsys *)ws)->dev;
 239    return amdgpu_get_marketing_name(dev);
 240 }
 241
 242 static void amdgpu_pin_threads_to_L3_cache(struct radeon_winsys *rws,
 243                                            unsigned cache)
 244 {
 245    struct amdgpu_winsys *ws = (struct amdgpu_winsys*)rws;
 246
 247    util_pin_thread_to_L3(ws->cs_queue.threads[0], cache,
 248                          util_cpu_caps.cores_per_L3);
 249 }
 250
 251 PUBLIC struct radeon_winsys *
 252 amdgpu_winsys_create(int fd, const struct pipe_screen_config *config,
 253                      radeon_screen_create_t screen_create)
 254 {
 255    struct amdgpu_winsys *ws;
 256    drmVersionPtr version = drmGetVersion(fd);
 257    amdgpu_device_handle dev;
 258    uint32_t drm_major, drm_minor, r;
 259
 260    /* The DRM driver version of amdgpu is 3.x.x. */
 261    if (version->version_major != 3) {
 262       drmFreeVersion(version);
 263       return NULL;
 264    }
 265    drmFreeVersion(version);
 266
 267    /* Look up the winsys from the dev table. */
 268    simple_mtx_lock(&dev_tab_mutex);
 269    if (!dev_tab)
 270       dev_tab = util_hash_table_create(hash_pointer, compare_pointers);
 271
 272    /* Initialize the amdgpu device. This should always return the same pointer
 273     * for the same fd. */
 274    r = amdgpu_device_initialize(fd, &drm_major, &drm_minor, &dev);
 275    if (r) {
 276       simple_mtx_unlock(&dev_tab_mutex);
 277       fprintf(stderr, "amdgpu: amdgpu_device_initialize failed.\n");
 278       return NULL;
 279    }
 280
 281    /* Lookup a winsys if we have already created one for this device. */
 282    ws = util_hash_table_get(dev_tab, dev);
 283    if (ws) {
 284       pipe_reference(NULL, &ws->reference);
 285       simple_mtx_unlock(&dev_tab_mutex);
 286
 287       /* Release the device handle, because we don't need it anymore.
 288        * This function is returning an existing winsys instance, which
 289        * has its own device handle.
 290        */
 291       amdgpu_device_deinitialize(dev);
 292       return &ws->base;
 293    }
 294
 295    /* Create a new winsys. */
 296    ws = CALLOC_STRUCT(amdgpu_winsys);
 297    if (!ws)
 298       goto fail;
 299
 300    ws->dev = dev;
 301    ws->info.drm_major = drm_major;
 302    ws->info.drm_minor = drm_minor;
 303
 304    if (!do_winsys_init(ws, config, fd))
 305       goto fail_alloc;
 306
 307    /* Create managers. */
 308    pb_cache_init(&ws->bo_cache, RADEON_MAX_CACHED_HEAPS,
 309                  500000, ws->check_vm ? 1.0f : 2.0f, 0,
 310                  (ws->info.vram_size + ws->info.gart_size) / 8,
 311                  amdgpu_bo_destroy, amdgpu_bo_can_reclaim);
 312
 313    unsigned min_slab_order = 9;  /* 512 bytes */
 314    unsigned max_slab_order = 18; /* 256 KB - higher numbers increase memory usage */
 315    unsigned num_slab_orders_per_allocator = (max_slab_order - min_slab_order) /
 316                                             NUM_SLAB_ALLOCATORS;
 317
 318    /* Divide the size order range among slab managers. */
 319    for (unsigned i = 0; i < NUM_SLAB_ALLOCATORS; i++) {
 320       unsigned min_order = min_slab_order;
 321       unsigned max_order = MIN2(min_order + num_slab_orders_per_allocator,
 322                                 max_slab_order);
 323
 324       if (!pb_slabs_init(&ws->bo_slabs[i],
 325                          min_order, max_order,
 326                          RADEON_MAX_SLAB_HEAPS,
 327                          ws,
 328                          amdgpu_bo_can_reclaim_slab,
 329                          amdgpu_bo_slab_alloc,
 330                          amdgpu_bo_slab_free)) {
 331          amdgpu_winsys_destroy(&ws->base);
 332          simple_mtx_unlock(&dev_tab_mutex);
 333          return NULL;
 334       }
 335
 336       min_slab_order = max_order + 1;
 337    }
 338
 339    ws->info.min_alloc_size = 1 << ws->bo_slabs[0].min_order;
 340
 341    /* init reference */
 342    pipe_reference_init(&ws->reference, 1);
 343
 344    /* Set functions. */
 345    ws->base.unref = amdgpu_winsys_unref;
 346    ws->base.destroy = amdgpu_winsys_destroy;
 347    ws->base.query_info = amdgpu_winsys_query_info;
 348    ws->base.cs_request_feature = amdgpu_cs_request_feature;
 349    ws->base.query_value = amdgpu_query_value;
 350    ws->base.read_registers = amdgpu_read_registers;
 351    ws->base.get_chip_name = amdgpu_get_chip_name;
 352    ws->base.pin_threads_to_L3_cache = amdgpu_pin_threads_to_L3_cache;
 353
 354    amdgpu_bo_init_functions(ws);
 355    amdgpu_cs_init_functions(ws);
 356    amdgpu_surface_init_functions(ws);
 357
 358    LIST_INITHEAD(&ws->global_bo_list);
 359    ws->bo_export_table = util_hash_table_create(hash_pointer, compare_pointers);
 360
 361    (void) simple_mtx_init(&ws->global_bo_list_lock, mtx_plain);
 362    (void) simple_mtx_init(&ws->bo_fence_lock, mtx_plain);
 363    (void) simple_mtx_init(&ws->bo_export_table_lock, mtx_plain);
 364
 365    if (!util_queue_init(&ws->cs_queue, "cs", 8, 1,
 366                         UTIL_QUEUE_INIT_RESIZE_IF_FULL)) {
 367       amdgpu_winsys_destroy(&ws->base);
 368       simple_mtx_unlock(&dev_tab_mutex);
 369       return NULL;
 370    }
 371
 372    /* Create the screen at the end. The winsys must be initialized
 373     * completely.
 374     *
 375     * Alternatively, we could create the screen based on "ws->gen"
 376     * and link all drivers into one binary blob. */
 377    ws->base.screen = screen_create(&ws->base, config);
 378    if (!ws->base.screen) {
 379       amdgpu_winsys_destroy(&ws->base);
 380       simple_mtx_unlock(&dev_tab_mutex);
 381       return NULL;
 382    }
 383
 384    util_hash_table_set(dev_tab, dev, ws);
 385
 386    if (ws->reserve_vmid) {
 387            r = amdgpu_vm_reserve_vmid(dev, 0);
 388            if (r) {
 389                 fprintf(stderr, "amdgpu: amdgpu_vm_reserve_vmid failed. (%i)\n", r);
 390                 goto fail_cache;
 391            }
 392    }
 393
 394    /* We must unlock the mutex once the winsys is fully initialized, so that
 395     * other threads attempting to create the winsys from the same fd will
 396     * get a fully initialized winsys and not just half-way initialized. */
 397    simple_mtx_unlock(&dev_tab_mutex);
 398
 399    return &ws->base;
 400
 401 fail_cache:
 402    pb_cache_deinit(&ws->bo_cache);
 403    do_winsys_deinit(ws);
 404 fail_alloc:
 405    FREE(ws);
 406 fail:
 407    simple_mtx_unlock(&dev_tab_mutex);
 408    return NULL;
 409 }