2 * Copyright © 2009 Corbin Simpson <MostAwesomeDude@gmail.com>
3 * Copyright © 2009 Joakim Sindholt <opensource@zhasha.com>
4 * Copyright © 2011 Marek Olšák <maraeo@gmail.com>
5 * Copyright © 2015 Advanced Micro Devices, Inc.
8 * Permission is hereby granted, free of charge, to any person obtaining
9 * a copy of this software and associated documentation files (the
10 * "Software"), to deal in the Software without restriction, including
11 * without limitation the rights to use, copy, modify, merge, publish,
12 * distribute, sub license, and/or sell copies of the Software, and to
13 * permit persons to whom the Software is furnished to do so, subject to
14 * the following conditions:
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
17 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
18 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
19 * NON-INFRINGEMENT. IN NO EVENT SHALL THE COPYRIGHT HOLDERS, AUTHORS
20 * AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
21 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
22 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
23 * USE OR OTHER DEALINGS IN THE SOFTWARE.
25 * The above copyright notice and this permission notice (including the
26 * next paragraph) shall be included in all copies or substantial portions
30 #include "amdgpu_cs.h"
31 #include "amdgpu_public.h"
33 #include "util/u_cpu_detect.h"
34 #include "util/u_hash_table.h"
35 #include "util/hash_table.h"
36 #include "util/xmlconfig.h"
37 #include <amdgpu_drm.h>
41 #include "amd/common/ac_llvm_util.h"
42 #include "amd/common/sid.h"
43 #include "amd/common/gfx9d.h"
45 #ifndef AMDGPU_INFO_NUM_VRAM_CPU_PAGE_FAULTS
46 #define AMDGPU_INFO_NUM_VRAM_CPU_PAGE_FAULTS 0x1E
49 static struct util_hash_table
*dev_tab
= NULL
;
50 static simple_mtx_t dev_tab_mutex
= _SIMPLE_MTX_INITIALIZER_NP
;
52 DEBUG_GET_ONCE_BOOL_OPTION(all_bos
, "RADEON_ALL_BOS", false)
54 static void handle_env_var_force_family(struct amdgpu_winsys
*ws
)
56 const char *family
= debug_get_option("SI_FORCE_FAMILY", NULL
);
62 for (i
= CHIP_TAHITI
; i
< CHIP_LAST
; i
++) {
63 if (!strcmp(family
, ac_get_llvm_processor_name(i
))) {
64 /* Override family and chip_class. */
66 ws
->info
.name
= "GCN-NOOP";
69 ws
->info
.chip_class
= GFX9
;
70 else if (i
>= CHIP_TONGA
)
71 ws
->info
.chip_class
= VI
;
72 else if (i
>= CHIP_BONAIRE
)
73 ws
->info
.chip_class
= CIK
;
75 ws
->info
.chip_class
= SI
;
77 /* Don't submit any IBs. */
78 setenv("RADEON_NOOP", "1", 1);
83 fprintf(stderr
, "radeonsi: Unknown family: %s\n", family
);
87 /* Helper function to do the ioctls needed for setup and init. */
88 static bool do_winsys_init(struct amdgpu_winsys
*ws
,
89 const struct pipe_screen_config
*config
,
92 if (!ac_query_gpu_info(fd
, ws
->dev
, &ws
->info
, &ws
->amdinfo
))
95 handle_env_var_force_family(ws
);
97 ws
->addrlib
= amdgpu_addr_create(&ws
->info
, &ws
->amdinfo
, &ws
->info
.max_alignment
);
99 fprintf(stderr
, "amdgpu: Cannot create addrlib.\n");
103 ws
->check_vm
= strstr(debug_get_option("R600_DEBUG", ""), "check_vm") != NULL
;
104 ws
->debug_all_bos
= debug_get_option_all_bos();
105 ws
->reserve_vmid
= strstr(debug_get_option("R600_DEBUG", ""), "reserve_vmid") != NULL
;
106 ws
->zero_all_vram_allocs
= strstr(debug_get_option("R600_DEBUG", ""), "zerovram") != NULL
||
107 driQueryOptionb(config
->options
, "radeonsi_zerovram");
112 amdgpu_device_deinitialize(ws
->dev
);
117 static void do_winsys_deinit(struct amdgpu_winsys
*ws
)
119 AddrDestroy(ws
->addrlib
);
120 amdgpu_device_deinitialize(ws
->dev
);
123 static void amdgpu_winsys_destroy(struct radeon_winsys
*rws
)
125 struct amdgpu_winsys
*ws
= (struct amdgpu_winsys
*)rws
;
127 if (ws
->reserve_vmid
)
128 amdgpu_vm_unreserve_vmid(ws
->dev
, 0);
130 if (util_queue_is_initialized(&ws
->cs_queue
))
131 util_queue_destroy(&ws
->cs_queue
);
133 simple_mtx_destroy(&ws
->bo_fence_lock
);
134 for (unsigned i
= 0; i
< NUM_SLAB_ALLOCATORS
; i
++) {
135 if (ws
->bo_slabs
[i
].groups
)
136 pb_slabs_deinit(&ws
->bo_slabs
[i
]);
138 pb_cache_deinit(&ws
->bo_cache
);
139 util_hash_table_destroy(ws
->bo_export_table
);
140 simple_mtx_destroy(&ws
->global_bo_list_lock
);
141 simple_mtx_destroy(&ws
->bo_export_table_lock
);
142 do_winsys_deinit(ws
);
146 static void amdgpu_winsys_query_info(struct radeon_winsys
*rws
,
147 struct radeon_info
*info
)
149 *info
= ((struct amdgpu_winsys
*)rws
)->info
;
152 static bool amdgpu_cs_request_feature(struct radeon_cmdbuf
*rcs
,
153 enum radeon_feature_id fid
,
159 static uint64_t amdgpu_query_value(struct radeon_winsys
*rws
,
160 enum radeon_value_id value
)
162 struct amdgpu_winsys
*ws
= (struct amdgpu_winsys
*)rws
;
163 struct amdgpu_heap_info heap
;
167 case RADEON_REQUESTED_VRAM_MEMORY
:
168 return ws
->allocated_vram
;
169 case RADEON_REQUESTED_GTT_MEMORY
:
170 return ws
->allocated_gtt
;
171 case RADEON_MAPPED_VRAM
:
172 return ws
->mapped_vram
;
173 case RADEON_MAPPED_GTT
:
174 return ws
->mapped_gtt
;
175 case RADEON_BUFFER_WAIT_TIME_NS
:
176 return ws
->buffer_wait_time
;
177 case RADEON_NUM_MAPPED_BUFFERS
:
178 return ws
->num_mapped_buffers
;
179 case RADEON_TIMESTAMP
:
180 amdgpu_query_info(ws
->dev
, AMDGPU_INFO_TIMESTAMP
, 8, &retval
);
182 case RADEON_NUM_GFX_IBS
:
183 return ws
->num_gfx_IBs
;
184 case RADEON_NUM_SDMA_IBS
:
185 return ws
->num_sdma_IBs
;
186 case RADEON_GFX_BO_LIST_COUNTER
:
187 return ws
->gfx_bo_list_counter
;
188 case RADEON_GFX_IB_SIZE_COUNTER
:
189 return ws
->gfx_ib_size_counter
;
190 case RADEON_NUM_BYTES_MOVED
:
191 amdgpu_query_info(ws
->dev
, AMDGPU_INFO_NUM_BYTES_MOVED
, 8, &retval
);
193 case RADEON_NUM_EVICTIONS
:
194 amdgpu_query_info(ws
->dev
, AMDGPU_INFO_NUM_EVICTIONS
, 8, &retval
);
196 case RADEON_NUM_VRAM_CPU_PAGE_FAULTS
:
197 amdgpu_query_info(ws
->dev
, AMDGPU_INFO_NUM_VRAM_CPU_PAGE_FAULTS
, 8, &retval
);
199 case RADEON_VRAM_USAGE
:
200 amdgpu_query_heap_info(ws
->dev
, AMDGPU_GEM_DOMAIN_VRAM
, 0, &heap
);
201 return heap
.heap_usage
;
202 case RADEON_VRAM_VIS_USAGE
:
203 amdgpu_query_heap_info(ws
->dev
, AMDGPU_GEM_DOMAIN_VRAM
,
204 AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED
, &heap
);
205 return heap
.heap_usage
;
206 case RADEON_GTT_USAGE
:
207 amdgpu_query_heap_info(ws
->dev
, AMDGPU_GEM_DOMAIN_GTT
, 0, &heap
);
208 return heap
.heap_usage
;
209 case RADEON_GPU_TEMPERATURE
:
210 amdgpu_query_sensor_info(ws
->dev
, AMDGPU_INFO_SENSOR_GPU_TEMP
, 4, &retval
);
212 case RADEON_CURRENT_SCLK
:
213 amdgpu_query_sensor_info(ws
->dev
, AMDGPU_INFO_SENSOR_GFX_SCLK
, 4, &retval
);
215 case RADEON_CURRENT_MCLK
:
216 amdgpu_query_sensor_info(ws
->dev
, AMDGPU_INFO_SENSOR_GFX_MCLK
, 4, &retval
);
218 case RADEON_GPU_RESET_COUNTER
:
221 case RADEON_CS_THREAD_TIME
:
222 return util_queue_get_thread_time_nano(&ws
->cs_queue
, 0);
227 static bool amdgpu_read_registers(struct radeon_winsys
*rws
,
229 unsigned num_registers
, uint32_t *out
)
231 struct amdgpu_winsys
*ws
= (struct amdgpu_winsys
*)rws
;
233 return amdgpu_read_mm_registers(ws
->dev
, reg_offset
/ 4, num_registers
,
234 0xffffffff, 0, out
) == 0;
237 static unsigned hash_pointer(void *key
)
239 return _mesa_hash_pointer(key
);
242 static int compare_pointers(void *key1
, void *key2
)
247 static bool amdgpu_winsys_unref(struct radeon_winsys
*rws
)
249 struct amdgpu_winsys
*ws
= (struct amdgpu_winsys
*)rws
;
252 /* When the reference counter drops to zero, remove the device pointer
254 * This must happen while the mutex is locked, so that
255 * amdgpu_winsys_create in another thread doesn't get the winsys
256 * from the table when the counter drops to 0. */
257 simple_mtx_lock(&dev_tab_mutex
);
259 destroy
= pipe_reference(&ws
->reference
, NULL
);
260 if (destroy
&& dev_tab
) {
261 util_hash_table_remove(dev_tab
, ws
->dev
);
262 if (util_hash_table_count(dev_tab
) == 0) {
263 util_hash_table_destroy(dev_tab
);
268 simple_mtx_unlock(&dev_tab_mutex
);
272 static const char* amdgpu_get_chip_name(struct radeon_winsys
*ws
)
274 amdgpu_device_handle dev
= ((struct amdgpu_winsys
*)ws
)->dev
;
275 return amdgpu_get_marketing_name(dev
);
278 static void amdgpu_pin_threads_to_L3_cache(struct radeon_winsys
*rws
,
281 struct amdgpu_winsys
*ws
= (struct amdgpu_winsys
*)rws
;
283 util_pin_thread_to_L3(ws
->cs_queue
.threads
[0], cache
,
284 util_cpu_caps
.cores_per_L3
);
287 PUBLIC
struct radeon_winsys
*
288 amdgpu_winsys_create(int fd
, const struct pipe_screen_config
*config
,
289 radeon_screen_create_t screen_create
)
291 struct amdgpu_winsys
*ws
;
292 drmVersionPtr version
= drmGetVersion(fd
);
293 amdgpu_device_handle dev
;
294 uint32_t drm_major
, drm_minor
, r
;
296 /* The DRM driver version of amdgpu is 3.x.x. */
297 if (version
->version_major
!= 3) {
298 drmFreeVersion(version
);
301 drmFreeVersion(version
);
303 /* Look up the winsys from the dev table. */
304 simple_mtx_lock(&dev_tab_mutex
);
306 dev_tab
= util_hash_table_create(hash_pointer
, compare_pointers
);
308 /* Initialize the amdgpu device. This should always return the same pointer
309 * for the same fd. */
310 r
= amdgpu_device_initialize(fd
, &drm_major
, &drm_minor
, &dev
);
312 simple_mtx_unlock(&dev_tab_mutex
);
313 fprintf(stderr
, "amdgpu: amdgpu_device_initialize failed.\n");
317 /* Lookup a winsys if we have already created one for this device. */
318 ws
= util_hash_table_get(dev_tab
, dev
);
320 pipe_reference(NULL
, &ws
->reference
);
321 simple_mtx_unlock(&dev_tab_mutex
);
323 /* Release the device handle, because we don't need it anymore.
324 * This function is returning an existing winsys instance, which
325 * has its own device handle.
327 amdgpu_device_deinitialize(dev
);
331 /* Create a new winsys. */
332 ws
= CALLOC_STRUCT(amdgpu_winsys
);
337 ws
->info
.drm_major
= drm_major
;
338 ws
->info
.drm_minor
= drm_minor
;
340 if (!do_winsys_init(ws
, config
, fd
))
343 /* Create managers. */
344 pb_cache_init(&ws
->bo_cache
, RADEON_MAX_CACHED_HEAPS
,
345 500000, ws
->check_vm
? 1.0f
: 2.0f
, 0,
346 (ws
->info
.vram_size
+ ws
->info
.gart_size
) / 8,
347 amdgpu_bo_destroy
, amdgpu_bo_can_reclaim
);
349 unsigned min_slab_order
= 9; /* 512 bytes */
350 unsigned max_slab_order
= 18; /* 256 KB - higher numbers increase memory usage */
351 unsigned num_slab_orders_per_allocator
= (max_slab_order
- min_slab_order
) /
354 /* Divide the size order range among slab managers. */
355 for (unsigned i
= 0; i
< NUM_SLAB_ALLOCATORS
; i
++) {
356 unsigned min_order
= min_slab_order
;
357 unsigned max_order
= MIN2(min_order
+ num_slab_orders_per_allocator
,
360 if (!pb_slabs_init(&ws
->bo_slabs
[i
],
361 min_order
, max_order
,
362 RADEON_MAX_SLAB_HEAPS
,
364 amdgpu_bo_can_reclaim_slab
,
365 amdgpu_bo_slab_alloc
,
366 amdgpu_bo_slab_free
)) {
367 amdgpu_winsys_destroy(&ws
->base
);
368 simple_mtx_unlock(&dev_tab_mutex
);
372 min_slab_order
= max_order
+ 1;
375 ws
->info
.min_alloc_size
= 1 << ws
->bo_slabs
[0].min_order
;
378 pipe_reference_init(&ws
->reference
, 1);
381 ws
->base
.unref
= amdgpu_winsys_unref
;
382 ws
->base
.destroy
= amdgpu_winsys_destroy
;
383 ws
->base
.query_info
= amdgpu_winsys_query_info
;
384 ws
->base
.cs_request_feature
= amdgpu_cs_request_feature
;
385 ws
->base
.query_value
= amdgpu_query_value
;
386 ws
->base
.read_registers
= amdgpu_read_registers
;
387 ws
->base
.get_chip_name
= amdgpu_get_chip_name
;
388 ws
->base
.pin_threads_to_L3_cache
= amdgpu_pin_threads_to_L3_cache
;
390 amdgpu_bo_init_functions(ws
);
391 amdgpu_cs_init_functions(ws
);
392 amdgpu_surface_init_functions(ws
);
394 LIST_INITHEAD(&ws
->global_bo_list
);
395 ws
->bo_export_table
= util_hash_table_create(hash_pointer
, compare_pointers
);
397 (void) simple_mtx_init(&ws
->global_bo_list_lock
, mtx_plain
);
398 (void) simple_mtx_init(&ws
->bo_fence_lock
, mtx_plain
);
399 (void) simple_mtx_init(&ws
->bo_export_table_lock
, mtx_plain
);
401 if (!util_queue_init(&ws
->cs_queue
, "cs", 8, 1,
402 UTIL_QUEUE_INIT_RESIZE_IF_FULL
)) {
403 amdgpu_winsys_destroy(&ws
->base
);
404 simple_mtx_unlock(&dev_tab_mutex
);
408 /* Create the screen at the end. The winsys must be initialized
411 * Alternatively, we could create the screen based on "ws->gen"
412 * and link all drivers into one binary blob. */
413 ws
->base
.screen
= screen_create(&ws
->base
, config
);
414 if (!ws
->base
.screen
) {
415 amdgpu_winsys_destroy(&ws
->base
);
416 simple_mtx_unlock(&dev_tab_mutex
);
420 util_hash_table_set(dev_tab
, dev
, ws
);
422 if (ws
->reserve_vmid
) {
423 r
= amdgpu_vm_reserve_vmid(dev
, 0);
425 fprintf(stderr
, "amdgpu: amdgpu_vm_reserve_vmid failed. (%i)\n", r
);
430 /* We must unlock the mutex once the winsys is fully initialized, so that
431 * other threads attempting to create the winsys from the same fd will
432 * get a fully initialized winsys and not just half-way initialized. */
433 simple_mtx_unlock(&dev_tab_mutex
);
438 pb_cache_deinit(&ws
->bo_cache
);
439 do_winsys_deinit(ws
);
443 simple_mtx_unlock(&dev_tab_mutex
);