src/gallium/winsys/amdgpu/drm/amdgpu_winsys.c

   1 /*
   2  * Copyright © 2009 Corbin Simpson <MostAwesomeDude@gmail.com>
   3  * Copyright © 2009 Joakim Sindholt <opensource@zhasha.com>
   4  * Copyright © 2011 Marek Olšák <maraeo@gmail.com>
   5  * Copyright © 2015 Advanced Micro Devices, Inc.
   6  * All Rights Reserved.
   7  *
   8  * Permission is hereby granted, free of charge, to any person obtaining
   9  * a copy of this software and associated documentation files (the
  10  * "Software"), to deal in the Software without restriction, including
  11  * without limitation the rights to use, copy, modify, merge, publish,
  12  * distribute, sub license, and/or sell copies of the Software, and to
  13  * permit persons to whom the Software is furnished to do so, subject to
  14  * the following conditions:
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  17  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
  18  * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  19  * NON-INFRINGEMENT. IN NO EVENT SHALL THE COPYRIGHT HOLDERS, AUTHORS
  20  * AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  21  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  22  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
  23  * USE OR OTHER DEALINGS IN THE SOFTWARE.
  24  *
  25  * The above copyright notice and this permission notice (including the
  26  * next paragraph) shall be included in all copies or substantial portions
  27  * of the Software.
  28  */
  29 /*
  30  * Authors:
  31  *      Marek Olšák <maraeo@gmail.com>
  32  */
  33
  34 #include "amdgpu_cs.h"
  35 #include "amdgpu_public.h"
  36
  37 #include "util/u_hash_table.h"
  38 #include <amdgpu_drm.h>
  39 #include <xf86drm.h>
  40 #include <stdio.h>
  41 #include <sys/stat.h>
  42 #include "amdgpu_id.h"
  43
  44 #define CIK_TILE_MODE_COLOR_2D                  14
  45
  46 #define CIK__GB_TILE_MODE__PIPE_CONFIG(x)        (((x) >> 6) & 0x1f)
  47 #define     CIK__PIPE_CONFIG__ADDR_SURF_P2               0
  48 #define     CIK__PIPE_CONFIG__ADDR_SURF_P4_8x16          4
  49 #define     CIK__PIPE_CONFIG__ADDR_SURF_P4_16x16         5
  50 #define     CIK__PIPE_CONFIG__ADDR_SURF_P4_16x32         6
  51 #define     CIK__PIPE_CONFIG__ADDR_SURF_P4_32x32         7
  52 #define     CIK__PIPE_CONFIG__ADDR_SURF_P8_16x16_8x16    8
  53 #define     CIK__PIPE_CONFIG__ADDR_SURF_P8_16x32_8x16    9
  54 #define     CIK__PIPE_CONFIG__ADDR_SURF_P8_32x32_8x16    10
  55 #define     CIK__PIPE_CONFIG__ADDR_SURF_P8_16x32_16x16   11
  56 #define     CIK__PIPE_CONFIG__ADDR_SURF_P8_32x32_16x16   12
  57 #define     CIK__PIPE_CONFIG__ADDR_SURF_P8_32x32_16x32   13
  58 #define     CIK__PIPE_CONFIG__ADDR_SURF_P8_32x64_32x32   14
  59 #define     CIK__PIPE_CONFIG__ADDR_SURF_P16_32X32_8X16   16
  60 #define     CIK__PIPE_CONFIG__ADDR_SURF_P16_32X32_16X16  17
  61
  62 static struct util_hash_table *dev_tab = NULL;
  63 pipe_static_mutex(dev_tab_mutex);
  64
  65 static unsigned cik_get_num_tile_pipes(struct amdgpu_gpu_info *info)
  66 {
  67    unsigned mode2d = info->gb_tile_mode[CIK_TILE_MODE_COLOR_2D];
  68
  69    switch (CIK__GB_TILE_MODE__PIPE_CONFIG(mode2d)) {
  70    case CIK__PIPE_CONFIG__ADDR_SURF_P2:
  71        return 2;
  72    case CIK__PIPE_CONFIG__ADDR_SURF_P4_8x16:
  73    case CIK__PIPE_CONFIG__ADDR_SURF_P4_16x16:
  74    case CIK__PIPE_CONFIG__ADDR_SURF_P4_16x32:
  75    case CIK__PIPE_CONFIG__ADDR_SURF_P4_32x32:
  76        return 4;
  77    case CIK__PIPE_CONFIG__ADDR_SURF_P8_16x16_8x16:
  78    case CIK__PIPE_CONFIG__ADDR_SURF_P8_16x32_8x16:
  79    case CIK__PIPE_CONFIG__ADDR_SURF_P8_32x32_8x16:
  80    case CIK__PIPE_CONFIG__ADDR_SURF_P8_16x32_16x16:
  81    case CIK__PIPE_CONFIG__ADDR_SURF_P8_32x32_16x16:
  82    case CIK__PIPE_CONFIG__ADDR_SURF_P8_32x32_16x32:
  83    case CIK__PIPE_CONFIG__ADDR_SURF_P8_32x64_32x32:
  84        return 8;
  85    case CIK__PIPE_CONFIG__ADDR_SURF_P16_32X32_8X16:
  86    case CIK__PIPE_CONFIG__ADDR_SURF_P16_32X32_16X16:
  87        return 16;
  88    default:
  89        fprintf(stderr, "Invalid CIK pipe configuration, assuming P2\n");
  90        assert(!"this should never occur");
  91        return 2;
  92    }
  93 }
  94
  95 /* Helper function to do the ioctls needed for setup and init. */
  96 static boolean do_winsys_init(struct amdgpu_winsys *ws, int fd)
  97 {
  98    struct amdgpu_buffer_size_alignments alignment_info = {};
  99    struct amdgpu_heap_info vram, gtt;
 100    struct drm_amdgpu_info_hw_ip dma = {}, uvd = {}, vce = {};
 101    uint32_t vce_version = 0, vce_feature = 0;
 102    int r, i, j;
 103    drmDevicePtr devinfo;
 104
 105    /* Get PCI info. */
 106    r = drmGetDevice(fd, &devinfo);
 107    if (r) {
 108       fprintf(stderr, "amdgpu: drmGetDevice failed.\n");
 109       goto fail;
 110    }
 111    ws->info.pci_domain = devinfo->businfo.pci->domain;
 112    ws->info.pci_bus = devinfo->businfo.pci->bus;
 113    ws->info.pci_dev = devinfo->businfo.pci->dev;
 114    ws->info.pci_func = devinfo->businfo.pci->func;
 115    drmFreeDevice(&devinfo);
 116
 117    /* Query hardware and driver information. */
 118    r = amdgpu_query_gpu_info(ws->dev, &ws->amdinfo);
 119    if (r) {
 120       fprintf(stderr, "amdgpu: amdgpu_query_gpu_info failed.\n");
 121       goto fail;
 122    }
 123
 124    r = amdgpu_query_buffer_size_alignment(ws->dev, &alignment_info);
 125    if (r) {
 126       fprintf(stderr, "amdgpu: amdgpu_query_buffer_size_alignment failed.\n");
 127       goto fail;
 128    }
 129
 130    r = amdgpu_query_heap_info(ws->dev, AMDGPU_GEM_DOMAIN_VRAM, 0, &vram);
 131    if (r) {
 132       fprintf(stderr, "amdgpu: amdgpu_query_heap_info(vram) failed.\n");
 133       goto fail;
 134    }
 135
 136    r = amdgpu_query_heap_info(ws->dev, AMDGPU_GEM_DOMAIN_GTT, 0, &gtt);
 137    if (r) {
 138       fprintf(stderr, "amdgpu: amdgpu_query_heap_info(gtt) failed.\n");
 139       goto fail;
 140    }
 141
 142    r = amdgpu_query_hw_ip_info(ws->dev, AMDGPU_HW_IP_DMA, 0, &dma);
 143    if (r) {
 144       fprintf(stderr, "amdgpu: amdgpu_query_hw_ip_info(dma) failed.\n");
 145       goto fail;
 146    }
 147
 148    r = amdgpu_query_hw_ip_info(ws->dev, AMDGPU_HW_IP_UVD, 0, &uvd);
 149    if (r) {
 150       fprintf(stderr, "amdgpu: amdgpu_query_hw_ip_info(uvd) failed.\n");
 151       goto fail;
 152    }
 153
 154    r = amdgpu_query_hw_ip_info(ws->dev, AMDGPU_HW_IP_VCE, 0, &vce);
 155    if (r) {
 156       fprintf(stderr, "amdgpu: amdgpu_query_hw_ip_info(vce) failed.\n");
 157       goto fail;
 158    }
 159
 160    r = amdgpu_query_firmware_version(ws->dev, AMDGPU_INFO_FW_VCE, 0, 0,
 161                                      &vce_version, &vce_feature);
 162    if (r) {
 163       fprintf(stderr, "amdgpu: amdgpu_query_firmware_version(vce) failed.\n");
 164       goto fail;
 165    }
 166
 167    /* Set chip identification. */
 168    ws->info.pci_id = ws->amdinfo.asic_id; /* TODO: is this correct? */
 169    ws->info.vce_harvest_config = ws->amdinfo.vce_harvest_config;
 170
 171    switch (ws->info.pci_id) {
 172 #define CHIPSET(pci_id, name, cfamily) case pci_id: ws->info.family = CHIP_##cfamily; break;
 173 #include "pci_ids/radeonsi_pci_ids.h"
 174 #undef CHIPSET
 175
 176    default:
 177       fprintf(stderr, "amdgpu: Invalid PCI ID.\n");
 178       goto fail;
 179    }
 180
 181    if (ws->info.family >= CHIP_TONGA)
 182       ws->info.chip_class = VI;
 183    else if (ws->info.family >= CHIP_BONAIRE)
 184       ws->info.chip_class = CIK;
 185    else {
 186       fprintf(stderr, "amdgpu: Unknown family.\n");
 187       goto fail;
 188    }
 189
 190    /* LLVM 3.6.1 is required for VI. */
 191    if (ws->info.chip_class >= VI &&
 192        HAVE_LLVM == 0x0306 && MESA_LLVM_VERSION_PATCH < 1) {
 193       fprintf(stderr, "amdgpu: LLVM 3.6.1 is required, got LLVM %i.%i.%i\n",
 194               HAVE_LLVM >> 8, HAVE_LLVM & 255, MESA_LLVM_VERSION_PATCH);
 195       goto fail;
 196    }
 197
 198    /* family and rev_id are for addrlib */
 199    switch (ws->info.family) {
 200    case CHIP_BONAIRE:
 201       ws->family = FAMILY_CI;
 202       ws->rev_id = CI_BONAIRE_M_A0;
 203       break;
 204    case CHIP_KAVERI:
 205       ws->family = FAMILY_KV;
 206       ws->rev_id = KV_SPECTRE_A0;
 207       break;
 208    case CHIP_KABINI:
 209       ws->family = FAMILY_KV;
 210       ws->rev_id = KB_KALINDI_A0;
 211       break;
 212    case CHIP_HAWAII:
 213       ws->family = FAMILY_CI;
 214       ws->rev_id = CI_HAWAII_P_A0;
 215       break;
 216    case CHIP_MULLINS:
 217       ws->family = FAMILY_KV;
 218       ws->rev_id = ML_GODAVARI_A0;
 219       break;
 220    case CHIP_TONGA:
 221       ws->family = FAMILY_VI;
 222       ws->rev_id = VI_TONGA_P_A0;
 223       break;
 224    case CHIP_ICELAND:
 225       ws->family = FAMILY_VI;
 226       ws->rev_id = VI_ICELAND_M_A0;
 227       break;
 228    case CHIP_CARRIZO:
 229       ws->family = FAMILY_CZ;
 230       ws->rev_id = CARRIZO_A0;
 231       break;
 232    case CHIP_STONEY:
 233       ws->family = FAMILY_CZ;
 234       ws->rev_id = STONEY_A0;
 235       break;
 236    case CHIP_FIJI:
 237       ws->family = FAMILY_VI;
 238       ws->rev_id = VI_FIJI_P_A0;
 239       break;
 240    case CHIP_POLARIS10:
 241       ws->family = FAMILY_VI;
 242       ws->rev_id = VI_POLARIS10_P_A0;
 243       break;
 244    case CHIP_POLARIS11:
 245       ws->family = FAMILY_VI;
 246       ws->rev_id = VI_POLARIS11_M_A0;
 247       break;
 248    default:
 249       fprintf(stderr, "amdgpu: Unknown family.\n");
 250       goto fail;
 251    }
 252
 253    ws->addrlib = amdgpu_addr_create(ws);
 254    if (!ws->addrlib) {
 255       fprintf(stderr, "amdgpu: Cannot create addrlib.\n");
 256       goto fail;
 257    }
 258
 259    /* Set which chips have dedicated VRAM. */
 260    ws->info.has_dedicated_vram =
 261       !(ws->amdinfo.ids_flags & AMDGPU_IDS_FLAGS_FUSION);
 262
 263    /* Set hardware information. */
 264    ws->info.gart_size = gtt.heap_size;
 265    ws->info.vram_size = vram.heap_size;
 266    /* convert the shader clock from KHz to MHz */
 267    ws->info.max_shader_clock = ws->amdinfo.max_engine_clk / 1000;
 268    ws->info.max_se = ws->amdinfo.num_shader_engines;
 269    ws->info.max_sh_per_se = ws->amdinfo.num_shader_arrays_per_engine;
 270    ws->info.has_uvd = uvd.available_rings != 0;
 271    ws->info.vce_fw_version =
 272          vce.available_rings ? vce_version : 0;
 273    ws->info.has_userptr = TRUE;
 274    ws->info.num_render_backends = ws->amdinfo.rb_pipes;
 275    ws->info.clock_crystal_freq = ws->amdinfo.gpu_counter_freq;
 276    ws->info.num_tile_pipes = cik_get_num_tile_pipes(&ws->amdinfo);
 277    ws->info.pipe_interleave_bytes = 256 << ((ws->amdinfo.gb_addr_cfg >> 4) & 0x7);
 278    ws->info.has_virtual_memory = TRUE;
 279    ws->info.has_sdma = dma.available_rings != 0;
 280
 281    /* Get the number of good compute units. */
 282    ws->info.num_good_compute_units = 0;
 283    for (i = 0; i < ws->info.max_se; i++)
 284       for (j = 0; j < ws->info.max_sh_per_se; j++)
 285          ws->info.num_good_compute_units +=
 286             util_bitcount(ws->amdinfo.cu_bitmap[i][j]);
 287
 288    memcpy(ws->info.si_tile_mode_array, ws->amdinfo.gb_tile_mode,
 289           sizeof(ws->amdinfo.gb_tile_mode));
 290    ws->info.enabled_rb_mask = ws->amdinfo.enabled_rb_pipes_mask;
 291
 292    memcpy(ws->info.cik_macrotile_mode_array, ws->amdinfo.gb_macro_tile_mode,
 293           sizeof(ws->amdinfo.gb_macro_tile_mode));
 294
 295    ws->info.gart_page_size = alignment_info.size_remote;
 296
 297    return TRUE;
 298
 299 fail:
 300    if (ws->addrlib)
 301       AddrDestroy(ws->addrlib);
 302    amdgpu_device_deinitialize(ws->dev);
 303    ws->dev = NULL;
 304    return FALSE;
 305 }
 306
 307 static void amdgpu_winsys_destroy(struct radeon_winsys *rws)
 308 {
 309    struct amdgpu_winsys *ws = (struct amdgpu_winsys*)rws;
 310
 311    if (util_queue_is_initialized(&ws->cs_queue))
 312       util_queue_destroy(&ws->cs_queue);
 313
 314    pipe_mutex_destroy(ws->bo_fence_lock);
 315    pb_cache_deinit(&ws->bo_cache);
 316    pipe_mutex_destroy(ws->global_bo_list_lock);
 317    AddrDestroy(ws->addrlib);
 318    amdgpu_device_deinitialize(ws->dev);
 319    FREE(rws);
 320 }
 321
 322 static void amdgpu_winsys_query_info(struct radeon_winsys *rws,
 323                                      struct radeon_info *info)
 324 {
 325    *info = ((struct amdgpu_winsys *)rws)->info;
 326 }
 327
 328 static boolean amdgpu_cs_request_feature(struct radeon_winsys_cs *rcs,
 329                                          enum radeon_feature_id fid,
 330                                          boolean enable)
 331 {
 332    return FALSE;
 333 }
 334
 335 static uint64_t amdgpu_query_value(struct radeon_winsys *rws,
 336                                    enum radeon_value_id value)
 337 {
 338    struct amdgpu_winsys *ws = (struct amdgpu_winsys*)rws;
 339    struct amdgpu_heap_info heap;
 340    uint64_t retval = 0;
 341
 342    switch (value) {
 343    case RADEON_REQUESTED_VRAM_MEMORY:
 344       return ws->allocated_vram;
 345    case RADEON_REQUESTED_GTT_MEMORY:
 346       return ws->allocated_gtt;
 347    case RADEON_BUFFER_WAIT_TIME_NS:
 348       return ws->buffer_wait_time;
 349    case RADEON_TIMESTAMP:
 350       amdgpu_query_info(ws->dev, AMDGPU_INFO_TIMESTAMP, 8, &retval);
 351       return retval;
 352    case RADEON_NUM_CS_FLUSHES:
 353       return ws->num_cs_flushes;
 354    case RADEON_NUM_BYTES_MOVED:
 355       amdgpu_query_info(ws->dev, AMDGPU_INFO_NUM_BYTES_MOVED, 8, &retval);
 356       return retval;
 357    case RADEON_VRAM_USAGE:
 358       amdgpu_query_heap_info(ws->dev, AMDGPU_GEM_DOMAIN_VRAM, 0, &heap);
 359       return heap.heap_usage;
 360    case RADEON_GTT_USAGE:
 361       amdgpu_query_heap_info(ws->dev, AMDGPU_GEM_DOMAIN_GTT, 0, &heap);
 362       return heap.heap_usage;
 363    case RADEON_GPU_TEMPERATURE:
 364    case RADEON_CURRENT_SCLK:
 365    case RADEON_CURRENT_MCLK:
 366       return 0;
 367    case RADEON_GPU_RESET_COUNTER:
 368       assert(0);
 369       return 0;
 370    }
 371    return 0;
 372 }
 373
 374 static bool amdgpu_read_registers(struct radeon_winsys *rws,
 375                                   unsigned reg_offset,
 376                                   unsigned num_registers, uint32_t *out)
 377 {
 378    struct amdgpu_winsys *ws = (struct amdgpu_winsys*)rws;
 379
 380    return amdgpu_read_mm_registers(ws->dev, reg_offset / 4, num_registers,
 381                                    0xffffffff, 0, out) == 0;
 382 }
 383
 384 static unsigned hash_dev(void *key)
 385 {
 386 #if defined(PIPE_ARCH_X86_64)
 387    return pointer_to_intptr(key) ^ (pointer_to_intptr(key) >> 32);
 388 #else
 389    return pointer_to_intptr(key);
 390 #endif
 391 }
 392
 393 static int compare_dev(void *key1, void *key2)
 394 {
 395    return key1 != key2;
 396 }
 397
 398 DEBUG_GET_ONCE_BOOL_OPTION(thread, "RADEON_THREAD", TRUE)
 399
 400 static bool amdgpu_winsys_unref(struct radeon_winsys *rws)
 401 {
 402    struct amdgpu_winsys *ws = (struct amdgpu_winsys*)rws;
 403    bool destroy;
 404
 405    /* When the reference counter drops to zero, remove the device pointer
 406     * from the table.
 407     * This must happen while the mutex is locked, so that
 408     * amdgpu_winsys_create in another thread doesn't get the winsys
 409     * from the table when the counter drops to 0. */
 410    pipe_mutex_lock(dev_tab_mutex);
 411
 412    destroy = pipe_reference(&ws->reference, NULL);
 413    if (destroy && dev_tab)
 414       util_hash_table_remove(dev_tab, ws->dev);
 415
 416    pipe_mutex_unlock(dev_tab_mutex);
 417    return destroy;
 418 }
 419
 420 PUBLIC struct radeon_winsys *
 421 amdgpu_winsys_create(int fd, radeon_screen_create_t screen_create)
 422 {
 423    struct amdgpu_winsys *ws;
 424    drmVersionPtr version = drmGetVersion(fd);
 425    amdgpu_device_handle dev;
 426    uint32_t drm_major, drm_minor, r;
 427
 428    /* The DRM driver version of amdgpu is 3.x.x. */
 429    if (version->version_major != 3) {
 430       drmFreeVersion(version);
 431       return NULL;
 432    }
 433    drmFreeVersion(version);
 434
 435    /* Look up the winsys from the dev table. */
 436    pipe_mutex_lock(dev_tab_mutex);
 437    if (!dev_tab)
 438       dev_tab = util_hash_table_create(hash_dev, compare_dev);
 439
 440    /* Initialize the amdgpu device. This should always return the same pointer
 441     * for the same fd. */
 442    r = amdgpu_device_initialize(fd, &drm_major, &drm_minor, &dev);
 443    if (r) {
 444       pipe_mutex_unlock(dev_tab_mutex);
 445       fprintf(stderr, "amdgpu: amdgpu_device_initialize failed.\n");
 446       return NULL;
 447    }
 448
 449    /* Lookup a winsys if we have already created one for this device. */
 450    ws = util_hash_table_get(dev_tab, dev);
 451    if (ws) {
 452       pipe_reference(NULL, &ws->reference);
 453       pipe_mutex_unlock(dev_tab_mutex);
 454       return &ws->base;
 455    }
 456
 457    /* Create a new winsys. */
 458    ws = CALLOC_STRUCT(amdgpu_winsys);
 459    if (!ws) {
 460       pipe_mutex_unlock(dev_tab_mutex);
 461       return NULL;
 462    }
 463
 464    ws->dev = dev;
 465    ws->info.drm_major = drm_major;
 466    ws->info.drm_minor = drm_minor;
 467
 468    if (!do_winsys_init(ws, fd))
 469       goto fail;
 470
 471    /* Create managers. */
 472    pb_cache_init(&ws->bo_cache, 500000, 2.0f, 0,
 473                  (ws->info.vram_size + ws->info.gart_size) / 8,
 474                  amdgpu_bo_destroy, amdgpu_bo_can_reclaim);
 475
 476    /* init reference */
 477    pipe_reference_init(&ws->reference, 1);
 478
 479    /* Set functions. */
 480    ws->base.unref = amdgpu_winsys_unref;
 481    ws->base.destroy = amdgpu_winsys_destroy;
 482    ws->base.query_info = amdgpu_winsys_query_info;
 483    ws->base.cs_request_feature = amdgpu_cs_request_feature;
 484    ws->base.query_value = amdgpu_query_value;
 485    ws->base.read_registers = amdgpu_read_registers;
 486
 487    amdgpu_bo_init_functions(ws);
 488    amdgpu_cs_init_functions(ws);
 489    amdgpu_surface_init_functions(ws);
 490
 491    LIST_INITHEAD(&ws->global_bo_list);
 492    pipe_mutex_init(ws->global_bo_list_lock);
 493    pipe_mutex_init(ws->bo_fence_lock);
 494
 495    if (sysconf(_SC_NPROCESSORS_ONLN) > 1 && debug_get_option_thread())
 496       util_queue_init(&ws->cs_queue, "amdgpu_cs", 8, 1, amdgpu_cs_submit_ib);
 497
 498    /* Create the screen at the end. The winsys must be initialized
 499     * completely.
 500     *
 501     * Alternatively, we could create the screen based on "ws->gen"
 502     * and link all drivers into one binary blob. */
 503    ws->base.screen = screen_create(&ws->base);
 504    if (!ws->base.screen) {
 505       amdgpu_winsys_destroy(&ws->base);
 506       pipe_mutex_unlock(dev_tab_mutex);
 507       return NULL;
 508    }
 509
 510    util_hash_table_set(dev_tab, dev, ws);
 511
 512    /* We must unlock the mutex once the winsys is fully initialized, so that
 513     * other threads attempting to create the winsys from the same fd will
 514     * get a fully initialized winsys and not just half-way initialized. */
 515    pipe_mutex_unlock(dev_tab_mutex);
 516
 517    return &ws->base;
 518
 519 fail:
 520    pipe_mutex_unlock(dev_tab_mutex);
 521    pb_cache_deinit(&ws->bo_cache);
 522    FREE(ws);
 523    return NULL;
 524 }