src/gallium/winsys/amdgpu/drm/amdgpu_winsys.c

   1 /*
   2  * Copyright © 2009 Corbin Simpson <MostAwesomeDude@gmail.com>
   3  * Copyright © 2009 Joakim Sindholt <opensource@zhasha.com>
   4  * Copyright © 2011 Marek Olšák <maraeo@gmail.com>
   5  * Copyright © 2015 Advanced Micro Devices, Inc.
   6  * All Rights Reserved.
   7  *
   8  * Permission is hereby granted, free of charge, to any person obtaining
   9  * a copy of this software and associated documentation files (the
  10  * "Software"), to deal in the Software without restriction, including
  11  * without limitation the rights to use, copy, modify, merge, publish,
  12  * distribute, sub license, and/or sell copies of the Software, and to
  13  * permit persons to whom the Software is furnished to do so, subject to
  14  * the following conditions:
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  17  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
  18  * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  19  * NON-INFRINGEMENT. IN NO EVENT SHALL THE COPYRIGHT HOLDERS, AUTHORS
  20  * AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  21  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  22  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
  23  * USE OR OTHER DEALINGS IN THE SOFTWARE.
  24  *
  25  * The above copyright notice and this permission notice (including the
  26  * next paragraph) shall be included in all copies or substantial portions
  27  * of the Software.
  28  */
  29 /*
  30  * Authors:
  31  *      Marek Olšák <maraeo@gmail.com>
  32  */
  33
  34 #include "amdgpu_cs.h"
  35 #include "amdgpu_public.h"
  36
  37 #include "util/u_hash_table.h"
  38 #include <amdgpu_drm.h>
  39 #include <xf86drm.h>
  40 #include <stdio.h>
  41 #include <sys/stat.h>
  42 #include "amd/common/amdgpu_id.h"
  43 #include "amd/common/sid.h"
  44 #include "amd/common/gfx9d.h"
  45
  46 #ifndef AMDGPU_INFO_NUM_VRAM_CPU_PAGE_FAULTS
  47 #define AMDGPU_INFO_NUM_VRAM_CPU_PAGE_FAULTS    0x1E
  48 #endif
  49
  50 static struct util_hash_table *dev_tab = NULL;
  51 static mtx_t dev_tab_mutex = _MTX_INITIALIZER_NP;
  52
  53 DEBUG_GET_ONCE_BOOL_OPTION(all_bos, "RADEON_ALL_BOS", false)
  54
  55 /* Helper function to do the ioctls needed for setup and init. */
  56 static bool do_winsys_init(struct amdgpu_winsys *ws, int fd)
  57 {
  58    if (!ac_query_gpu_info(fd, ws->dev, &ws->info, &ws->amdinfo))
  59       goto fail;
  60
  61    /* LLVM 5.0 is required for GFX9. */
  62    if (ws->info.chip_class >= GFX9 && HAVE_LLVM < 0x0500) {
  63       fprintf(stderr, "amdgpu: LLVM 5.0 is required, got LLVM %i.%i\n",
  64               HAVE_LLVM >> 8, HAVE_LLVM & 255);
  65       goto fail;
  66    }
  67
  68    ws->addrlib = amdgpu_addr_create(&ws->info, &ws->amdinfo, &ws->info.max_alignment);
  69    if (!ws->addrlib) {
  70       fprintf(stderr, "amdgpu: Cannot create addrlib.\n");
  71       goto fail;
  72    }
  73
  74    ws->check_vm = strstr(debug_get_option("R600_DEBUG", ""), "check_vm") != NULL;
  75    ws->debug_all_bos = debug_get_option_all_bos();
  76
  77    return true;
  78
  79 fail:
  80    amdgpu_device_deinitialize(ws->dev);
  81    ws->dev = NULL;
  82    return false;
  83 }
  84
  85 static void do_winsys_deinit(struct amdgpu_winsys *ws)
  86 {
  87    AddrDestroy(ws->addrlib);
  88    amdgpu_device_deinitialize(ws->dev);
  89 }
  90
  91 static void amdgpu_winsys_destroy(struct radeon_winsys *rws)
  92 {
  93    struct amdgpu_winsys *ws = (struct amdgpu_winsys*)rws;
  94
  95    if (util_queue_is_initialized(&ws->cs_queue))
  96       util_queue_destroy(&ws->cs_queue);
  97
  98    mtx_destroy(&ws->bo_fence_lock);
  99    pb_slabs_deinit(&ws->bo_slabs);
 100    pb_cache_deinit(&ws->bo_cache);
 101    mtx_destroy(&ws->global_bo_list_lock);
 102    do_winsys_deinit(ws);
 103    FREE(rws);
 104 }
 105
 106 static void amdgpu_winsys_query_info(struct radeon_winsys *rws,
 107                                      struct radeon_info *info)
 108 {
 109    *info = ((struct amdgpu_winsys *)rws)->info;
 110 }
 111
 112 static bool amdgpu_cs_request_feature(struct radeon_winsys_cs *rcs,
 113                                       enum radeon_feature_id fid,
 114                                       bool enable)
 115 {
 116    return false;
 117 }
 118
 119 static uint64_t amdgpu_query_value(struct radeon_winsys *rws,
 120                                    enum radeon_value_id value)
 121 {
 122    struct amdgpu_winsys *ws = (struct amdgpu_winsys*)rws;
 123    struct amdgpu_heap_info heap;
 124    uint64_t retval = 0;
 125
 126    switch (value) {
 127    case RADEON_REQUESTED_VRAM_MEMORY:
 128       return ws->allocated_vram;
 129    case RADEON_REQUESTED_GTT_MEMORY:
 130       return ws->allocated_gtt;
 131    case RADEON_MAPPED_VRAM:
 132       return ws->mapped_vram;
 133    case RADEON_MAPPED_GTT:
 134       return ws->mapped_gtt;
 135    case RADEON_BUFFER_WAIT_TIME_NS:
 136       return ws->buffer_wait_time;
 137    case RADEON_NUM_MAPPED_BUFFERS:
 138       return ws->num_mapped_buffers;
 139    case RADEON_TIMESTAMP:
 140       amdgpu_query_info(ws->dev, AMDGPU_INFO_TIMESTAMP, 8, &retval);
 141       return retval;
 142    case RADEON_NUM_GFX_IBS:
 143       return ws->num_gfx_IBs;
 144    case RADEON_NUM_SDMA_IBS:
 145       return ws->num_sdma_IBs;
 146    case RADEON_GFX_BO_LIST_COUNTER:
 147       return ws->gfx_bo_list_counter;
 148    case RADEON_GFX_IB_SIZE_COUNTER:
 149       return ws->gfx_ib_size_counter;
 150    case RADEON_NUM_BYTES_MOVED:
 151       amdgpu_query_info(ws->dev, AMDGPU_INFO_NUM_BYTES_MOVED, 8, &retval);
 152       return retval;
 153    case RADEON_NUM_EVICTIONS:
 154       amdgpu_query_info(ws->dev, AMDGPU_INFO_NUM_EVICTIONS, 8, &retval);
 155       return retval;
 156    case RADEON_NUM_VRAM_CPU_PAGE_FAULTS:
 157       amdgpu_query_info(ws->dev, AMDGPU_INFO_NUM_VRAM_CPU_PAGE_FAULTS, 8, &retval);
 158       return retval;
 159    case RADEON_VRAM_USAGE:
 160       amdgpu_query_heap_info(ws->dev, AMDGPU_GEM_DOMAIN_VRAM, 0, &heap);
 161       return heap.heap_usage;
 162    case RADEON_VRAM_VIS_USAGE:
 163       amdgpu_query_heap_info(ws->dev, AMDGPU_GEM_DOMAIN_VRAM,
 164                              AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED, &heap);
 165       return heap.heap_usage;
 166    case RADEON_GTT_USAGE:
 167       amdgpu_query_heap_info(ws->dev, AMDGPU_GEM_DOMAIN_GTT, 0, &heap);
 168       return heap.heap_usage;
 169    case RADEON_GPU_TEMPERATURE:
 170       amdgpu_query_sensor_info(ws->dev, AMDGPU_INFO_SENSOR_GPU_TEMP, 4, &retval);
 171       return retval;
 172    case RADEON_CURRENT_SCLK:
 173       amdgpu_query_sensor_info(ws->dev, AMDGPU_INFO_SENSOR_GFX_SCLK, 4, &retval);
 174       return retval;
 175    case RADEON_CURRENT_MCLK:
 176       amdgpu_query_sensor_info(ws->dev, AMDGPU_INFO_SENSOR_GFX_MCLK, 4, &retval);
 177       return retval;
 178    case RADEON_GPU_RESET_COUNTER:
 179       assert(0);
 180       return 0;
 181    case RADEON_CS_THREAD_TIME:
 182       return util_queue_get_thread_time_nano(&ws->cs_queue, 0);
 183    }
 184    return 0;
 185 }
 186
 187 static bool amdgpu_read_registers(struct radeon_winsys *rws,
 188                                   unsigned reg_offset,
 189                                   unsigned num_registers, uint32_t *out)
 190 {
 191    struct amdgpu_winsys *ws = (struct amdgpu_winsys*)rws;
 192
 193    return amdgpu_read_mm_registers(ws->dev, reg_offset / 4, num_registers,
 194                                    0xffffffff, 0, out) == 0;
 195 }
 196
 197 static unsigned hash_dev(void *key)
 198 {
 199 #if defined(PIPE_ARCH_X86_64)
 200    return pointer_to_intptr(key) ^ (pointer_to_intptr(key) >> 32);
 201 #else
 202    return pointer_to_intptr(key);
 203 #endif
 204 }
 205
 206 static int compare_dev(void *key1, void *key2)
 207 {
 208    return key1 != key2;
 209 }
 210
 211 static bool amdgpu_winsys_unref(struct radeon_winsys *rws)
 212 {
 213    struct amdgpu_winsys *ws = (struct amdgpu_winsys*)rws;
 214    bool destroy;
 215
 216    /* When the reference counter drops to zero, remove the device pointer
 217     * from the table.
 218     * This must happen while the mutex is locked, so that
 219     * amdgpu_winsys_create in another thread doesn't get the winsys
 220     * from the table when the counter drops to 0. */
 221    mtx_lock(&dev_tab_mutex);
 222
 223    destroy = pipe_reference(&ws->reference, NULL);
 224    if (destroy && dev_tab)
 225       util_hash_table_remove(dev_tab, ws->dev);
 226
 227    mtx_unlock(&dev_tab_mutex);
 228    return destroy;
 229 }
 230
 231 static const char* amdgpu_get_chip_name(struct radeon_winsys *ws)
 232 {
 233    amdgpu_device_handle dev = ((struct amdgpu_winsys *)ws)->dev;
 234    return amdgpu_get_marketing_name(dev);
 235 }
 236
 237
 238 PUBLIC struct radeon_winsys *
 239 amdgpu_winsys_create(int fd, const struct pipe_screen_config *config,
 240                      radeon_screen_create_t screen_create)
 241 {
 242    struct amdgpu_winsys *ws;
 243    drmVersionPtr version = drmGetVersion(fd);
 244    amdgpu_device_handle dev;
 245    uint32_t drm_major, drm_minor, r;
 246
 247    /* The DRM driver version of amdgpu is 3.x.x. */
 248    if (version->version_major != 3) {
 249       drmFreeVersion(version);
 250       return NULL;
 251    }
 252    drmFreeVersion(version);
 253
 254    /* Look up the winsys from the dev table. */
 255    mtx_lock(&dev_tab_mutex);
 256    if (!dev_tab)
 257       dev_tab = util_hash_table_create(hash_dev, compare_dev);
 258
 259    /* Initialize the amdgpu device. This should always return the same pointer
 260     * for the same fd. */
 261    r = amdgpu_device_initialize(fd, &drm_major, &drm_minor, &dev);
 262    if (r) {
 263       mtx_unlock(&dev_tab_mutex);
 264       fprintf(stderr, "amdgpu: amdgpu_device_initialize failed.\n");
 265       return NULL;
 266    }
 267
 268    /* Lookup a winsys if we have already created one for this device. */
 269    ws = util_hash_table_get(dev_tab, dev);
 270    if (ws) {
 271       pipe_reference(NULL, &ws->reference);
 272       mtx_unlock(&dev_tab_mutex);
 273       return &ws->base;
 274    }
 275
 276    /* Create a new winsys. */
 277    ws = CALLOC_STRUCT(amdgpu_winsys);
 278    if (!ws)
 279       goto fail;
 280
 281    ws->dev = dev;
 282    ws->info.drm_major = drm_major;
 283    ws->info.drm_minor = drm_minor;
 284
 285    if (!do_winsys_init(ws, fd))
 286       goto fail_alloc;
 287
 288    /* Create managers. */
 289    pb_cache_init(&ws->bo_cache, 500000, ws->check_vm ? 1.0f : 2.0f, 0,
 290                  (ws->info.vram_size + ws->info.gart_size) / 8,
 291                  amdgpu_bo_destroy, amdgpu_bo_can_reclaim);
 292
 293    if (!pb_slabs_init(&ws->bo_slabs,
 294                       AMDGPU_SLAB_MIN_SIZE_LOG2, AMDGPU_SLAB_MAX_SIZE_LOG2,
 295                       RADEON_MAX_SLAB_HEAPS,
 296                       ws,
 297                       amdgpu_bo_can_reclaim_slab,
 298                       amdgpu_bo_slab_alloc,
 299                       amdgpu_bo_slab_free))
 300       goto fail_cache;
 301
 302    ws->info.min_alloc_size = 1 << AMDGPU_SLAB_MIN_SIZE_LOG2;
 303
 304    /* init reference */
 305    pipe_reference_init(&ws->reference, 1);
 306
 307    /* Set functions. */
 308    ws->base.unref = amdgpu_winsys_unref;
 309    ws->base.destroy = amdgpu_winsys_destroy;
 310    ws->base.query_info = amdgpu_winsys_query_info;
 311    ws->base.cs_request_feature = amdgpu_cs_request_feature;
 312    ws->base.query_value = amdgpu_query_value;
 313    ws->base.read_registers = amdgpu_read_registers;
 314    ws->base.get_chip_name = amdgpu_get_chip_name;
 315
 316    amdgpu_bo_init_functions(ws);
 317    amdgpu_cs_init_functions(ws);
 318    amdgpu_surface_init_functions(ws);
 319
 320    LIST_INITHEAD(&ws->global_bo_list);
 321    (void) mtx_init(&ws->global_bo_list_lock, mtx_plain);
 322    (void) mtx_init(&ws->bo_fence_lock, mtx_plain);
 323
 324    if (!util_queue_init(&ws->cs_queue, "amdgpu_cs", 8, 1,
 325                         UTIL_QUEUE_INIT_RESIZE_IF_FULL)) {
 326       amdgpu_winsys_destroy(&ws->base);
 327       mtx_unlock(&dev_tab_mutex);
 328       return NULL;
 329    }
 330
 331    /* Create the screen at the end. The winsys must be initialized
 332     * completely.
 333     *
 334     * Alternatively, we could create the screen based on "ws->gen"
 335     * and link all drivers into one binary blob. */
 336    ws->base.screen = screen_create(&ws->base, config);
 337    if (!ws->base.screen) {
 338       amdgpu_winsys_destroy(&ws->base);
 339       mtx_unlock(&dev_tab_mutex);
 340       return NULL;
 341    }
 342
 343    util_hash_table_set(dev_tab, dev, ws);
 344
 345    /* We must unlock the mutex once the winsys is fully initialized, so that
 346     * other threads attempting to create the winsys from the same fd will
 347     * get a fully initialized winsys and not just half-way initialized. */
 348    mtx_unlock(&dev_tab_mutex);
 349
 350    return &ws->base;
 351
 352 fail_cache:
 353    pb_cache_deinit(&ws->bo_cache);
 354    do_winsys_deinit(ws);
 355 fail_alloc:
 356    FREE(ws);
 357 fail:
 358    mtx_unlock(&dev_tab_mutex);
 359    return NULL;
 360 }