src/gallium/winsys/amdgpu/drm/amdgpu_winsys.c

   1 /*
   2  * Copyright © 2009 Corbin Simpson <MostAwesomeDude@gmail.com>
   3  * Copyright © 2009 Joakim Sindholt <opensource@zhasha.com>
   4  * Copyright © 2011 Marek Olšák <maraeo@gmail.com>
   5  * Copyright © 2015 Advanced Micro Devices, Inc.
   6  * All Rights Reserved.
   7  *
   8  * Permission is hereby granted, free of charge, to any person obtaining
   9  * a copy of this software and associated documentation files (the
  10  * "Software"), to deal in the Software without restriction, including
  11  * without limitation the rights to use, copy, modify, merge, publish,
  12  * distribute, sub license, and/or sell copies of the Software, and to
  13  * permit persons to whom the Software is furnished to do so, subject to
  14  * the following conditions:
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  17  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
  18  * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  19  * NON-INFRINGEMENT. IN NO EVENT SHALL THE COPYRIGHT HOLDERS, AUTHORS
  20  * AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  21  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  22  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
  23  * USE OR OTHER DEALINGS IN THE SOFTWARE.
  24  *
  25  * The above copyright notice and this permission notice (including the
  26  * next paragraph) shall be included in all copies or substantial portions
  27  * of the Software.
  28  */
  29
  30 #include "amdgpu_cs.h"
  31 #include "amdgpu_public.h"
  32
  33 #include "util/u_hash_table.h"
  34 #include <amdgpu_drm.h>
  35 #include <xf86drm.h>
  36 #include <stdio.h>
  37 #include <sys/stat.h>
  38 #include "amd/common/amdgpu_id.h"
  39 #include "amd/common/sid.h"
  40 #include "amd/common/gfx9d.h"
  41
  42 #ifndef AMDGPU_INFO_NUM_VRAM_CPU_PAGE_FAULTS
  43 #define AMDGPU_INFO_NUM_VRAM_CPU_PAGE_FAULTS    0x1E
  44 #endif
  45
  46 static struct util_hash_table *dev_tab = NULL;
  47 static mtx_t dev_tab_mutex = _MTX_INITIALIZER_NP;
  48
  49 DEBUG_GET_ONCE_BOOL_OPTION(all_bos, "RADEON_ALL_BOS", false)
  50
  51 /* Helper function to do the ioctls needed for setup and init. */
  52 static bool do_winsys_init(struct amdgpu_winsys *ws, int fd)
  53 {
  54    if (!ac_query_gpu_info(fd, ws->dev, &ws->info, &ws->amdinfo))
  55       goto fail;
  56
  57    /* LLVM 5.0 is required for GFX9. */
  58    if (ws->info.chip_class >= GFX9 && HAVE_LLVM < 0x0500) {
  59       fprintf(stderr, "amdgpu: LLVM 5.0 is required, got LLVM %i.%i\n",
  60               HAVE_LLVM >> 8, HAVE_LLVM & 255);
  61       goto fail;
  62    }
  63
  64    ws->addrlib = amdgpu_addr_create(&ws->info, &ws->amdinfo, &ws->info.max_alignment);
  65    if (!ws->addrlib) {
  66       fprintf(stderr, "amdgpu: Cannot create addrlib.\n");
  67       goto fail;
  68    }
  69
  70    ws->check_vm = strstr(debug_get_option("R600_DEBUG", ""), "check_vm") != NULL;
  71    ws->debug_all_bos = debug_get_option_all_bos();
  72
  73    return true;
  74
  75 fail:
  76    amdgpu_device_deinitialize(ws->dev);
  77    ws->dev = NULL;
  78    return false;
  79 }
  80
  81 static void do_winsys_deinit(struct amdgpu_winsys *ws)
  82 {
  83    AddrDestroy(ws->addrlib);
  84    amdgpu_device_deinitialize(ws->dev);
  85 }
  86
  87 static void amdgpu_winsys_destroy(struct radeon_winsys *rws)
  88 {
  89    struct amdgpu_winsys *ws = (struct amdgpu_winsys*)rws;
  90
  91    if (util_queue_is_initialized(&ws->cs_queue))
  92       util_queue_destroy(&ws->cs_queue);
  93
  94    mtx_destroy(&ws->bo_fence_lock);
  95    pb_slabs_deinit(&ws->bo_slabs);
  96    pb_cache_deinit(&ws->bo_cache);
  97    mtx_destroy(&ws->global_bo_list_lock);
  98    do_winsys_deinit(ws);
  99    FREE(rws);
 100 }
 101
 102 static void amdgpu_winsys_query_info(struct radeon_winsys *rws,
 103                                      struct radeon_info *info)
 104 {
 105    *info = ((struct amdgpu_winsys *)rws)->info;
 106 }
 107
 108 static bool amdgpu_cs_request_feature(struct radeon_winsys_cs *rcs,
 109                                       enum radeon_feature_id fid,
 110                                       bool enable)
 111 {
 112    return false;
 113 }
 114
 115 static uint64_t amdgpu_query_value(struct radeon_winsys *rws,
 116                                    enum radeon_value_id value)
 117 {
 118    struct amdgpu_winsys *ws = (struct amdgpu_winsys*)rws;
 119    struct amdgpu_heap_info heap;
 120    uint64_t retval = 0;
 121
 122    switch (value) {
 123    case RADEON_REQUESTED_VRAM_MEMORY:
 124       return ws->allocated_vram;
 125    case RADEON_REQUESTED_GTT_MEMORY:
 126       return ws->allocated_gtt;
 127    case RADEON_MAPPED_VRAM:
 128       return ws->mapped_vram;
 129    case RADEON_MAPPED_GTT:
 130       return ws->mapped_gtt;
 131    case RADEON_BUFFER_WAIT_TIME_NS:
 132       return ws->buffer_wait_time;
 133    case RADEON_NUM_MAPPED_BUFFERS:
 134       return ws->num_mapped_buffers;
 135    case RADEON_TIMESTAMP:
 136       amdgpu_query_info(ws->dev, AMDGPU_INFO_TIMESTAMP, 8, &retval);
 137       return retval;
 138    case RADEON_NUM_GFX_IBS:
 139       return ws->num_gfx_IBs;
 140    case RADEON_NUM_SDMA_IBS:
 141       return ws->num_sdma_IBs;
 142    case RADEON_GFX_BO_LIST_COUNTER:
 143       return ws->gfx_bo_list_counter;
 144    case RADEON_GFX_IB_SIZE_COUNTER:
 145       return ws->gfx_ib_size_counter;
 146    case RADEON_NUM_BYTES_MOVED:
 147       amdgpu_query_info(ws->dev, AMDGPU_INFO_NUM_BYTES_MOVED, 8, &retval);
 148       return retval;
 149    case RADEON_NUM_EVICTIONS:
 150       amdgpu_query_info(ws->dev, AMDGPU_INFO_NUM_EVICTIONS, 8, &retval);
 151       return retval;
 152    case RADEON_NUM_VRAM_CPU_PAGE_FAULTS:
 153       amdgpu_query_info(ws->dev, AMDGPU_INFO_NUM_VRAM_CPU_PAGE_FAULTS, 8, &retval);
 154       return retval;
 155    case RADEON_VRAM_USAGE:
 156       amdgpu_query_heap_info(ws->dev, AMDGPU_GEM_DOMAIN_VRAM, 0, &heap);
 157       return heap.heap_usage;
 158    case RADEON_VRAM_VIS_USAGE:
 159       amdgpu_query_heap_info(ws->dev, AMDGPU_GEM_DOMAIN_VRAM,
 160                              AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED, &heap);
 161       return heap.heap_usage;
 162    case RADEON_GTT_USAGE:
 163       amdgpu_query_heap_info(ws->dev, AMDGPU_GEM_DOMAIN_GTT, 0, &heap);
 164       return heap.heap_usage;
 165    case RADEON_GPU_TEMPERATURE:
 166       amdgpu_query_sensor_info(ws->dev, AMDGPU_INFO_SENSOR_GPU_TEMP, 4, &retval);
 167       return retval;
 168    case RADEON_CURRENT_SCLK:
 169       amdgpu_query_sensor_info(ws->dev, AMDGPU_INFO_SENSOR_GFX_SCLK, 4, &retval);
 170       return retval;
 171    case RADEON_CURRENT_MCLK:
 172       amdgpu_query_sensor_info(ws->dev, AMDGPU_INFO_SENSOR_GFX_MCLK, 4, &retval);
 173       return retval;
 174    case RADEON_GPU_RESET_COUNTER:
 175       assert(0);
 176       return 0;
 177    case RADEON_CS_THREAD_TIME:
 178       return util_queue_get_thread_time_nano(&ws->cs_queue, 0);
 179    }
 180    return 0;
 181 }
 182
 183 static bool amdgpu_read_registers(struct radeon_winsys *rws,
 184                                   unsigned reg_offset,
 185                                   unsigned num_registers, uint32_t *out)
 186 {
 187    struct amdgpu_winsys *ws = (struct amdgpu_winsys*)rws;
 188
 189    return amdgpu_read_mm_registers(ws->dev, reg_offset / 4, num_registers,
 190                                    0xffffffff, 0, out) == 0;
 191 }
 192
 193 static unsigned hash_dev(void *key)
 194 {
 195 #if defined(PIPE_ARCH_X86_64)
 196    return pointer_to_intptr(key) ^ (pointer_to_intptr(key) >> 32);
 197 #else
 198    return pointer_to_intptr(key);
 199 #endif
 200 }
 201
 202 static int compare_dev(void *key1, void *key2)
 203 {
 204    return key1 != key2;
 205 }
 206
 207 static bool amdgpu_winsys_unref(struct radeon_winsys *rws)
 208 {
 209    struct amdgpu_winsys *ws = (struct amdgpu_winsys*)rws;
 210    bool destroy;
 211
 212    /* When the reference counter drops to zero, remove the device pointer
 213     * from the table.
 214     * This must happen while the mutex is locked, so that
 215     * amdgpu_winsys_create in another thread doesn't get the winsys
 216     * from the table when the counter drops to 0. */
 217    mtx_lock(&dev_tab_mutex);
 218
 219    destroy = pipe_reference(&ws->reference, NULL);
 220    if (destroy && dev_tab)
 221       util_hash_table_remove(dev_tab, ws->dev);
 222
 223    mtx_unlock(&dev_tab_mutex);
 224    return destroy;
 225 }
 226
 227 static const char* amdgpu_get_chip_name(struct radeon_winsys *ws)
 228 {
 229    amdgpu_device_handle dev = ((struct amdgpu_winsys *)ws)->dev;
 230    return amdgpu_get_marketing_name(dev);
 231 }
 232
 233
 234 PUBLIC struct radeon_winsys *
 235 amdgpu_winsys_create(int fd, const struct pipe_screen_config *config,
 236                      radeon_screen_create_t screen_create)
 237 {
 238    struct amdgpu_winsys *ws;
 239    drmVersionPtr version = drmGetVersion(fd);
 240    amdgpu_device_handle dev;
 241    uint32_t drm_major, drm_minor, r;
 242
 243    /* The DRM driver version of amdgpu is 3.x.x. */
 244    if (version->version_major != 3) {
 245       drmFreeVersion(version);
 246       return NULL;
 247    }
 248    drmFreeVersion(version);
 249
 250    /* Look up the winsys from the dev table. */
 251    mtx_lock(&dev_tab_mutex);
 252    if (!dev_tab)
 253       dev_tab = util_hash_table_create(hash_dev, compare_dev);
 254
 255    /* Initialize the amdgpu device. This should always return the same pointer
 256     * for the same fd. */
 257    r = amdgpu_device_initialize(fd, &drm_major, &drm_minor, &dev);
 258    if (r) {
 259       mtx_unlock(&dev_tab_mutex);
 260       fprintf(stderr, "amdgpu: amdgpu_device_initialize failed.\n");
 261       return NULL;
 262    }
 263
 264    /* Lookup a winsys if we have already created one for this device. */
 265    ws = util_hash_table_get(dev_tab, dev);
 266    if (ws) {
 267       pipe_reference(NULL, &ws->reference);
 268       mtx_unlock(&dev_tab_mutex);
 269       return &ws->base;
 270    }
 271
 272    /* Create a new winsys. */
 273    ws = CALLOC_STRUCT(amdgpu_winsys);
 274    if (!ws)
 275       goto fail;
 276
 277    ws->dev = dev;
 278    ws->info.drm_major = drm_major;
 279    ws->info.drm_minor = drm_minor;
 280
 281    if (!do_winsys_init(ws, fd))
 282       goto fail_alloc;
 283
 284    /* Create managers. */
 285    pb_cache_init(&ws->bo_cache, 500000, ws->check_vm ? 1.0f : 2.0f, 0,
 286                  (ws->info.vram_size + ws->info.gart_size) / 8,
 287                  amdgpu_bo_destroy, amdgpu_bo_can_reclaim);
 288
 289    if (!pb_slabs_init(&ws->bo_slabs,
 290                       AMDGPU_SLAB_MIN_SIZE_LOG2, AMDGPU_SLAB_MAX_SIZE_LOG2,
 291                       RADEON_MAX_SLAB_HEAPS,
 292                       ws,
 293                       amdgpu_bo_can_reclaim_slab,
 294                       amdgpu_bo_slab_alloc,
 295                       amdgpu_bo_slab_free))
 296       goto fail_cache;
 297
 298    ws->info.min_alloc_size = 1 << AMDGPU_SLAB_MIN_SIZE_LOG2;
 299
 300    /* init reference */
 301    pipe_reference_init(&ws->reference, 1);
 302
 303    /* Set functions. */
 304    ws->base.unref = amdgpu_winsys_unref;
 305    ws->base.destroy = amdgpu_winsys_destroy;
 306    ws->base.query_info = amdgpu_winsys_query_info;
 307    ws->base.cs_request_feature = amdgpu_cs_request_feature;
 308    ws->base.query_value = amdgpu_query_value;
 309    ws->base.read_registers = amdgpu_read_registers;
 310    ws->base.get_chip_name = amdgpu_get_chip_name;
 311
 312    amdgpu_bo_init_functions(ws);
 313    amdgpu_cs_init_functions(ws);
 314    amdgpu_surface_init_functions(ws);
 315
 316    LIST_INITHEAD(&ws->global_bo_list);
 317    (void) mtx_init(&ws->global_bo_list_lock, mtx_plain);
 318    (void) mtx_init(&ws->bo_fence_lock, mtx_plain);
 319
 320    if (!util_queue_init(&ws->cs_queue, "amdgpu_cs", 8, 1,
 321                         UTIL_QUEUE_INIT_RESIZE_IF_FULL)) {
 322       amdgpu_winsys_destroy(&ws->base);
 323       mtx_unlock(&dev_tab_mutex);
 324       return NULL;
 325    }
 326
 327    /* Create the screen at the end. The winsys must be initialized
 328     * completely.
 329     *
 330     * Alternatively, we could create the screen based on "ws->gen"
 331     * and link all drivers into one binary blob. */
 332    ws->base.screen = screen_create(&ws->base, config);
 333    if (!ws->base.screen) {
 334       amdgpu_winsys_destroy(&ws->base);
 335       mtx_unlock(&dev_tab_mutex);
 336       return NULL;
 337    }
 338
 339    util_hash_table_set(dev_tab, dev, ws);
 340
 341    /* We must unlock the mutex once the winsys is fully initialized, so that
 342     * other threads attempting to create the winsys from the same fd will
 343     * get a fully initialized winsys and not just half-way initialized. */
 344    mtx_unlock(&dev_tab_mutex);
 345
 346    return &ws->base;
 347
 348 fail_cache:
 349    pb_cache_deinit(&ws->bo_cache);
 350    do_winsys_deinit(ws);
 351 fail_alloc:
 352    FREE(ws);
 353 fail:
 354    mtx_unlock(&dev_tab_mutex);
 355    return NULL;
 356 }