src/gallium/winsys/amdgpu/drm/amdgpu_winsys.c

   1 /*
   2  * Copyright © 2009 Corbin Simpson <MostAwesomeDude@gmail.com>
   3  * Copyright © 2009 Joakim Sindholt <opensource@zhasha.com>
   4  * Copyright © 2011 Marek Olšák <maraeo@gmail.com>
   5  * Copyright © 2015 Advanced Micro Devices, Inc.
   6  * All Rights Reserved.
   7  *
   8  * Permission is hereby granted, free of charge, to any person obtaining
   9  * a copy of this software and associated documentation files (the
  10  * "Software"), to deal in the Software without restriction, including
  11  * without limitation the rights to use, copy, modify, merge, publish,
  12  * distribute, sub license, and/or sell copies of the Software, and to
  13  * permit persons to whom the Software is furnished to do so, subject to
  14  * the following conditions:
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  17  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
  18  * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  19  * NON-INFRINGEMENT. IN NO EVENT SHALL THE COPYRIGHT HOLDERS, AUTHORS
  20  * AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  21  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  22  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
  23  * USE OR OTHER DEALINGS IN THE SOFTWARE.
  24  *
  25  * The above copyright notice and this permission notice (including the
  26  * next paragraph) shall be included in all copies or substantial portions
  27  * of the Software.
  28  */
  29 /*
  30  * Authors:
  31  *      Marek Olšák <maraeo@gmail.com>
  32  */
  33
  34 #include "amdgpu_cs.h"
  35 #include "amdgpu_public.h"
  36
  37 #include "util/u_hash_table.h"
  38 #include <amdgpu_drm.h>
  39 #include <xf86drm.h>
  40 #include <stdio.h>
  41 #include <sys/stat.h>
  42 #include "amdgpu_id.h"
  43
  44 #define CIK_TILE_MODE_COLOR_2D                  14
  45
  46 #define CIK__GB_TILE_MODE__PIPE_CONFIG(x)        (((x) >> 6) & 0x1f)
  47 #define     CIK__PIPE_CONFIG__ADDR_SURF_P2               0
  48 #define     CIK__PIPE_CONFIG__ADDR_SURF_P4_8x16          4
  49 #define     CIK__PIPE_CONFIG__ADDR_SURF_P4_16x16         5
  50 #define     CIK__PIPE_CONFIG__ADDR_SURF_P4_16x32         6
  51 #define     CIK__PIPE_CONFIG__ADDR_SURF_P4_32x32         7
  52 #define     CIK__PIPE_CONFIG__ADDR_SURF_P8_16x16_8x16    8
  53 #define     CIK__PIPE_CONFIG__ADDR_SURF_P8_16x32_8x16    9
  54 #define     CIK__PIPE_CONFIG__ADDR_SURF_P8_32x32_8x16    10
  55 #define     CIK__PIPE_CONFIG__ADDR_SURF_P8_16x32_16x16   11
  56 #define     CIK__PIPE_CONFIG__ADDR_SURF_P8_32x32_16x16   12
  57 #define     CIK__PIPE_CONFIG__ADDR_SURF_P8_32x32_16x32   13
  58 #define     CIK__PIPE_CONFIG__ADDR_SURF_P8_32x64_32x32   14
  59 #define     CIK__PIPE_CONFIG__ADDR_SURF_P16_32X32_8X16   16
  60 #define     CIK__PIPE_CONFIG__ADDR_SURF_P16_32X32_16X16  17
  61
  62 static struct util_hash_table *dev_tab = NULL;
  63 pipe_static_mutex(dev_tab_mutex);
  64
  65 static unsigned cik_get_num_tile_pipes(struct amdgpu_gpu_info *info)
  66 {
  67    unsigned mode2d = info->gb_tile_mode[CIK_TILE_MODE_COLOR_2D];
  68
  69    switch (CIK__GB_TILE_MODE__PIPE_CONFIG(mode2d)) {
  70    case CIK__PIPE_CONFIG__ADDR_SURF_P2:
  71    default:
  72        return 2;
  73    case CIK__PIPE_CONFIG__ADDR_SURF_P4_8x16:
  74    case CIK__PIPE_CONFIG__ADDR_SURF_P4_16x16:
  75    case CIK__PIPE_CONFIG__ADDR_SURF_P4_16x32:
  76    case CIK__PIPE_CONFIG__ADDR_SURF_P4_32x32:
  77        return 4;
  78    case CIK__PIPE_CONFIG__ADDR_SURF_P8_16x16_8x16:
  79    case CIK__PIPE_CONFIG__ADDR_SURF_P8_16x32_8x16:
  80    case CIK__PIPE_CONFIG__ADDR_SURF_P8_32x32_8x16:
  81    case CIK__PIPE_CONFIG__ADDR_SURF_P8_16x32_16x16:
  82    case CIK__PIPE_CONFIG__ADDR_SURF_P8_32x32_16x16:
  83    case CIK__PIPE_CONFIG__ADDR_SURF_P8_32x32_16x32:
  84    case CIK__PIPE_CONFIG__ADDR_SURF_P8_32x64_32x32:
  85        return 8;
  86    case CIK__PIPE_CONFIG__ADDR_SURF_P16_32X32_8X16:
  87    case CIK__PIPE_CONFIG__ADDR_SURF_P16_32X32_16X16:
  88        return 16;
  89    }
  90 }
  91
  92 /* Convert Sea Islands register values GB_ADDR_CFG and MC_ADDR_CFG
  93  * into GB_TILING_CONFIG register which is only present on R600-R700. */
  94 static unsigned r600_get_gb_tiling_config(struct amdgpu_gpu_info *info)
  95 {
  96    unsigned num_pipes = info->gb_addr_cfg & 0x7;
  97    unsigned num_banks = info->mc_arb_ramcfg & 0x3;
  98    unsigned pipe_interleave_bytes = (info->gb_addr_cfg >> 4) & 0x7;
  99    unsigned row_size = (info->gb_addr_cfg >> 28) & 0x3;
 100
 101    return num_pipes | (num_banks << 4) |
 102          (pipe_interleave_bytes << 8) |
 103          (row_size << 12);
 104 }
 105
 106 /* Helper function to do the ioctls needed for setup and init. */
 107 static boolean do_winsys_init(struct amdgpu_winsys *ws)
 108 {
 109    struct amdgpu_buffer_size_alignments alignment_info = {};
 110    struct amdgpu_heap_info vram, gtt;
 111    struct drm_amdgpu_info_hw_ip dma = {}, uvd = {}, vce = {};
 112    uint32_t vce_version = 0, vce_feature = 0;
 113    int r, i, j;
 114
 115    /* Query hardware and driver information. */
 116    r = amdgpu_query_gpu_info(ws->dev, &ws->amdinfo);
 117    if (r) {
 118       fprintf(stderr, "amdgpu: amdgpu_query_gpu_info failed.\n");
 119       goto fail;
 120    }
 121
 122    r = amdgpu_query_buffer_size_alignment(ws->dev, &alignment_info);
 123    if (r) {
 124       fprintf(stderr, "amdgpu: amdgpu_query_buffer_size_alignment failed.\n");
 125       goto fail;
 126    }
 127
 128    r = amdgpu_query_heap_info(ws->dev, AMDGPU_GEM_DOMAIN_VRAM, 0, &vram);
 129    if (r) {
 130       fprintf(stderr, "amdgpu: amdgpu_query_heap_info(vram) failed.\n");
 131       goto fail;
 132    }
 133
 134    r = amdgpu_query_heap_info(ws->dev, AMDGPU_GEM_DOMAIN_GTT, 0, &gtt);
 135    if (r) {
 136       fprintf(stderr, "amdgpu: amdgpu_query_heap_info(gtt) failed.\n");
 137       goto fail;
 138    }
 139
 140    r = amdgpu_query_hw_ip_info(ws->dev, AMDGPU_HW_IP_DMA, 0, &dma);
 141    if (r) {
 142       fprintf(stderr, "amdgpu: amdgpu_query_hw_ip_info(dma) failed.\n");
 143       goto fail;
 144    }
 145
 146    r = amdgpu_query_hw_ip_info(ws->dev, AMDGPU_HW_IP_UVD, 0, &uvd);
 147    if (r) {
 148       fprintf(stderr, "amdgpu: amdgpu_query_hw_ip_info(uvd) failed.\n");
 149       goto fail;
 150    }
 151
 152    r = amdgpu_query_hw_ip_info(ws->dev, AMDGPU_HW_IP_VCE, 0, &vce);
 153    if (r) {
 154       fprintf(stderr, "amdgpu: amdgpu_query_hw_ip_info(vce) failed.\n");
 155       goto fail;
 156    }
 157
 158    r = amdgpu_query_firmware_version(ws->dev, AMDGPU_INFO_FW_VCE, 0, 0,
 159                                      &vce_version, &vce_feature);
 160    if (r) {
 161       fprintf(stderr, "amdgpu: amdgpu_query_firmware_version(vce) failed.\n");
 162       goto fail;
 163    }
 164
 165    /* Set chip identification. */
 166    ws->info.pci_id = ws->amdinfo.asic_id; /* TODO: is this correct? */
 167    ws->info.vce_harvest_config = ws->amdinfo.vce_harvest_config;
 168
 169    switch (ws->info.pci_id) {
 170 #define CHIPSET(pci_id, name, cfamily) case pci_id: ws->info.family = CHIP_##cfamily; break;
 171 #include "pci_ids/radeonsi_pci_ids.h"
 172 #undef CHIPSET
 173
 174    default:
 175       fprintf(stderr, "amdgpu: Invalid PCI ID.\n");
 176       goto fail;
 177    }
 178
 179    if (ws->info.family >= CHIP_TONGA)
 180       ws->info.chip_class = VI;
 181    else if (ws->info.family >= CHIP_BONAIRE)
 182       ws->info.chip_class = CIK;
 183    else {
 184       fprintf(stderr, "amdgpu: Unknown family.\n");
 185       goto fail;
 186    }
 187
 188    /* LLVM 3.6 is required for VI. */
 189    if (ws->info.chip_class >= VI &&
 190        (HAVE_LLVM < 0x0306 ||
 191         (HAVE_LLVM == 0x0306 && MESA_LLVM_VERSION_PATCH < 1))) {
 192       fprintf(stderr, "amdgpu: LLVM 3.6.1 is required, got LLVM %i.%i.%i\n",
 193               HAVE_LLVM >> 8, HAVE_LLVM & 255, MESA_LLVM_VERSION_PATCH);
 194       goto fail;
 195    }
 196
 197    /* family and rev_id are for addrlib */
 198    switch (ws->info.family) {
 199    case CHIP_BONAIRE:
 200       ws->family = FAMILY_CI;
 201       ws->rev_id = CI_BONAIRE_M_A0;
 202       break;
 203    case CHIP_KAVERI:
 204       ws->family = FAMILY_KV;
 205       ws->rev_id = KV_SPECTRE_A0;
 206       break;
 207    case CHIP_KABINI:
 208       ws->family = FAMILY_KV;
 209       ws->rev_id = KB_KALINDI_A0;
 210       break;
 211    case CHIP_HAWAII:
 212       ws->family = FAMILY_CI;
 213       ws->rev_id = CI_HAWAII_P_A0;
 214       break;
 215    case CHIP_MULLINS:
 216       ws->family = FAMILY_KV;
 217       ws->rev_id = ML_GODAVARI_A0;
 218       break;
 219    case CHIP_TONGA:
 220       ws->family = FAMILY_VI;
 221       ws->rev_id = VI_TONGA_P_A0;
 222       break;
 223    case CHIP_ICELAND:
 224       ws->family = FAMILY_VI;
 225       ws->rev_id = VI_ICELAND_M_A0;
 226       break;
 227    case CHIP_CARRIZO:
 228       ws->family = FAMILY_CZ;
 229       ws->rev_id = CARRIZO_A0;
 230       break;
 231    case CHIP_STONEY:
 232       ws->family = FAMILY_CZ;
 233       ws->rev_id = STONEY_A0;
 234       break;
 235    case CHIP_FIJI:
 236       ws->family = FAMILY_VI;
 237       ws->rev_id = VI_FIJI_P_A0;
 238       break;
 239    default:
 240       fprintf(stderr, "amdgpu: Unknown family.\n");
 241       goto fail;
 242    }
 243
 244    ws->addrlib = amdgpu_addr_create(ws);
 245    if (!ws->addrlib) {
 246       fprintf(stderr, "amdgpu: Cannot create addrlib.\n");
 247       goto fail;
 248    }
 249
 250    /* Set hardware information. */
 251    ws->info.gart_size = gtt.heap_size;
 252    ws->info.vram_size = vram.heap_size;
 253    /* convert the shader clock from KHz to MHz */
 254    ws->info.max_sclk = ws->amdinfo.max_engine_clk / 1000;
 255    ws->info.max_se = ws->amdinfo.num_shader_engines;
 256    ws->info.max_sh_per_se = ws->amdinfo.num_shader_arrays_per_engine;
 257    ws->info.has_uvd = uvd.available_rings != 0;
 258    ws->info.vce_fw_version =
 259          vce.available_rings ? vce_version : 0;
 260    ws->info.has_userptr = TRUE;
 261    ws->info.r600_num_backends = ws->amdinfo.rb_pipes;
 262    ws->info.r600_clock_crystal_freq = ws->amdinfo.gpu_counter_freq;
 263    ws->info.r600_tiling_config = r600_get_gb_tiling_config(&ws->amdinfo);
 264    ws->info.r600_num_tile_pipes = cik_get_num_tile_pipes(&ws->amdinfo);
 265    ws->info.r600_max_pipes = ws->amdinfo.max_quad_shader_pipes; /* TODO: is this correct? */
 266    ws->info.r600_virtual_address = TRUE;
 267    ws->info.r600_has_dma = dma.available_rings != 0;
 268
 269    /* Guess what the maximum compute unit number is by looking at the mask
 270     * of enabled CUs.
 271     */
 272    for (i = 0; i < ws->info.max_se; i++)
 273       for (j = 0; j < ws->info.max_sh_per_se; j++) {
 274          unsigned max = util_last_bit(ws->amdinfo.cu_bitmap[i][j]);
 275
 276          if (ws->info.max_compute_units < max)
 277             ws->info.max_compute_units = max;
 278       }
 279    ws->info.max_compute_units *= ws->info.max_se * ws->info.max_sh_per_se;
 280
 281    memcpy(ws->info.si_tile_mode_array, ws->amdinfo.gb_tile_mode,
 282           sizeof(ws->amdinfo.gb_tile_mode));
 283    ws->info.si_tile_mode_array_valid = TRUE;
 284    ws->info.si_backend_enabled_mask = ws->amdinfo.enabled_rb_pipes_mask;
 285
 286    memcpy(ws->info.cik_macrotile_mode_array, ws->amdinfo.gb_macro_tile_mode,
 287           sizeof(ws->amdinfo.gb_macro_tile_mode));
 288    ws->info.cik_macrotile_mode_array_valid = TRUE;
 289
 290    ws->gart_page_size = alignment_info.size_remote;
 291
 292    return TRUE;
 293
 294 fail:
 295    if (ws->addrlib)
 296       AddrDestroy(ws->addrlib);
 297    amdgpu_device_deinitialize(ws->dev);
 298    ws->dev = NULL;
 299    return FALSE;
 300 }
 301
 302 static void amdgpu_winsys_destroy(struct radeon_winsys *rws)
 303 {
 304    struct amdgpu_winsys *ws = (struct amdgpu_winsys*)rws;
 305
 306    pipe_mutex_destroy(ws->bo_fence_lock);
 307    pb_cache_deinit(&ws->bo_cache);
 308    AddrDestroy(ws->addrlib);
 309    amdgpu_device_deinitialize(ws->dev);
 310    FREE(rws);
 311 }
 312
 313 static void amdgpu_winsys_query_info(struct radeon_winsys *rws,
 314                                      struct radeon_info *info)
 315 {
 316    *info = ((struct amdgpu_winsys *)rws)->info;
 317 }
 318
 319 static boolean amdgpu_cs_request_feature(struct radeon_winsys_cs *rcs,
 320                                          enum radeon_feature_id fid,
 321                                          boolean enable)
 322 {
 323    return FALSE;
 324 }
 325
 326 static uint64_t amdgpu_query_value(struct radeon_winsys *rws,
 327                                    enum radeon_value_id value)
 328 {
 329    struct amdgpu_winsys *ws = (struct amdgpu_winsys*)rws;
 330    struct amdgpu_heap_info heap;
 331    uint64_t retval = 0;
 332
 333    switch (value) {
 334    case RADEON_REQUESTED_VRAM_MEMORY:
 335       return ws->allocated_vram;
 336    case RADEON_REQUESTED_GTT_MEMORY:
 337       return ws->allocated_gtt;
 338    case RADEON_BUFFER_WAIT_TIME_NS:
 339       return ws->buffer_wait_time;
 340    case RADEON_TIMESTAMP:
 341       amdgpu_query_info(ws->dev, AMDGPU_INFO_TIMESTAMP, 8, &retval);
 342       return retval;
 343    case RADEON_NUM_CS_FLUSHES:
 344       return ws->num_cs_flushes;
 345    case RADEON_NUM_BYTES_MOVED:
 346       amdgpu_query_info(ws->dev, AMDGPU_INFO_NUM_BYTES_MOVED, 8, &retval);
 347       return retval;
 348    case RADEON_VRAM_USAGE:
 349       amdgpu_query_heap_info(ws->dev, AMDGPU_GEM_DOMAIN_VRAM, 0, &heap);
 350       return heap.heap_usage;
 351    case RADEON_GTT_USAGE:
 352       amdgpu_query_heap_info(ws->dev, AMDGPU_GEM_DOMAIN_GTT, 0, &heap);
 353       return heap.heap_usage;
 354    case RADEON_GPU_TEMPERATURE:
 355    case RADEON_CURRENT_SCLK:
 356    case RADEON_CURRENT_MCLK:
 357       return 0;
 358    case RADEON_GPU_RESET_COUNTER:
 359       assert(0);
 360       return 0;
 361    }
 362    return 0;
 363 }
 364
 365 static bool amdgpu_read_registers(struct radeon_winsys *rws,
 366                                   unsigned reg_offset,
 367                                   unsigned num_registers, uint32_t *out)
 368 {
 369    struct amdgpu_winsys *ws = (struct amdgpu_winsys*)rws;
 370
 371    return amdgpu_read_mm_registers(ws->dev, reg_offset / 4, num_registers,
 372                                    0xffffffff, 0, out) == 0;
 373 }
 374
 375 static unsigned hash_dev(void *key)
 376 {
 377 #if defined(PIPE_ARCH_X86_64)
 378    return pointer_to_intptr(key) ^ (pointer_to_intptr(key) >> 32);
 379 #else
 380    return pointer_to_intptr(key);
 381 #endif
 382 }
 383
 384 static int compare_dev(void *key1, void *key2)
 385 {
 386    return key1 != key2;
 387 }
 388
 389 static bool amdgpu_winsys_unref(struct radeon_winsys *ws)
 390 {
 391    struct amdgpu_winsys *rws = (struct amdgpu_winsys*)ws;
 392    bool destroy;
 393
 394    /* When the reference counter drops to zero, remove the device pointer
 395     * from the table.
 396     * This must happen while the mutex is locked, so that
 397     * amdgpu_winsys_create in another thread doesn't get the winsys
 398     * from the table when the counter drops to 0. */
 399    pipe_mutex_lock(dev_tab_mutex);
 400
 401    destroy = pipe_reference(&rws->reference, NULL);
 402    if (destroy && dev_tab)
 403       util_hash_table_remove(dev_tab, rws->dev);
 404
 405    pipe_mutex_unlock(dev_tab_mutex);
 406    return destroy;
 407 }
 408
 409 PUBLIC struct radeon_winsys *
 410 amdgpu_winsys_create(int fd, radeon_screen_create_t screen_create)
 411 {
 412    struct amdgpu_winsys *ws;
 413    drmVersionPtr version = drmGetVersion(fd);
 414    amdgpu_device_handle dev;
 415    uint32_t drm_major, drm_minor, r;
 416
 417    /* The DRM driver version of amdgpu is 3.x.x. */
 418    if (version->version_major != 3) {
 419       drmFreeVersion(version);
 420       return NULL;
 421    }
 422    drmFreeVersion(version);
 423
 424    /* Look up the winsys from the dev table. */
 425    pipe_mutex_lock(dev_tab_mutex);
 426    if (!dev_tab)
 427       dev_tab = util_hash_table_create(hash_dev, compare_dev);
 428
 429    /* Initialize the amdgpu device. This should always return the same pointer
 430     * for the same fd. */
 431    r = amdgpu_device_initialize(fd, &drm_major, &drm_minor, &dev);
 432    if (r) {
 433       pipe_mutex_unlock(dev_tab_mutex);
 434       fprintf(stderr, "amdgpu: amdgpu_device_initialize failed.\n");
 435       return NULL;
 436    }
 437
 438    /* Lookup a winsys if we have already created one for this device. */
 439    ws = util_hash_table_get(dev_tab, dev);
 440    if (ws) {
 441       pipe_reference(NULL, &ws->reference);
 442       pipe_mutex_unlock(dev_tab_mutex);
 443       return &ws->base;
 444    }
 445
 446    /* Create a new winsys. */
 447    ws = CALLOC_STRUCT(amdgpu_winsys);
 448    if (!ws) {
 449       pipe_mutex_unlock(dev_tab_mutex);
 450       return NULL;
 451    }
 452
 453    ws->dev = dev;
 454    ws->info.drm_major = drm_major;
 455    ws->info.drm_minor = drm_minor;
 456
 457    if (!do_winsys_init(ws))
 458       goto fail;
 459
 460    /* Create managers. */
 461    pb_cache_init(&ws->bo_cache, 500000, 2.0f, 0,
 462                  (ws->info.vram_size + ws->info.gart_size) / 8,
 463                  amdgpu_bo_destroy, amdgpu_bo_can_reclaim);
 464
 465    /* init reference */
 466    pipe_reference_init(&ws->reference, 1);
 467
 468    /* Set functions. */
 469    ws->base.unref = amdgpu_winsys_unref;
 470    ws->base.destroy = amdgpu_winsys_destroy;
 471    ws->base.query_info = amdgpu_winsys_query_info;
 472    ws->base.cs_request_feature = amdgpu_cs_request_feature;
 473    ws->base.query_value = amdgpu_query_value;
 474    ws->base.read_registers = amdgpu_read_registers;
 475
 476    amdgpu_bo_init_functions(ws);
 477    amdgpu_cs_init_functions(ws);
 478    amdgpu_surface_init_functions(ws);
 479
 480    pipe_mutex_init(ws->bo_fence_lock);
 481
 482    /* Create the screen at the end. The winsys must be initialized
 483     * completely.
 484     *
 485     * Alternatively, we could create the screen based on "ws->gen"
 486     * and link all drivers into one binary blob. */
 487    ws->base.screen = screen_create(&ws->base);
 488    if (!ws->base.screen) {
 489       amdgpu_winsys_destroy(&ws->base);
 490       pipe_mutex_unlock(dev_tab_mutex);
 491       return NULL;
 492    }
 493
 494    util_hash_table_set(dev_tab, dev, ws);
 495
 496    /* We must unlock the mutex once the winsys is fully initialized, so that
 497     * other threads attempting to create the winsys from the same fd will
 498     * get a fully initialized winsys and not just half-way initialized. */
 499    pipe_mutex_unlock(dev_tab_mutex);
 500
 501    return &ws->base;
 502
 503 fail:
 504    pipe_mutex_unlock(dev_tab_mutex);
 505    pb_cache_deinit(&ws->bo_cache);
 506    FREE(ws);
 507    return NULL;
 508 }