2 * Copyright © 2009 Corbin Simpson <MostAwesomeDude@gmail.com>
3 * Copyright © 2009 Joakim Sindholt <opensource@zhasha.com>
4 * Copyright © 2011 Marek Olšák <maraeo@gmail.com>
5 * Copyright © 2015 Advanced Micro Devices, Inc.
8 * Permission is hereby granted, free of charge, to any person obtaining
9 * a copy of this software and associated documentation files (the
10 * "Software"), to deal in the Software without restriction, including
11 * without limitation the rights to use, copy, modify, merge, publish,
12 * distribute, sub license, and/or sell copies of the Software, and to
13 * permit persons to whom the Software is furnished to do so, subject to
14 * the following conditions:
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
17 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
18 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
19 * NON-INFRINGEMENT. IN NO EVENT SHALL THE COPYRIGHT HOLDERS, AUTHORS
20 * AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
21 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
22 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
23 * USE OR OTHER DEALINGS IN THE SOFTWARE.
25 * The above copyright notice and this permission notice (including the
26 * next paragraph) shall be included in all copies or substantial portions
31 * Marek Olšák <maraeo@gmail.com>
34 #include "amdgpu_cs.h"
35 #include "amdgpu_public.h"
37 #include "util/u_hash_table.h"
38 #include <amdgpu_drm.h>
42 #include "amd/common/amdgpu_id.h"
44 #define CIK_TILE_MODE_COLOR_2D 14
46 #define CIK__GB_TILE_MODE__PIPE_CONFIG(x) (((x) >> 6) & 0x1f)
47 #define CIK__PIPE_CONFIG__ADDR_SURF_P2 0
48 #define CIK__PIPE_CONFIG__ADDR_SURF_P4_8x16 4
49 #define CIK__PIPE_CONFIG__ADDR_SURF_P4_16x16 5
50 #define CIK__PIPE_CONFIG__ADDR_SURF_P4_16x32 6
51 #define CIK__PIPE_CONFIG__ADDR_SURF_P4_32x32 7
52 #define CIK__PIPE_CONFIG__ADDR_SURF_P8_16x16_8x16 8
53 #define CIK__PIPE_CONFIG__ADDR_SURF_P8_16x32_8x16 9
54 #define CIK__PIPE_CONFIG__ADDR_SURF_P8_32x32_8x16 10
55 #define CIK__PIPE_CONFIG__ADDR_SURF_P8_16x32_16x16 11
56 #define CIK__PIPE_CONFIG__ADDR_SURF_P8_32x32_16x16 12
57 #define CIK__PIPE_CONFIG__ADDR_SURF_P8_32x32_16x32 13
58 #define CIK__PIPE_CONFIG__ADDR_SURF_P8_32x64_32x32 14
59 #define CIK__PIPE_CONFIG__ADDR_SURF_P16_32X32_8X16 16
60 #define CIK__PIPE_CONFIG__ADDR_SURF_P16_32X32_16X16 17
62 #ifndef AMDGPU_INFO_NUM_EVICTIONS
63 #define AMDGPU_INFO_NUM_EVICTIONS 0x18
66 static struct util_hash_table
*dev_tab
= NULL
;
67 pipe_static_mutex(dev_tab_mutex
);
69 static unsigned cik_get_num_tile_pipes(struct amdgpu_gpu_info
*info
)
71 unsigned mode2d
= info
->gb_tile_mode
[CIK_TILE_MODE_COLOR_2D
];
73 switch (CIK__GB_TILE_MODE__PIPE_CONFIG(mode2d
)) {
74 case CIK__PIPE_CONFIG__ADDR_SURF_P2
:
76 case CIK__PIPE_CONFIG__ADDR_SURF_P4_8x16
:
77 case CIK__PIPE_CONFIG__ADDR_SURF_P4_16x16
:
78 case CIK__PIPE_CONFIG__ADDR_SURF_P4_16x32
:
79 case CIK__PIPE_CONFIG__ADDR_SURF_P4_32x32
:
81 case CIK__PIPE_CONFIG__ADDR_SURF_P8_16x16_8x16
:
82 case CIK__PIPE_CONFIG__ADDR_SURF_P8_16x32_8x16
:
83 case CIK__PIPE_CONFIG__ADDR_SURF_P8_32x32_8x16
:
84 case CIK__PIPE_CONFIG__ADDR_SURF_P8_16x32_16x16
:
85 case CIK__PIPE_CONFIG__ADDR_SURF_P8_32x32_16x16
:
86 case CIK__PIPE_CONFIG__ADDR_SURF_P8_32x32_16x32
:
87 case CIK__PIPE_CONFIG__ADDR_SURF_P8_32x64_32x32
:
89 case CIK__PIPE_CONFIG__ADDR_SURF_P16_32X32_8X16
:
90 case CIK__PIPE_CONFIG__ADDR_SURF_P16_32X32_16X16
:
93 fprintf(stderr
, "Invalid CIK pipe configuration, assuming P2\n");
94 assert(!"this should never occur");
99 /* Helper function to do the ioctls needed for setup and init. */
100 static bool do_winsys_init(struct amdgpu_winsys
*ws
, int fd
)
102 struct amdgpu_buffer_size_alignments alignment_info
= {};
103 struct amdgpu_heap_info vram
, gtt
;
104 struct drm_amdgpu_info_hw_ip dma
= {}, uvd
= {}, vce
= {};
105 uint32_t vce_version
= 0, vce_feature
= 0, uvd_version
= 0, uvd_feature
= 0;
106 uint32_t unused_feature
;
108 drmDevicePtr devinfo
;
111 r
= drmGetDevice(fd
, &devinfo
);
113 fprintf(stderr
, "amdgpu: drmGetDevice failed.\n");
116 ws
->info
.pci_domain
= devinfo
->businfo
.pci
->domain
;
117 ws
->info
.pci_bus
= devinfo
->businfo
.pci
->bus
;
118 ws
->info
.pci_dev
= devinfo
->businfo
.pci
->dev
;
119 ws
->info
.pci_func
= devinfo
->businfo
.pci
->func
;
120 drmFreeDevice(&devinfo
);
122 /* Query hardware and driver information. */
123 r
= amdgpu_query_gpu_info(ws
->dev
, &ws
->amdinfo
);
125 fprintf(stderr
, "amdgpu: amdgpu_query_gpu_info failed.\n");
129 r
= amdgpu_query_buffer_size_alignment(ws
->dev
, &alignment_info
);
131 fprintf(stderr
, "amdgpu: amdgpu_query_buffer_size_alignment failed.\n");
135 r
= amdgpu_query_heap_info(ws
->dev
, AMDGPU_GEM_DOMAIN_VRAM
, 0, &vram
);
137 fprintf(stderr
, "amdgpu: amdgpu_query_heap_info(vram) failed.\n");
141 r
= amdgpu_query_heap_info(ws
->dev
, AMDGPU_GEM_DOMAIN_GTT
, 0, >t
);
143 fprintf(stderr
, "amdgpu: amdgpu_query_heap_info(gtt) failed.\n");
147 r
= amdgpu_query_hw_ip_info(ws
->dev
, AMDGPU_HW_IP_DMA
, 0, &dma
);
149 fprintf(stderr
, "amdgpu: amdgpu_query_hw_ip_info(dma) failed.\n");
153 r
= amdgpu_query_hw_ip_info(ws
->dev
, AMDGPU_HW_IP_UVD
, 0, &uvd
);
155 fprintf(stderr
, "amdgpu: amdgpu_query_hw_ip_info(uvd) failed.\n");
159 r
= amdgpu_query_firmware_version(ws
->dev
, AMDGPU_INFO_FW_GFX_ME
, 0, 0,
160 &ws
->info
.me_fw_version
, &unused_feature
);
162 fprintf(stderr
, "amdgpu: amdgpu_query_firmware_version(me) failed.\n");
166 r
= amdgpu_query_firmware_version(ws
->dev
, AMDGPU_INFO_FW_GFX_PFP
, 0, 0,
167 &ws
->info
.pfp_fw_version
, &unused_feature
);
169 fprintf(stderr
, "amdgpu: amdgpu_query_firmware_version(pfp) failed.\n");
173 r
= amdgpu_query_firmware_version(ws
->dev
, AMDGPU_INFO_FW_GFX_CE
, 0, 0,
174 &ws
->info
.ce_fw_version
, &unused_feature
);
176 fprintf(stderr
, "amdgpu: amdgpu_query_firmware_version(ce) failed.\n");
180 r
= amdgpu_query_firmware_version(ws
->dev
, AMDGPU_INFO_FW_UVD
, 0, 0,
181 &uvd_version
, &uvd_feature
);
183 fprintf(stderr
, "amdgpu: amdgpu_query_firmware_version(uvd) failed.\n");
187 r
= amdgpu_query_hw_ip_info(ws
->dev
, AMDGPU_HW_IP_VCE
, 0, &vce
);
189 fprintf(stderr
, "amdgpu: amdgpu_query_hw_ip_info(vce) failed.\n");
193 r
= amdgpu_query_firmware_version(ws
->dev
, AMDGPU_INFO_FW_VCE
, 0, 0,
194 &vce_version
, &vce_feature
);
196 fprintf(stderr
, "amdgpu: amdgpu_query_firmware_version(vce) failed.\n");
200 /* Set chip identification. */
201 ws
->info
.pci_id
= ws
->amdinfo
.asic_id
; /* TODO: is this correct? */
202 ws
->info
.vce_harvest_config
= ws
->amdinfo
.vce_harvest_config
;
204 switch (ws
->info
.pci_id
) {
205 #define CHIPSET(pci_id, name, cfamily) case pci_id: ws->info.family = CHIP_##cfamily; break;
206 #include "pci_ids/radeonsi_pci_ids.h"
210 fprintf(stderr
, "amdgpu: Invalid PCI ID.\n");
214 if (ws
->info
.family
>= CHIP_TONGA
)
215 ws
->info
.chip_class
= VI
;
216 else if (ws
->info
.family
>= CHIP_BONAIRE
)
217 ws
->info
.chip_class
= CIK
;
218 else if (ws
->info
.family
>= CHIP_TAHITI
)
219 ws
->info
.chip_class
= SI
;
221 fprintf(stderr
, "amdgpu: Unknown family.\n");
225 /* LLVM 3.6.1 is required for VI. */
226 if (ws
->info
.chip_class
>= VI
&&
227 HAVE_LLVM
== 0x0306 && MESA_LLVM_VERSION_PATCH
< 1) {
228 fprintf(stderr
, "amdgpu: LLVM 3.6.1 is required, got LLVM %i.%i.%i\n",
229 HAVE_LLVM
>> 8, HAVE_LLVM
& 255, MESA_LLVM_VERSION_PATCH
);
233 /* family and rev_id are for addrlib */
234 switch (ws
->info
.family
) {
236 ws
->family
= FAMILY_SI
;
237 ws
->rev_id
= SI_TAHITI_P_A0
;
240 ws
->family
= FAMILY_SI
;
241 ws
->rev_id
= SI_PITCAIRN_PM_A0
;
244 ws
->family
= FAMILY_SI
;
245 ws
->rev_id
= SI_CAPEVERDE_M_A0
;
248 ws
->family
= FAMILY_SI
;
249 ws
->rev_id
= SI_OLAND_M_A0
;
252 ws
->family
= FAMILY_SI
;
253 ws
->rev_id
= SI_HAINAN_V_A0
;
256 ws
->family
= FAMILY_CI
;
257 ws
->rev_id
= CI_BONAIRE_M_A0
;
260 ws
->family
= FAMILY_KV
;
261 ws
->rev_id
= KV_SPECTRE_A0
;
264 ws
->family
= FAMILY_KV
;
265 ws
->rev_id
= KB_KALINDI_A0
;
268 ws
->family
= FAMILY_CI
;
269 ws
->rev_id
= CI_HAWAII_P_A0
;
272 ws
->family
= FAMILY_KV
;
273 ws
->rev_id
= ML_GODAVARI_A0
;
276 ws
->family
= FAMILY_VI
;
277 ws
->rev_id
= VI_TONGA_P_A0
;
280 ws
->family
= FAMILY_VI
;
281 ws
->rev_id
= VI_ICELAND_M_A0
;
284 ws
->family
= FAMILY_CZ
;
285 ws
->rev_id
= CARRIZO_A0
;
288 ws
->family
= FAMILY_CZ
;
289 ws
->rev_id
= STONEY_A0
;
292 ws
->family
= FAMILY_VI
;
293 ws
->rev_id
= VI_FIJI_P_A0
;
296 ws
->family
= FAMILY_VI
;
297 ws
->rev_id
= VI_POLARIS10_P_A0
;
300 ws
->family
= FAMILY_VI
;
301 ws
->rev_id
= VI_POLARIS11_M_A0
;
304 ws
->family
= FAMILY_VI
;
305 ws
->rev_id
= VI_POLARIS12_V_A0
;
308 fprintf(stderr
, "amdgpu: Unknown family.\n");
312 ws
->addrlib
= amdgpu_addr_create(ws
);
314 fprintf(stderr
, "amdgpu: Cannot create addrlib.\n");
318 /* Set which chips have dedicated VRAM. */
319 ws
->info
.has_dedicated_vram
=
320 !(ws
->amdinfo
.ids_flags
& AMDGPU_IDS_FLAGS_FUSION
);
322 /* Set hardware information. */
323 ws
->info
.gart_size
= gtt
.heap_size
;
324 ws
->info
.vram_size
= vram
.heap_size
;
325 /* The kernel can split large buffers, so we can do large allocations. */
326 ws
->info
.max_alloc_size
= MAX2(ws
->info
.vram_size
, ws
->info
.gart_size
) * 0.9;
327 /* convert the shader clock from KHz to MHz */
328 ws
->info
.max_shader_clock
= ws
->amdinfo
.max_engine_clk
/ 1000;
329 ws
->info
.max_se
= ws
->amdinfo
.num_shader_engines
;
330 ws
->info
.max_sh_per_se
= ws
->amdinfo
.num_shader_arrays_per_engine
;
331 ws
->info
.has_uvd
= uvd
.available_rings
!= 0;
332 ws
->info
.uvd_fw_version
=
333 uvd
.available_rings
? uvd_version
: 0;
334 ws
->info
.vce_fw_version
=
335 vce
.available_rings
? vce_version
: 0;
336 ws
->info
.has_userptr
= true;
337 ws
->info
.num_render_backends
= ws
->amdinfo
.rb_pipes
;
338 ws
->info
.clock_crystal_freq
= ws
->amdinfo
.gpu_counter_freq
;
339 ws
->info
.num_tile_pipes
= cik_get_num_tile_pipes(&ws
->amdinfo
);
340 ws
->info
.pipe_interleave_bytes
= 256 << ((ws
->amdinfo
.gb_addr_cfg
>> 4) & 0x7);
341 ws
->info
.has_virtual_memory
= true;
342 ws
->info
.has_sdma
= dma
.available_rings
!= 0;
344 /* Get the number of good compute units. */
345 ws
->info
.num_good_compute_units
= 0;
346 for (i
= 0; i
< ws
->info
.max_se
; i
++)
347 for (j
= 0; j
< ws
->info
.max_sh_per_se
; j
++)
348 ws
->info
.num_good_compute_units
+=
349 util_bitcount(ws
->amdinfo
.cu_bitmap
[i
][j
]);
351 memcpy(ws
->info
.si_tile_mode_array
, ws
->amdinfo
.gb_tile_mode
,
352 sizeof(ws
->amdinfo
.gb_tile_mode
));
353 ws
->info
.enabled_rb_mask
= ws
->amdinfo
.enabled_rb_pipes_mask
;
355 memcpy(ws
->info
.cik_macrotile_mode_array
, ws
->amdinfo
.gb_macro_tile_mode
,
356 sizeof(ws
->amdinfo
.gb_macro_tile_mode
));
358 ws
->info
.gart_page_size
= alignment_info
.size_remote
;
360 if (ws
->info
.chip_class
== SI
)
361 ws
->info
.gfx_ib_pad_with_type2
= TRUE
;
363 ws
->check_vm
= strstr(debug_get_option("R600_DEBUG", ""), "check_vm") != NULL
;
369 AddrDestroy(ws
->addrlib
);
370 amdgpu_device_deinitialize(ws
->dev
);
375 static void do_winsys_deinit(struct amdgpu_winsys
*ws
)
377 AddrDestroy(ws
->addrlib
);
378 amdgpu_device_deinitialize(ws
->dev
);
381 static void amdgpu_winsys_destroy(struct radeon_winsys
*rws
)
383 struct amdgpu_winsys
*ws
= (struct amdgpu_winsys
*)rws
;
385 if (util_queue_is_initialized(&ws
->cs_queue
))
386 util_queue_destroy(&ws
->cs_queue
);
388 pipe_mutex_destroy(ws
->bo_fence_lock
);
389 pb_slabs_deinit(&ws
->bo_slabs
);
390 pb_cache_deinit(&ws
->bo_cache
);
391 pipe_mutex_destroy(ws
->global_bo_list_lock
);
392 do_winsys_deinit(ws
);
396 static void amdgpu_winsys_query_info(struct radeon_winsys
*rws
,
397 struct radeon_info
*info
)
399 *info
= ((struct amdgpu_winsys
*)rws
)->info
;
402 static bool amdgpu_cs_request_feature(struct radeon_winsys_cs
*rcs
,
403 enum radeon_feature_id fid
,
409 static uint64_t amdgpu_query_value(struct radeon_winsys
*rws
,
410 enum radeon_value_id value
)
412 struct amdgpu_winsys
*ws
= (struct amdgpu_winsys
*)rws
;
413 struct amdgpu_heap_info heap
;
417 case RADEON_REQUESTED_VRAM_MEMORY
:
418 return ws
->allocated_vram
;
419 case RADEON_REQUESTED_GTT_MEMORY
:
420 return ws
->allocated_gtt
;
421 case RADEON_MAPPED_VRAM
:
422 return ws
->mapped_vram
;
423 case RADEON_MAPPED_GTT
:
424 return ws
->mapped_gtt
;
425 case RADEON_BUFFER_WAIT_TIME_NS
:
426 return ws
->buffer_wait_time
;
427 case RADEON_TIMESTAMP
:
428 amdgpu_query_info(ws
->dev
, AMDGPU_INFO_TIMESTAMP
, 8, &retval
);
430 case RADEON_NUM_CS_FLUSHES
:
431 return ws
->num_cs_flushes
;
432 case RADEON_NUM_BYTES_MOVED
:
433 amdgpu_query_info(ws
->dev
, AMDGPU_INFO_NUM_BYTES_MOVED
, 8, &retval
);
435 case RADEON_NUM_EVICTIONS
:
436 amdgpu_query_info(ws
->dev
, AMDGPU_INFO_NUM_EVICTIONS
, 8, &retval
);
438 case RADEON_VRAM_USAGE
:
439 amdgpu_query_heap_info(ws
->dev
, AMDGPU_GEM_DOMAIN_VRAM
, 0, &heap
);
440 return heap
.heap_usage
;
441 case RADEON_GTT_USAGE
:
442 amdgpu_query_heap_info(ws
->dev
, AMDGPU_GEM_DOMAIN_GTT
, 0, &heap
);
443 return heap
.heap_usage
;
444 case RADEON_GPU_TEMPERATURE
:
445 case RADEON_CURRENT_SCLK
:
446 case RADEON_CURRENT_MCLK
:
448 case RADEON_GPU_RESET_COUNTER
:
455 static bool amdgpu_read_registers(struct radeon_winsys
*rws
,
457 unsigned num_registers
, uint32_t *out
)
459 struct amdgpu_winsys
*ws
= (struct amdgpu_winsys
*)rws
;
461 return amdgpu_read_mm_registers(ws
->dev
, reg_offset
/ 4, num_registers
,
462 0xffffffff, 0, out
) == 0;
465 static unsigned hash_dev(void *key
)
467 #if defined(PIPE_ARCH_X86_64)
468 return pointer_to_intptr(key
) ^ (pointer_to_intptr(key
) >> 32);
470 return pointer_to_intptr(key
);
474 static int compare_dev(void *key1
, void *key2
)
479 DEBUG_GET_ONCE_BOOL_OPTION(thread
, "RADEON_THREAD", true)
481 static bool amdgpu_winsys_unref(struct radeon_winsys
*rws
)
483 struct amdgpu_winsys
*ws
= (struct amdgpu_winsys
*)rws
;
486 /* When the reference counter drops to zero, remove the device pointer
488 * This must happen while the mutex is locked, so that
489 * amdgpu_winsys_create in another thread doesn't get the winsys
490 * from the table when the counter drops to 0. */
491 pipe_mutex_lock(dev_tab_mutex
);
493 destroy
= pipe_reference(&ws
->reference
, NULL
);
494 if (destroy
&& dev_tab
)
495 util_hash_table_remove(dev_tab
, ws
->dev
);
497 pipe_mutex_unlock(dev_tab_mutex
);
501 PUBLIC
struct radeon_winsys
*
502 amdgpu_winsys_create(int fd
, radeon_screen_create_t screen_create
)
504 struct amdgpu_winsys
*ws
;
505 drmVersionPtr version
= drmGetVersion(fd
);
506 amdgpu_device_handle dev
;
507 uint32_t drm_major
, drm_minor
, r
;
509 /* The DRM driver version of amdgpu is 3.x.x. */
510 if (version
->version_major
!= 3) {
511 drmFreeVersion(version
);
514 drmFreeVersion(version
);
516 /* Look up the winsys from the dev table. */
517 pipe_mutex_lock(dev_tab_mutex
);
519 dev_tab
= util_hash_table_create(hash_dev
, compare_dev
);
521 /* Initialize the amdgpu device. This should always return the same pointer
522 * for the same fd. */
523 r
= amdgpu_device_initialize(fd
, &drm_major
, &drm_minor
, &dev
);
525 pipe_mutex_unlock(dev_tab_mutex
);
526 fprintf(stderr
, "amdgpu: amdgpu_device_initialize failed.\n");
530 /* Lookup a winsys if we have already created one for this device. */
531 ws
= util_hash_table_get(dev_tab
, dev
);
533 pipe_reference(NULL
, &ws
->reference
);
534 pipe_mutex_unlock(dev_tab_mutex
);
538 /* Create a new winsys. */
539 ws
= CALLOC_STRUCT(amdgpu_winsys
);
544 ws
->info
.drm_major
= drm_major
;
545 ws
->info
.drm_minor
= drm_minor
;
547 if (!do_winsys_init(ws
, fd
))
550 /* Create managers. */
551 pb_cache_init(&ws
->bo_cache
, 500000, ws
->check_vm
? 1.0f
: 2.0f
, 0,
552 (ws
->info
.vram_size
+ ws
->info
.gart_size
) / 8,
553 amdgpu_bo_destroy
, amdgpu_bo_can_reclaim
);
555 if (!pb_slabs_init(&ws
->bo_slabs
,
556 AMDGPU_SLAB_MIN_SIZE_LOG2
, AMDGPU_SLAB_MAX_SIZE_LOG2
,
557 12, /* number of heaps (domain/flags combinations) */
559 amdgpu_bo_can_reclaim_slab
,
560 amdgpu_bo_slab_alloc
,
561 amdgpu_bo_slab_free
))
564 ws
->info
.min_alloc_size
= 1 << AMDGPU_SLAB_MIN_SIZE_LOG2
;
567 pipe_reference_init(&ws
->reference
, 1);
570 ws
->base
.unref
= amdgpu_winsys_unref
;
571 ws
->base
.destroy
= amdgpu_winsys_destroy
;
572 ws
->base
.query_info
= amdgpu_winsys_query_info
;
573 ws
->base
.cs_request_feature
= amdgpu_cs_request_feature
;
574 ws
->base
.query_value
= amdgpu_query_value
;
575 ws
->base
.read_registers
= amdgpu_read_registers
;
577 amdgpu_bo_init_functions(ws
);
578 amdgpu_cs_init_functions(ws
);
579 amdgpu_surface_init_functions(ws
);
581 LIST_INITHEAD(&ws
->global_bo_list
);
582 pipe_mutex_init(ws
->global_bo_list_lock
);
583 pipe_mutex_init(ws
->bo_fence_lock
);
585 if (sysconf(_SC_NPROCESSORS_ONLN
) > 1 && debug_get_option_thread())
586 util_queue_init(&ws
->cs_queue
, "amdgpu_cs", 8, 1);
588 /* Create the screen at the end. The winsys must be initialized
591 * Alternatively, we could create the screen based on "ws->gen"
592 * and link all drivers into one binary blob. */
593 ws
->base
.screen
= screen_create(&ws
->base
);
594 if (!ws
->base
.screen
) {
595 amdgpu_winsys_destroy(&ws
->base
);
596 pipe_mutex_unlock(dev_tab_mutex
);
600 util_hash_table_set(dev_tab
, dev
, ws
);
602 /* We must unlock the mutex once the winsys is fully initialized, so that
603 * other threads attempting to create the winsys from the same fd will
604 * get a fully initialized winsys and not just half-way initialized. */
605 pipe_mutex_unlock(dev_tab_mutex
);
610 pb_cache_deinit(&ws
->bo_cache
);
611 do_winsys_deinit(ws
);
615 pipe_mutex_unlock(dev_tab_mutex
);