src/gallium/winsys/amdgpu/drm/amdgpu_winsys.c

   1 /*
   2  * Copyright © 2009 Corbin Simpson <MostAwesomeDude@gmail.com>
   3  * Copyright © 2009 Joakim Sindholt <opensource@zhasha.com>
   4  * Copyright © 2011 Marek Olšák <maraeo@gmail.com>
   5  * Copyright © 2015 Advanced Micro Devices, Inc.
   6  * All Rights Reserved.
   7  *
   8  * Permission is hereby granted, free of charge, to any person obtaining
   9  * a copy of this software and associated documentation files (the
  10  * "Software"), to deal in the Software without restriction, including
  11  * without limitation the rights to use, copy, modify, merge, publish,
  12  * distribute, sub license, and/or sell copies of the Software, and to
  13  * permit persons to whom the Software is furnished to do so, subject to
  14  * the following conditions:
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  17  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
  18  * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  19  * NON-INFRINGEMENT. IN NO EVENT SHALL THE COPYRIGHT HOLDERS, AUTHORS
  20  * AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  21  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  22  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
  23  * USE OR OTHER DEALINGS IN THE SOFTWARE.
  24  *
  25  * The above copyright notice and this permission notice (including the
  26  * next paragraph) shall be included in all copies or substantial portions
  27  * of the Software.
  28  */
  29 /*
  30  * Authors:
  31  *      Marek Olšák <maraeo@gmail.com>
  32  */
  33
  34 #include "amdgpu_cs.h"
  35 #include "amdgpu_public.h"
  36
  37 #include "util/u_hash_table.h"
  38 #include <amdgpu_drm.h>
  39 #include <xf86drm.h>
  40 #include <stdio.h>
  41 #include <sys/stat.h>
  42 #include "amdgpu_id.h"
  43
  44 #define CIK_TILE_MODE_COLOR_2D                  14
  45
  46 #define CIK__GB_TILE_MODE__PIPE_CONFIG(x)        (((x) >> 6) & 0x1f)
  47 #define     CIK__PIPE_CONFIG__ADDR_SURF_P2               0
  48 #define     CIK__PIPE_CONFIG__ADDR_SURF_P4_8x16          4
  49 #define     CIK__PIPE_CONFIG__ADDR_SURF_P4_16x16         5
  50 #define     CIK__PIPE_CONFIG__ADDR_SURF_P4_16x32         6
  51 #define     CIK__PIPE_CONFIG__ADDR_SURF_P4_32x32         7
  52 #define     CIK__PIPE_CONFIG__ADDR_SURF_P8_16x16_8x16    8
  53 #define     CIK__PIPE_CONFIG__ADDR_SURF_P8_16x32_8x16    9
  54 #define     CIK__PIPE_CONFIG__ADDR_SURF_P8_32x32_8x16    10
  55 #define     CIK__PIPE_CONFIG__ADDR_SURF_P8_16x32_16x16   11
  56 #define     CIK__PIPE_CONFIG__ADDR_SURF_P8_32x32_16x16   12
  57 #define     CIK__PIPE_CONFIG__ADDR_SURF_P8_32x32_16x32   13
  58 #define     CIK__PIPE_CONFIG__ADDR_SURF_P8_32x64_32x32   14
  59 #define     CIK__PIPE_CONFIG__ADDR_SURF_P16_32X32_8X16   16
  60 #define     CIK__PIPE_CONFIG__ADDR_SURF_P16_32X32_16X16  17
  61
  62 static struct util_hash_table *dev_tab = NULL;
  63 pipe_static_mutex(dev_tab_mutex);
  64
  65 static unsigned cik_get_num_tile_pipes(struct amdgpu_gpu_info *info)
  66 {
  67    unsigned mode2d = info->gb_tile_mode[CIK_TILE_MODE_COLOR_2D];
  68
  69    switch (CIK__GB_TILE_MODE__PIPE_CONFIG(mode2d)) {
  70    case CIK__PIPE_CONFIG__ADDR_SURF_P2:
  71        return 2;
  72    case CIK__PIPE_CONFIG__ADDR_SURF_P4_8x16:
  73    case CIK__PIPE_CONFIG__ADDR_SURF_P4_16x16:
  74    case CIK__PIPE_CONFIG__ADDR_SURF_P4_16x32:
  75    case CIK__PIPE_CONFIG__ADDR_SURF_P4_32x32:
  76        return 4;
  77    case CIK__PIPE_CONFIG__ADDR_SURF_P8_16x16_8x16:
  78    case CIK__PIPE_CONFIG__ADDR_SURF_P8_16x32_8x16:
  79    case CIK__PIPE_CONFIG__ADDR_SURF_P8_32x32_8x16:
  80    case CIK__PIPE_CONFIG__ADDR_SURF_P8_16x32_16x16:
  81    case CIK__PIPE_CONFIG__ADDR_SURF_P8_32x32_16x16:
  82    case CIK__PIPE_CONFIG__ADDR_SURF_P8_32x32_16x32:
  83    case CIK__PIPE_CONFIG__ADDR_SURF_P8_32x64_32x32:
  84        return 8;
  85    case CIK__PIPE_CONFIG__ADDR_SURF_P16_32X32_8X16:
  86    case CIK__PIPE_CONFIG__ADDR_SURF_P16_32X32_16X16:
  87        return 16;
  88    default:
  89        fprintf(stderr, "Invalid CIK pipe configuration, assuming P2\n");
  90        assert(!"this should never occur");
  91        return 2;
  92    }
  93 }
  94
  95 /* Convert Sea Islands register values GB_ADDR_CFG and MC_ADDR_CFG
  96  * into GB_TILING_CONFIG register which is only present on R600-R700. */
  97 static unsigned r600_get_gb_tiling_config(struct amdgpu_gpu_info *info)
  98 {
  99    unsigned num_pipes = info->gb_addr_cfg & 0x7;
 100    unsigned num_banks = info->mc_arb_ramcfg & 0x3;
 101    unsigned pipe_interleave_bytes = (info->gb_addr_cfg >> 4) & 0x7;
 102    unsigned row_size = (info->gb_addr_cfg >> 28) & 0x3;
 103
 104    return num_pipes | (num_banks << 4) |
 105          (pipe_interleave_bytes << 8) |
 106          (row_size << 12);
 107 }
 108
 109 /* Helper function to do the ioctls needed for setup and init. */
 110 static boolean do_winsys_init(struct amdgpu_winsys *ws)
 111 {
 112    struct amdgpu_buffer_size_alignments alignment_info = {};
 113    struct amdgpu_heap_info vram, gtt;
 114    struct drm_amdgpu_info_hw_ip dma = {}, uvd = {}, vce = {};
 115    uint32_t vce_version = 0, vce_feature = 0;
 116    int r, i, j;
 117
 118    /* Query hardware and driver information. */
 119    r = amdgpu_query_gpu_info(ws->dev, &ws->amdinfo);
 120    if (r) {
 121       fprintf(stderr, "amdgpu: amdgpu_query_gpu_info failed.\n");
 122       goto fail;
 123    }
 124
 125    r = amdgpu_query_buffer_size_alignment(ws->dev, &alignment_info);
 126    if (r) {
 127       fprintf(stderr, "amdgpu: amdgpu_query_buffer_size_alignment failed.\n");
 128       goto fail;
 129    }
 130
 131    r = amdgpu_query_heap_info(ws->dev, AMDGPU_GEM_DOMAIN_VRAM, 0, &vram);
 132    if (r) {
 133       fprintf(stderr, "amdgpu: amdgpu_query_heap_info(vram) failed.\n");
 134       goto fail;
 135    }
 136
 137    r = amdgpu_query_heap_info(ws->dev, AMDGPU_GEM_DOMAIN_GTT, 0, &gtt);
 138    if (r) {
 139       fprintf(stderr, "amdgpu: amdgpu_query_heap_info(gtt) failed.\n");
 140       goto fail;
 141    }
 142
 143    r = amdgpu_query_hw_ip_info(ws->dev, AMDGPU_HW_IP_DMA, 0, &dma);
 144    if (r) {
 145       fprintf(stderr, "amdgpu: amdgpu_query_hw_ip_info(dma) failed.\n");
 146       goto fail;
 147    }
 148
 149    r = amdgpu_query_hw_ip_info(ws->dev, AMDGPU_HW_IP_UVD, 0, &uvd);
 150    if (r) {
 151       fprintf(stderr, "amdgpu: amdgpu_query_hw_ip_info(uvd) failed.\n");
 152       goto fail;
 153    }
 154
 155    r = amdgpu_query_hw_ip_info(ws->dev, AMDGPU_HW_IP_VCE, 0, &vce);
 156    if (r) {
 157       fprintf(stderr, "amdgpu: amdgpu_query_hw_ip_info(vce) failed.\n");
 158       goto fail;
 159    }
 160
 161    r = amdgpu_query_firmware_version(ws->dev, AMDGPU_INFO_FW_VCE, 0, 0,
 162                                      &vce_version, &vce_feature);
 163    if (r) {
 164       fprintf(stderr, "amdgpu: amdgpu_query_firmware_version(vce) failed.\n");
 165       goto fail;
 166    }
 167
 168    /* Set chip identification. */
 169    ws->info.pci_id = ws->amdinfo.asic_id; /* TODO: is this correct? */
 170    ws->info.vce_harvest_config = ws->amdinfo.vce_harvest_config;
 171
 172    switch (ws->info.pci_id) {
 173 #define CHIPSET(pci_id, name, cfamily) case pci_id: ws->info.family = CHIP_##cfamily; break;
 174 #include "pci_ids/radeonsi_pci_ids.h"
 175 #undef CHIPSET
 176
 177    default:
 178       fprintf(stderr, "amdgpu: Invalid PCI ID.\n");
 179       goto fail;
 180    }
 181
 182    if (ws->info.family >= CHIP_TONGA)
 183       ws->info.chip_class = VI;
 184    else if (ws->info.family >= CHIP_BONAIRE)
 185       ws->info.chip_class = CIK;
 186    else {
 187       fprintf(stderr, "amdgpu: Unknown family.\n");
 188       goto fail;
 189    }
 190
 191    /* LLVM 3.6 is required for VI. */
 192    if (ws->info.chip_class >= VI &&
 193        (HAVE_LLVM < 0x0306 ||
 194         (HAVE_LLVM == 0x0306 && MESA_LLVM_VERSION_PATCH < 1))) {
 195       fprintf(stderr, "amdgpu: LLVM 3.6.1 is required, got LLVM %i.%i.%i\n",
 196               HAVE_LLVM >> 8, HAVE_LLVM & 255, MESA_LLVM_VERSION_PATCH);
 197       goto fail;
 198    }
 199
 200    /* family and rev_id are for addrlib */
 201    switch (ws->info.family) {
 202    case CHIP_BONAIRE:
 203       ws->family = FAMILY_CI;
 204       ws->rev_id = CI_BONAIRE_M_A0;
 205       break;
 206    case CHIP_KAVERI:
 207       ws->family = FAMILY_KV;
 208       ws->rev_id = KV_SPECTRE_A0;
 209       break;
 210    case CHIP_KABINI:
 211       ws->family = FAMILY_KV;
 212       ws->rev_id = KB_KALINDI_A0;
 213       break;
 214    case CHIP_HAWAII:
 215       ws->family = FAMILY_CI;
 216       ws->rev_id = CI_HAWAII_P_A0;
 217       break;
 218    case CHIP_MULLINS:
 219       ws->family = FAMILY_KV;
 220       ws->rev_id = ML_GODAVARI_A0;
 221       break;
 222    case CHIP_TONGA:
 223       ws->family = FAMILY_VI;
 224       ws->rev_id = VI_TONGA_P_A0;
 225       break;
 226    case CHIP_ICELAND:
 227       ws->family = FAMILY_VI;
 228       ws->rev_id = VI_ICELAND_M_A0;
 229       break;
 230    case CHIP_CARRIZO:
 231       ws->family = FAMILY_CZ;
 232       ws->rev_id = CARRIZO_A0;
 233       break;
 234    case CHIP_STONEY:
 235       ws->family = FAMILY_CZ;
 236       ws->rev_id = STONEY_A0;
 237       break;
 238    case CHIP_FIJI:
 239       ws->family = FAMILY_VI;
 240       ws->rev_id = VI_FIJI_P_A0;
 241       break;
 242    default:
 243       fprintf(stderr, "amdgpu: Unknown family.\n");
 244       goto fail;
 245    }
 246
 247    ws->addrlib = amdgpu_addr_create(ws);
 248    if (!ws->addrlib) {
 249       fprintf(stderr, "amdgpu: Cannot create addrlib.\n");
 250       goto fail;
 251    }
 252
 253    /* Set hardware information. */
 254    ws->info.gart_size = gtt.heap_size;
 255    ws->info.vram_size = vram.heap_size;
 256    /* convert the shader clock from KHz to MHz */
 257    ws->info.max_shader_clock = ws->amdinfo.max_engine_clk / 1000;
 258    ws->info.max_se = ws->amdinfo.num_shader_engines;
 259    ws->info.max_sh_per_se = ws->amdinfo.num_shader_arrays_per_engine;
 260    ws->info.has_uvd = uvd.available_rings != 0;
 261    ws->info.vce_fw_version =
 262          vce.available_rings ? vce_version : 0;
 263    ws->info.has_userptr = TRUE;
 264    ws->info.num_render_backends = ws->amdinfo.rb_pipes;
 265    ws->info.clock_crystal_freq = ws->amdinfo.gpu_counter_freq;
 266    ws->info.r600_tiling_config = r600_get_gb_tiling_config(&ws->amdinfo);
 267    ws->info.num_tile_pipes = cik_get_num_tile_pipes(&ws->amdinfo);
 268    ws->info.has_virtual_memory = TRUE;
 269    ws->info.has_sdma = dma.available_rings != 0;
 270
 271    /* Get the number of good compute units. */
 272    ws->info.num_good_compute_units = 0;
 273    for (i = 0; i < ws->info.max_se; i++)
 274       for (j = 0; j < ws->info.max_sh_per_se; j++)
 275          ws->info.num_good_compute_units +=
 276             util_bitcount(ws->amdinfo.cu_bitmap[i][j]);
 277
 278    memcpy(ws->info.si_tile_mode_array, ws->amdinfo.gb_tile_mode,
 279           sizeof(ws->amdinfo.gb_tile_mode));
 280    ws->info.si_tile_mode_array_valid = TRUE;
 281    ws->info.enabled_rb_mask = ws->amdinfo.enabled_rb_pipes_mask;
 282
 283    memcpy(ws->info.cik_macrotile_mode_array, ws->amdinfo.gb_macro_tile_mode,
 284           sizeof(ws->amdinfo.gb_macro_tile_mode));
 285    ws->info.cik_macrotile_mode_array_valid = TRUE;
 286
 287    ws->gart_page_size = alignment_info.size_remote;
 288
 289    return TRUE;
 290
 291 fail:
 292    if (ws->addrlib)
 293       AddrDestroy(ws->addrlib);
 294    amdgpu_device_deinitialize(ws->dev);
 295    ws->dev = NULL;
 296    return FALSE;
 297 }
 298
 299 static void amdgpu_winsys_destroy(struct radeon_winsys *rws)
 300 {
 301    struct amdgpu_winsys *ws = (struct amdgpu_winsys*)rws;
 302
 303    pipe_mutex_destroy(ws->bo_fence_lock);
 304    pb_cache_deinit(&ws->bo_cache);
 305    pipe_mutex_destroy(ws->global_bo_list_lock);
 306    AddrDestroy(ws->addrlib);
 307    amdgpu_device_deinitialize(ws->dev);
 308    FREE(rws);
 309 }
 310
 311 static void amdgpu_winsys_query_info(struct radeon_winsys *rws,
 312                                      struct radeon_info *info)
 313 {
 314    *info = ((struct amdgpu_winsys *)rws)->info;
 315 }
 316
 317 static boolean amdgpu_cs_request_feature(struct radeon_winsys_cs *rcs,
 318                                          enum radeon_feature_id fid,
 319                                          boolean enable)
 320 {
 321    return FALSE;
 322 }
 323
 324 static uint64_t amdgpu_query_value(struct radeon_winsys *rws,
 325                                    enum radeon_value_id value)
 326 {
 327    struct amdgpu_winsys *ws = (struct amdgpu_winsys*)rws;
 328    struct amdgpu_heap_info heap;
 329    uint64_t retval = 0;
 330
 331    switch (value) {
 332    case RADEON_REQUESTED_VRAM_MEMORY:
 333       return ws->allocated_vram;
 334    case RADEON_REQUESTED_GTT_MEMORY:
 335       return ws->allocated_gtt;
 336    case RADEON_BUFFER_WAIT_TIME_NS:
 337       return ws->buffer_wait_time;
 338    case RADEON_TIMESTAMP:
 339       amdgpu_query_info(ws->dev, AMDGPU_INFO_TIMESTAMP, 8, &retval);
 340       return retval;
 341    case RADEON_NUM_CS_FLUSHES:
 342       return ws->num_cs_flushes;
 343    case RADEON_NUM_BYTES_MOVED:
 344       amdgpu_query_info(ws->dev, AMDGPU_INFO_NUM_BYTES_MOVED, 8, &retval);
 345       return retval;
 346    case RADEON_VRAM_USAGE:
 347       amdgpu_query_heap_info(ws->dev, AMDGPU_GEM_DOMAIN_VRAM, 0, &heap);
 348       return heap.heap_usage;
 349    case RADEON_GTT_USAGE:
 350       amdgpu_query_heap_info(ws->dev, AMDGPU_GEM_DOMAIN_GTT, 0, &heap);
 351       return heap.heap_usage;
 352    case RADEON_GPU_TEMPERATURE:
 353    case RADEON_CURRENT_SCLK:
 354    case RADEON_CURRENT_MCLK:
 355       return 0;
 356    case RADEON_GPU_RESET_COUNTER:
 357       assert(0);
 358       return 0;
 359    }
 360    return 0;
 361 }
 362
 363 static bool amdgpu_read_registers(struct radeon_winsys *rws,
 364                                   unsigned reg_offset,
 365                                   unsigned num_registers, uint32_t *out)
 366 {
 367    struct amdgpu_winsys *ws = (struct amdgpu_winsys*)rws;
 368
 369    return amdgpu_read_mm_registers(ws->dev, reg_offset / 4, num_registers,
 370                                    0xffffffff, 0, out) == 0;
 371 }
 372
 373 static unsigned hash_dev(void *key)
 374 {
 375 #if defined(PIPE_ARCH_X86_64)
 376    return pointer_to_intptr(key) ^ (pointer_to_intptr(key) >> 32);
 377 #else
 378    return pointer_to_intptr(key);
 379 #endif
 380 }
 381
 382 static int compare_dev(void *key1, void *key2)
 383 {
 384    return key1 != key2;
 385 }
 386
 387 static bool amdgpu_winsys_unref(struct radeon_winsys *rws)
 388 {
 389    struct amdgpu_winsys *ws = (struct amdgpu_winsys*)rws;
 390    bool destroy;
 391
 392    /* When the reference counter drops to zero, remove the device pointer
 393     * from the table.
 394     * This must happen while the mutex is locked, so that
 395     * amdgpu_winsys_create in another thread doesn't get the winsys
 396     * from the table when the counter drops to 0. */
 397    pipe_mutex_lock(dev_tab_mutex);
 398
 399    destroy = pipe_reference(&ws->reference, NULL);
 400    if (destroy && dev_tab)
 401       util_hash_table_remove(dev_tab, ws->dev);
 402
 403    pipe_mutex_unlock(dev_tab_mutex);
 404    return destroy;
 405 }
 406
 407 PUBLIC struct radeon_winsys *
 408 amdgpu_winsys_create(int fd, radeon_screen_create_t screen_create)
 409 {
 410    struct amdgpu_winsys *ws;
 411    drmVersionPtr version = drmGetVersion(fd);
 412    amdgpu_device_handle dev;
 413    uint32_t drm_major, drm_minor, r;
 414
 415    /* The DRM driver version of amdgpu is 3.x.x. */
 416    if (version->version_major != 3) {
 417       drmFreeVersion(version);
 418       return NULL;
 419    }
 420    drmFreeVersion(version);
 421
 422    /* Look up the winsys from the dev table. */
 423    pipe_mutex_lock(dev_tab_mutex);
 424    if (!dev_tab)
 425       dev_tab = util_hash_table_create(hash_dev, compare_dev);
 426
 427    /* Initialize the amdgpu device. This should always return the same pointer
 428     * for the same fd. */
 429    r = amdgpu_device_initialize(fd, &drm_major, &drm_minor, &dev);
 430    if (r) {
 431       pipe_mutex_unlock(dev_tab_mutex);
 432       fprintf(stderr, "amdgpu: amdgpu_device_initialize failed.\n");
 433       return NULL;
 434    }
 435
 436    /* Lookup a winsys if we have already created one for this device. */
 437    ws = util_hash_table_get(dev_tab, dev);
 438    if (ws) {
 439       pipe_reference(NULL, &ws->reference);
 440       pipe_mutex_unlock(dev_tab_mutex);
 441       return &ws->base;
 442    }
 443
 444    /* Create a new winsys. */
 445    ws = CALLOC_STRUCT(amdgpu_winsys);
 446    if (!ws) {
 447       pipe_mutex_unlock(dev_tab_mutex);
 448       return NULL;
 449    }
 450
 451    ws->dev = dev;
 452    ws->info.drm_major = drm_major;
 453    ws->info.drm_minor = drm_minor;
 454
 455    if (!do_winsys_init(ws))
 456       goto fail;
 457
 458    /* Create managers. */
 459    pb_cache_init(&ws->bo_cache, 500000, 2.0f, 0,
 460                  (ws->info.vram_size + ws->info.gart_size) / 8,
 461                  amdgpu_bo_destroy, amdgpu_bo_can_reclaim);
 462
 463    /* init reference */
 464    pipe_reference_init(&ws->reference, 1);
 465
 466    /* Set functions. */
 467    ws->base.unref = amdgpu_winsys_unref;
 468    ws->base.destroy = amdgpu_winsys_destroy;
 469    ws->base.query_info = amdgpu_winsys_query_info;
 470    ws->base.cs_request_feature = amdgpu_cs_request_feature;
 471    ws->base.query_value = amdgpu_query_value;
 472    ws->base.read_registers = amdgpu_read_registers;
 473
 474    amdgpu_bo_init_functions(ws);
 475    amdgpu_cs_init_functions(ws);
 476    amdgpu_surface_init_functions(ws);
 477
 478    LIST_INITHEAD(&ws->global_bo_list);
 479    pipe_mutex_init(ws->global_bo_list_lock);
 480    pipe_mutex_init(ws->bo_fence_lock);
 481
 482    /* Create the screen at the end. The winsys must be initialized
 483     * completely.
 484     *
 485     * Alternatively, we could create the screen based on "ws->gen"
 486     * and link all drivers into one binary blob. */
 487    ws->base.screen = screen_create(&ws->base);
 488    if (!ws->base.screen) {
 489       amdgpu_winsys_destroy(&ws->base);
 490       pipe_mutex_unlock(dev_tab_mutex);
 491       return NULL;
 492    }
 493
 494    util_hash_table_set(dev_tab, dev, ws);
 495
 496    /* We must unlock the mutex once the winsys is fully initialized, so that
 497     * other threads attempting to create the winsys from the same fd will
 498     * get a fully initialized winsys and not just half-way initialized. */
 499    pipe_mutex_unlock(dev_tab_mutex);
 500
 501    return &ws->base;
 502
 503 fail:
 504    pipe_mutex_unlock(dev_tab_mutex);
 505    pb_cache_deinit(&ws->bo_cache);
 506    FREE(ws);
 507    return NULL;
 508 }