2 * Copyright © 2009 Corbin Simpson <MostAwesomeDude@gmail.com>
3 * Copyright © 2009 Joakim Sindholt <opensource@zhasha.com>
4 * Copyright © 2011 Marek Olšák <maraeo@gmail.com>
5 * Copyright © 2015 Advanced Micro Devices, Inc.
8 * Permission is hereby granted, free of charge, to any person obtaining
9 * a copy of this software and associated documentation files (the
10 * "Software"), to deal in the Software without restriction, including
11 * without limitation the rights to use, copy, modify, merge, publish,
12 * distribute, sub license, and/or sell copies of the Software, and to
13 * permit persons to whom the Software is furnished to do so, subject to
14 * the following conditions:
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
17 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
18 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
19 * NON-INFRINGEMENT. IN NO EVENT SHALL THE COPYRIGHT HOLDERS, AUTHORS
20 * AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
21 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
22 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
23 * USE OR OTHER DEALINGS IN THE SOFTWARE.
25 * The above copyright notice and this permission notice (including the
26 * next paragraph) shall be included in all copies or substantial portions
31 * Marek Olšák <maraeo@gmail.com>
34 #include "amdgpu_cs.h"
35 #include "amdgpu_public.h"
37 #include "util/u_hash_table.h"
38 #include <amdgpu_drm.h>
42 #include "amdgpu_id.h"
44 #define CIK_TILE_MODE_COLOR_2D 14
46 #define CIK__GB_TILE_MODE__PIPE_CONFIG(x) (((x) >> 6) & 0x1f)
47 #define CIK__PIPE_CONFIG__ADDR_SURF_P2 0
48 #define CIK__PIPE_CONFIG__ADDR_SURF_P4_8x16 4
49 #define CIK__PIPE_CONFIG__ADDR_SURF_P4_16x16 5
50 #define CIK__PIPE_CONFIG__ADDR_SURF_P4_16x32 6
51 #define CIK__PIPE_CONFIG__ADDR_SURF_P4_32x32 7
52 #define CIK__PIPE_CONFIG__ADDR_SURF_P8_16x16_8x16 8
53 #define CIK__PIPE_CONFIG__ADDR_SURF_P8_16x32_8x16 9
54 #define CIK__PIPE_CONFIG__ADDR_SURF_P8_32x32_8x16 10
55 #define CIK__PIPE_CONFIG__ADDR_SURF_P8_16x32_16x16 11
56 #define CIK__PIPE_CONFIG__ADDR_SURF_P8_32x32_16x16 12
57 #define CIK__PIPE_CONFIG__ADDR_SURF_P8_32x32_16x32 13
58 #define CIK__PIPE_CONFIG__ADDR_SURF_P8_32x64_32x32 14
59 #define CIK__PIPE_CONFIG__ADDR_SURF_P16_32X32_8X16 16
60 #define CIK__PIPE_CONFIG__ADDR_SURF_P16_32X32_16X16 17
62 static struct util_hash_table
*dev_tab
= NULL
;
63 pipe_static_mutex(dev_tab_mutex
);
65 static unsigned cik_get_num_tile_pipes(struct amdgpu_gpu_info
*info
)
67 unsigned mode2d
= info
->gb_tile_mode
[CIK_TILE_MODE_COLOR_2D
];
69 switch (CIK__GB_TILE_MODE__PIPE_CONFIG(mode2d
)) {
70 case CIK__PIPE_CONFIG__ADDR_SURF_P2
:
72 case CIK__PIPE_CONFIG__ADDR_SURF_P4_8x16
:
73 case CIK__PIPE_CONFIG__ADDR_SURF_P4_16x16
:
74 case CIK__PIPE_CONFIG__ADDR_SURF_P4_16x32
:
75 case CIK__PIPE_CONFIG__ADDR_SURF_P4_32x32
:
77 case CIK__PIPE_CONFIG__ADDR_SURF_P8_16x16_8x16
:
78 case CIK__PIPE_CONFIG__ADDR_SURF_P8_16x32_8x16
:
79 case CIK__PIPE_CONFIG__ADDR_SURF_P8_32x32_8x16
:
80 case CIK__PIPE_CONFIG__ADDR_SURF_P8_16x32_16x16
:
81 case CIK__PIPE_CONFIG__ADDR_SURF_P8_32x32_16x16
:
82 case CIK__PIPE_CONFIG__ADDR_SURF_P8_32x32_16x32
:
83 case CIK__PIPE_CONFIG__ADDR_SURF_P8_32x64_32x32
:
85 case CIK__PIPE_CONFIG__ADDR_SURF_P16_32X32_8X16
:
86 case CIK__PIPE_CONFIG__ADDR_SURF_P16_32X32_16X16
:
89 fprintf(stderr
, "Invalid CIK pipe configuration, assuming P2\n");
90 assert(!"this should never occur");
95 /* Helper function to do the ioctls needed for setup and init. */
96 static boolean
do_winsys_init(struct amdgpu_winsys
*ws
, int fd
)
98 struct amdgpu_buffer_size_alignments alignment_info
= {};
99 struct amdgpu_heap_info vram
, gtt
;
100 struct drm_amdgpu_info_hw_ip dma
= {}, uvd
= {}, vce
= {};
101 uint32_t vce_version
= 0, vce_feature
= 0;
103 drmDevicePtr devinfo
;
106 r
= drmGetDevice(fd
, &devinfo
);
108 fprintf(stderr
, "amdgpu: drmGetDevice failed.\n");
111 ws
->info
.pci_domain
= devinfo
->businfo
.pci
->domain
;
112 ws
->info
.pci_bus
= devinfo
->businfo
.pci
->bus
;
113 ws
->info
.pci_dev
= devinfo
->businfo
.pci
->dev
;
114 ws
->info
.pci_func
= devinfo
->businfo
.pci
->func
;
115 drmFreeDevice(&devinfo
);
117 /* Query hardware and driver information. */
118 r
= amdgpu_query_gpu_info(ws
->dev
, &ws
->amdinfo
);
120 fprintf(stderr
, "amdgpu: amdgpu_query_gpu_info failed.\n");
124 r
= amdgpu_query_buffer_size_alignment(ws
->dev
, &alignment_info
);
126 fprintf(stderr
, "amdgpu: amdgpu_query_buffer_size_alignment failed.\n");
130 r
= amdgpu_query_heap_info(ws
->dev
, AMDGPU_GEM_DOMAIN_VRAM
, 0, &vram
);
132 fprintf(stderr
, "amdgpu: amdgpu_query_heap_info(vram) failed.\n");
136 r
= amdgpu_query_heap_info(ws
->dev
, AMDGPU_GEM_DOMAIN_GTT
, 0, >t
);
138 fprintf(stderr
, "amdgpu: amdgpu_query_heap_info(gtt) failed.\n");
142 r
= amdgpu_query_hw_ip_info(ws
->dev
, AMDGPU_HW_IP_DMA
, 0, &dma
);
144 fprintf(stderr
, "amdgpu: amdgpu_query_hw_ip_info(dma) failed.\n");
148 r
= amdgpu_query_hw_ip_info(ws
->dev
, AMDGPU_HW_IP_UVD
, 0, &uvd
);
150 fprintf(stderr
, "amdgpu: amdgpu_query_hw_ip_info(uvd) failed.\n");
154 r
= amdgpu_query_hw_ip_info(ws
->dev
, AMDGPU_HW_IP_VCE
, 0, &vce
);
156 fprintf(stderr
, "amdgpu: amdgpu_query_hw_ip_info(vce) failed.\n");
160 r
= amdgpu_query_firmware_version(ws
->dev
, AMDGPU_INFO_FW_VCE
, 0, 0,
161 &vce_version
, &vce_feature
);
163 fprintf(stderr
, "amdgpu: amdgpu_query_firmware_version(vce) failed.\n");
167 /* Set chip identification. */
168 ws
->info
.pci_id
= ws
->amdinfo
.asic_id
; /* TODO: is this correct? */
169 ws
->info
.vce_harvest_config
= ws
->amdinfo
.vce_harvest_config
;
171 switch (ws
->info
.pci_id
) {
172 #define CHIPSET(pci_id, name, cfamily) case pci_id: ws->info.family = CHIP_##cfamily; break;
173 #include "pci_ids/radeonsi_pci_ids.h"
177 fprintf(stderr
, "amdgpu: Invalid PCI ID.\n");
181 if (ws
->info
.family
>= CHIP_TONGA
)
182 ws
->info
.chip_class
= VI
;
183 else if (ws
->info
.family
>= CHIP_BONAIRE
)
184 ws
->info
.chip_class
= CIK
;
186 fprintf(stderr
, "amdgpu: Unknown family.\n");
190 /* LLVM 3.6.1 is required for VI. */
191 if (ws
->info
.chip_class
>= VI
&&
192 HAVE_LLVM
== 0x0306 && MESA_LLVM_VERSION_PATCH
< 1) {
193 fprintf(stderr
, "amdgpu: LLVM 3.6.1 is required, got LLVM %i.%i.%i\n",
194 HAVE_LLVM
>> 8, HAVE_LLVM
& 255, MESA_LLVM_VERSION_PATCH
);
198 /* family and rev_id are for addrlib */
199 switch (ws
->info
.family
) {
201 ws
->family
= FAMILY_CI
;
202 ws
->rev_id
= CI_BONAIRE_M_A0
;
205 ws
->family
= FAMILY_KV
;
206 ws
->rev_id
= KV_SPECTRE_A0
;
209 ws
->family
= FAMILY_KV
;
210 ws
->rev_id
= KB_KALINDI_A0
;
213 ws
->family
= FAMILY_CI
;
214 ws
->rev_id
= CI_HAWAII_P_A0
;
217 ws
->family
= FAMILY_KV
;
218 ws
->rev_id
= ML_GODAVARI_A0
;
221 ws
->family
= FAMILY_VI
;
222 ws
->rev_id
= VI_TONGA_P_A0
;
225 ws
->family
= FAMILY_VI
;
226 ws
->rev_id
= VI_ICELAND_M_A0
;
229 ws
->family
= FAMILY_CZ
;
230 ws
->rev_id
= CARRIZO_A0
;
233 ws
->family
= FAMILY_CZ
;
234 ws
->rev_id
= STONEY_A0
;
237 ws
->family
= FAMILY_VI
;
238 ws
->rev_id
= VI_FIJI_P_A0
;
241 ws
->family
= FAMILY_VI
;
242 ws
->rev_id
= VI_POLARIS10_P_A0
;
245 ws
->family
= FAMILY_VI
;
246 ws
->rev_id
= VI_POLARIS11_M_A0
;
249 fprintf(stderr
, "amdgpu: Unknown family.\n");
253 ws
->addrlib
= amdgpu_addr_create(ws
);
255 fprintf(stderr
, "amdgpu: Cannot create addrlib.\n");
259 /* Set which chips have dedicated VRAM. */
260 ws
->info
.has_dedicated_vram
=
261 !(ws
->amdinfo
.ids_flags
& AMDGPU_IDS_FLAGS_FUSION
);
263 /* Set hardware information. */
264 ws
->info
.gart_size
= gtt
.heap_size
;
265 ws
->info
.vram_size
= vram
.heap_size
;
266 /* convert the shader clock from KHz to MHz */
267 ws
->info
.max_shader_clock
= ws
->amdinfo
.max_engine_clk
/ 1000;
268 ws
->info
.max_se
= ws
->amdinfo
.num_shader_engines
;
269 ws
->info
.max_sh_per_se
= ws
->amdinfo
.num_shader_arrays_per_engine
;
270 ws
->info
.has_uvd
= uvd
.available_rings
!= 0;
271 ws
->info
.vce_fw_version
=
272 vce
.available_rings
? vce_version
: 0;
273 ws
->info
.has_userptr
= TRUE
;
274 ws
->info
.num_render_backends
= ws
->amdinfo
.rb_pipes
;
275 ws
->info
.clock_crystal_freq
= ws
->amdinfo
.gpu_counter_freq
;
276 ws
->info
.num_tile_pipes
= cik_get_num_tile_pipes(&ws
->amdinfo
);
277 ws
->info
.pipe_interleave_bytes
= 256 << ((ws
->amdinfo
.gb_addr_cfg
>> 4) & 0x7);
278 ws
->info
.has_virtual_memory
= TRUE
;
279 ws
->info
.has_sdma
= dma
.available_rings
!= 0;
281 /* Get the number of good compute units. */
282 ws
->info
.num_good_compute_units
= 0;
283 for (i
= 0; i
< ws
->info
.max_se
; i
++)
284 for (j
= 0; j
< ws
->info
.max_sh_per_se
; j
++)
285 ws
->info
.num_good_compute_units
+=
286 util_bitcount(ws
->amdinfo
.cu_bitmap
[i
][j
]);
288 memcpy(ws
->info
.si_tile_mode_array
, ws
->amdinfo
.gb_tile_mode
,
289 sizeof(ws
->amdinfo
.gb_tile_mode
));
290 ws
->info
.enabled_rb_mask
= ws
->amdinfo
.enabled_rb_pipes_mask
;
292 memcpy(ws
->info
.cik_macrotile_mode_array
, ws
->amdinfo
.gb_macro_tile_mode
,
293 sizeof(ws
->amdinfo
.gb_macro_tile_mode
));
295 ws
->info
.gart_page_size
= alignment_info
.size_remote
;
301 AddrDestroy(ws
->addrlib
);
302 amdgpu_device_deinitialize(ws
->dev
);
307 static void amdgpu_winsys_destroy(struct radeon_winsys
*rws
)
309 struct amdgpu_winsys
*ws
= (struct amdgpu_winsys
*)rws
;
311 if (util_queue_is_initialized(&ws
->cs_queue
))
312 util_queue_destroy(&ws
->cs_queue
);
314 pipe_mutex_destroy(ws
->bo_fence_lock
);
315 pb_cache_deinit(&ws
->bo_cache
);
316 pipe_mutex_destroy(ws
->global_bo_list_lock
);
317 AddrDestroy(ws
->addrlib
);
318 amdgpu_device_deinitialize(ws
->dev
);
322 static void amdgpu_winsys_query_info(struct radeon_winsys
*rws
,
323 struct radeon_info
*info
)
325 *info
= ((struct amdgpu_winsys
*)rws
)->info
;
328 static boolean
amdgpu_cs_request_feature(struct radeon_winsys_cs
*rcs
,
329 enum radeon_feature_id fid
,
335 static uint64_t amdgpu_query_value(struct radeon_winsys
*rws
,
336 enum radeon_value_id value
)
338 struct amdgpu_winsys
*ws
= (struct amdgpu_winsys
*)rws
;
339 struct amdgpu_heap_info heap
;
343 case RADEON_REQUESTED_VRAM_MEMORY
:
344 return ws
->allocated_vram
;
345 case RADEON_REQUESTED_GTT_MEMORY
:
346 return ws
->allocated_gtt
;
347 case RADEON_BUFFER_WAIT_TIME_NS
:
348 return ws
->buffer_wait_time
;
349 case RADEON_TIMESTAMP
:
350 amdgpu_query_info(ws
->dev
, AMDGPU_INFO_TIMESTAMP
, 8, &retval
);
352 case RADEON_NUM_CS_FLUSHES
:
353 return ws
->num_cs_flushes
;
354 case RADEON_NUM_BYTES_MOVED
:
355 amdgpu_query_info(ws
->dev
, AMDGPU_INFO_NUM_BYTES_MOVED
, 8, &retval
);
357 case RADEON_VRAM_USAGE
:
358 amdgpu_query_heap_info(ws
->dev
, AMDGPU_GEM_DOMAIN_VRAM
, 0, &heap
);
359 return heap
.heap_usage
;
360 case RADEON_GTT_USAGE
:
361 amdgpu_query_heap_info(ws
->dev
, AMDGPU_GEM_DOMAIN_GTT
, 0, &heap
);
362 return heap
.heap_usage
;
363 case RADEON_GPU_TEMPERATURE
:
364 case RADEON_CURRENT_SCLK
:
365 case RADEON_CURRENT_MCLK
:
367 case RADEON_GPU_RESET_COUNTER
:
374 static bool amdgpu_read_registers(struct radeon_winsys
*rws
,
376 unsigned num_registers
, uint32_t *out
)
378 struct amdgpu_winsys
*ws
= (struct amdgpu_winsys
*)rws
;
380 return amdgpu_read_mm_registers(ws
->dev
, reg_offset
/ 4, num_registers
,
381 0xffffffff, 0, out
) == 0;
384 static unsigned hash_dev(void *key
)
386 #if defined(PIPE_ARCH_X86_64)
387 return pointer_to_intptr(key
) ^ (pointer_to_intptr(key
) >> 32);
389 return pointer_to_intptr(key
);
393 static int compare_dev(void *key1
, void *key2
)
398 DEBUG_GET_ONCE_BOOL_OPTION(thread
, "RADEON_THREAD", TRUE
)
400 static bool amdgpu_winsys_unref(struct radeon_winsys
*rws
)
402 struct amdgpu_winsys
*ws
= (struct amdgpu_winsys
*)rws
;
405 /* When the reference counter drops to zero, remove the device pointer
407 * This must happen while the mutex is locked, so that
408 * amdgpu_winsys_create in another thread doesn't get the winsys
409 * from the table when the counter drops to 0. */
410 pipe_mutex_lock(dev_tab_mutex
);
412 destroy
= pipe_reference(&ws
->reference
, NULL
);
413 if (destroy
&& dev_tab
)
414 util_hash_table_remove(dev_tab
, ws
->dev
);
416 pipe_mutex_unlock(dev_tab_mutex
);
420 PUBLIC
struct radeon_winsys
*
421 amdgpu_winsys_create(int fd
, radeon_screen_create_t screen_create
)
423 struct amdgpu_winsys
*ws
;
424 drmVersionPtr version
= drmGetVersion(fd
);
425 amdgpu_device_handle dev
;
426 uint32_t drm_major
, drm_minor
, r
;
428 /* The DRM driver version of amdgpu is 3.x.x. */
429 if (version
->version_major
!= 3) {
430 drmFreeVersion(version
);
433 drmFreeVersion(version
);
435 /* Look up the winsys from the dev table. */
436 pipe_mutex_lock(dev_tab_mutex
);
438 dev_tab
= util_hash_table_create(hash_dev
, compare_dev
);
440 /* Initialize the amdgpu device. This should always return the same pointer
441 * for the same fd. */
442 r
= amdgpu_device_initialize(fd
, &drm_major
, &drm_minor
, &dev
);
444 pipe_mutex_unlock(dev_tab_mutex
);
445 fprintf(stderr
, "amdgpu: amdgpu_device_initialize failed.\n");
449 /* Lookup a winsys if we have already created one for this device. */
450 ws
= util_hash_table_get(dev_tab
, dev
);
452 pipe_reference(NULL
, &ws
->reference
);
453 pipe_mutex_unlock(dev_tab_mutex
);
457 /* Create a new winsys. */
458 ws
= CALLOC_STRUCT(amdgpu_winsys
);
460 pipe_mutex_unlock(dev_tab_mutex
);
465 ws
->info
.drm_major
= drm_major
;
466 ws
->info
.drm_minor
= drm_minor
;
468 if (!do_winsys_init(ws
, fd
))
471 /* Create managers. */
472 pb_cache_init(&ws
->bo_cache
, 500000, 2.0f
, 0,
473 (ws
->info
.vram_size
+ ws
->info
.gart_size
) / 8,
474 amdgpu_bo_destroy
, amdgpu_bo_can_reclaim
);
477 pipe_reference_init(&ws
->reference
, 1);
480 ws
->base
.unref
= amdgpu_winsys_unref
;
481 ws
->base
.destroy
= amdgpu_winsys_destroy
;
482 ws
->base
.query_info
= amdgpu_winsys_query_info
;
483 ws
->base
.cs_request_feature
= amdgpu_cs_request_feature
;
484 ws
->base
.query_value
= amdgpu_query_value
;
485 ws
->base
.read_registers
= amdgpu_read_registers
;
487 amdgpu_bo_init_functions(ws
);
488 amdgpu_cs_init_functions(ws
);
489 amdgpu_surface_init_functions(ws
);
491 LIST_INITHEAD(&ws
->global_bo_list
);
492 pipe_mutex_init(ws
->global_bo_list_lock
);
493 pipe_mutex_init(ws
->bo_fence_lock
);
495 if (sysconf(_SC_NPROCESSORS_ONLN
) > 1 && debug_get_option_thread())
496 util_queue_init(&ws
->cs_queue
, 8, 1, amdgpu_cs_submit_ib
);
498 /* Create the screen at the end. The winsys must be initialized
501 * Alternatively, we could create the screen based on "ws->gen"
502 * and link all drivers into one binary blob. */
503 ws
->base
.screen
= screen_create(&ws
->base
);
504 if (!ws
->base
.screen
) {
505 amdgpu_winsys_destroy(&ws
->base
);
506 pipe_mutex_unlock(dev_tab_mutex
);
510 util_hash_table_set(dev_tab
, dev
, ws
);
512 /* We must unlock the mutex once the winsys is fully initialized, so that
513 * other threads attempting to create the winsys from the same fd will
514 * get a fully initialized winsys and not just half-way initialized. */
515 pipe_mutex_unlock(dev_tab_mutex
);
520 pipe_mutex_unlock(dev_tab_mutex
);
521 pb_cache_deinit(&ws
->bo_cache
);