src/gallium/winsys/amdgpu/drm/amdgpu_winsys.c

   1 /*
   2  * Copyright © 2009 Corbin Simpson <MostAwesomeDude@gmail.com>
   3  * Copyright © 2009 Joakim Sindholt <opensource@zhasha.com>
   4  * Copyright © 2011 Marek Olšák <maraeo@gmail.com>
   5  * Copyright © 2015 Advanced Micro Devices, Inc.
   6  * All Rights Reserved.
   7  *
   8  * Permission is hereby granted, free of charge, to any person obtaining
   9  * a copy of this software and associated documentation files (the
  10  * "Software"), to deal in the Software without restriction, including
  11  * without limitation the rights to use, copy, modify, merge, publish,
  12  * distribute, sub license, and/or sell copies of the Software, and to
  13  * permit persons to whom the Software is furnished to do so, subject to
  14  * the following conditions:
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  17  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
  18  * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  19  * NON-INFRINGEMENT. IN NO EVENT SHALL THE COPYRIGHT HOLDERS, AUTHORS
  20  * AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  21  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  22  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
  23  * USE OR OTHER DEALINGS IN THE SOFTWARE.
  24  *
  25  * The above copyright notice and this permission notice (including the
  26  * next paragraph) shall be included in all copies or substantial portions
  27  * of the Software.
  28  */
  29 /*
  30  * Authors:
  31  *      Marek Olšák <maraeo@gmail.com>
  32  */
  33
  34 #include "amdgpu_cs.h"
  35 #include "amdgpu_public.h"
  36
  37 #include "util/u_hash_table.h"
  38 #include <amdgpu_drm.h>
  39 #include <xf86drm.h>
  40 #include <stdio.h>
  41 #include <sys/stat.h>
  42 #include "amd/common/amdgpu_id.h"
  43
  44 #define CIK_TILE_MODE_COLOR_2D                  14
  45
  46 #define CIK__GB_TILE_MODE__PIPE_CONFIG(x)        (((x) >> 6) & 0x1f)
  47 #define     CIK__PIPE_CONFIG__ADDR_SURF_P2               0
  48 #define     CIK__PIPE_CONFIG__ADDR_SURF_P4_8x16          4
  49 #define     CIK__PIPE_CONFIG__ADDR_SURF_P4_16x16         5
  50 #define     CIK__PIPE_CONFIG__ADDR_SURF_P4_16x32         6
  51 #define     CIK__PIPE_CONFIG__ADDR_SURF_P4_32x32         7
  52 #define     CIK__PIPE_CONFIG__ADDR_SURF_P8_16x16_8x16    8
  53 #define     CIK__PIPE_CONFIG__ADDR_SURF_P8_16x32_8x16    9
  54 #define     CIK__PIPE_CONFIG__ADDR_SURF_P8_32x32_8x16    10
  55 #define     CIK__PIPE_CONFIG__ADDR_SURF_P8_16x32_16x16   11
  56 #define     CIK__PIPE_CONFIG__ADDR_SURF_P8_32x32_16x16   12
  57 #define     CIK__PIPE_CONFIG__ADDR_SURF_P8_32x32_16x32   13
  58 #define     CIK__PIPE_CONFIG__ADDR_SURF_P8_32x64_32x32   14
  59 #define     CIK__PIPE_CONFIG__ADDR_SURF_P16_32X32_8X16   16
  60 #define     CIK__PIPE_CONFIG__ADDR_SURF_P16_32X32_16X16  17
  61
  62 #ifndef AMDGPU_INFO_NUM_EVICTIONS
  63 #define AMDGPU_INFO_NUM_EVICTIONS               0x18
  64 #endif
  65
  66 static struct util_hash_table *dev_tab = NULL;
  67 static mtx_t dev_tab_mutex = _MTX_INITIALIZER_NP;
  68
  69 static unsigned cik_get_num_tile_pipes(struct amdgpu_gpu_info *info)
  70 {
  71    unsigned mode2d = info->gb_tile_mode[CIK_TILE_MODE_COLOR_2D];
  72
  73    switch (CIK__GB_TILE_MODE__PIPE_CONFIG(mode2d)) {
  74    case CIK__PIPE_CONFIG__ADDR_SURF_P2:
  75        return 2;
  76    case CIK__PIPE_CONFIG__ADDR_SURF_P4_8x16:
  77    case CIK__PIPE_CONFIG__ADDR_SURF_P4_16x16:
  78    case CIK__PIPE_CONFIG__ADDR_SURF_P4_16x32:
  79    case CIK__PIPE_CONFIG__ADDR_SURF_P4_32x32:
  80        return 4;
  81    case CIK__PIPE_CONFIG__ADDR_SURF_P8_16x16_8x16:
  82    case CIK__PIPE_CONFIG__ADDR_SURF_P8_16x32_8x16:
  83    case CIK__PIPE_CONFIG__ADDR_SURF_P8_32x32_8x16:
  84    case CIK__PIPE_CONFIG__ADDR_SURF_P8_16x32_16x16:
  85    case CIK__PIPE_CONFIG__ADDR_SURF_P8_32x32_16x16:
  86    case CIK__PIPE_CONFIG__ADDR_SURF_P8_32x32_16x32:
  87    case CIK__PIPE_CONFIG__ADDR_SURF_P8_32x64_32x32:
  88        return 8;
  89    case CIK__PIPE_CONFIG__ADDR_SURF_P16_32X32_8X16:
  90    case CIK__PIPE_CONFIG__ADDR_SURF_P16_32X32_16X16:
  91        return 16;
  92    default:
  93        fprintf(stderr, "Invalid CIK pipe configuration, assuming P2\n");
  94        assert(!"this should never occur");
  95        return 2;
  96    }
  97 }
  98
  99 /* Helper function to do the ioctls needed for setup and init. */
 100 static bool do_winsys_init(struct amdgpu_winsys *ws, int fd)
 101 {
 102    struct amdgpu_buffer_size_alignments alignment_info = {};
 103    struct amdgpu_heap_info vram, vram_vis, gtt;
 104    struct drm_amdgpu_info_hw_ip dma = {}, uvd = {}, vce = {};
 105    uint32_t vce_version = 0, vce_feature = 0, uvd_version = 0, uvd_feature = 0;
 106    uint32_t unused_feature;
 107    int r, i, j;
 108    drmDevicePtr devinfo;
 109
 110    /* Get PCI info. */
 111    r = drmGetDevice2(fd, 0, &devinfo);
 112    if (r) {
 113       fprintf(stderr, "amdgpu: drmGetDevice2 failed.\n");
 114       goto fail;
 115    }
 116    ws->info.pci_domain = devinfo->businfo.pci->domain;
 117    ws->info.pci_bus = devinfo->businfo.pci->bus;
 118    ws->info.pci_dev = devinfo->businfo.pci->dev;
 119    ws->info.pci_func = devinfo->businfo.pci->func;
 120    drmFreeDevice(&devinfo);
 121
 122    /* Query hardware and driver information. */
 123    r = amdgpu_query_gpu_info(ws->dev, &ws->amdinfo);
 124    if (r) {
 125       fprintf(stderr, "amdgpu: amdgpu_query_gpu_info failed.\n");
 126       goto fail;
 127    }
 128
 129    r = amdgpu_query_buffer_size_alignment(ws->dev, &alignment_info);
 130    if (r) {
 131       fprintf(stderr, "amdgpu: amdgpu_query_buffer_size_alignment failed.\n");
 132       goto fail;
 133    }
 134
 135    r = amdgpu_query_heap_info(ws->dev, AMDGPU_GEM_DOMAIN_VRAM, 0, &vram);
 136    if (r) {
 137       fprintf(stderr, "amdgpu: amdgpu_query_heap_info(vram) failed.\n");
 138       goto fail;
 139    }
 140
 141    r = amdgpu_query_heap_info(ws->dev, AMDGPU_GEM_DOMAIN_VRAM,
 142                               AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED,
 143                               &vram_vis);
 144    if (r) {
 145       fprintf(stderr, "amdgpu: amdgpu_query_heap_info(vram_vis) failed.\n");
 146       goto fail;
 147    }
 148
 149    r = amdgpu_query_heap_info(ws->dev, AMDGPU_GEM_DOMAIN_GTT, 0, &gtt);
 150    if (r) {
 151       fprintf(stderr, "amdgpu: amdgpu_query_heap_info(gtt) failed.\n");
 152       goto fail;
 153    }
 154
 155    r = amdgpu_query_hw_ip_info(ws->dev, AMDGPU_HW_IP_DMA, 0, &dma);
 156    if (r) {
 157       fprintf(stderr, "amdgpu: amdgpu_query_hw_ip_info(dma) failed.\n");
 158       goto fail;
 159    }
 160
 161    r = amdgpu_query_hw_ip_info(ws->dev, AMDGPU_HW_IP_UVD, 0, &uvd);
 162    if (r) {
 163       fprintf(stderr, "amdgpu: amdgpu_query_hw_ip_info(uvd) failed.\n");
 164       goto fail;
 165    }
 166
 167    r = amdgpu_query_firmware_version(ws->dev, AMDGPU_INFO_FW_GFX_ME, 0, 0,
 168                                      &ws->info.me_fw_version, &unused_feature);
 169    if (r) {
 170       fprintf(stderr, "amdgpu: amdgpu_query_firmware_version(me) failed.\n");
 171       goto fail;
 172    }
 173
 174    r = amdgpu_query_firmware_version(ws->dev, AMDGPU_INFO_FW_GFX_PFP, 0, 0,
 175                                      &ws->info.pfp_fw_version, &unused_feature);
 176    if (r) {
 177       fprintf(stderr, "amdgpu: amdgpu_query_firmware_version(pfp) failed.\n");
 178       goto fail;
 179    }
 180
 181    r = amdgpu_query_firmware_version(ws->dev, AMDGPU_INFO_FW_GFX_CE, 0, 0,
 182                                      &ws->info.ce_fw_version, &unused_feature);
 183    if (r) {
 184       fprintf(stderr, "amdgpu: amdgpu_query_firmware_version(ce) failed.\n");
 185       goto fail;
 186    }
 187
 188    r = amdgpu_query_firmware_version(ws->dev, AMDGPU_INFO_FW_UVD, 0, 0,
 189                                      &uvd_version, &uvd_feature);
 190    if (r) {
 191       fprintf(stderr, "amdgpu: amdgpu_query_firmware_version(uvd) failed.\n");
 192       goto fail;
 193    }
 194
 195    r = amdgpu_query_hw_ip_info(ws->dev, AMDGPU_HW_IP_VCE, 0, &vce);
 196    if (r) {
 197       fprintf(stderr, "amdgpu: amdgpu_query_hw_ip_info(vce) failed.\n");
 198       goto fail;
 199    }
 200
 201    r = amdgpu_query_firmware_version(ws->dev, AMDGPU_INFO_FW_VCE, 0, 0,
 202                                      &vce_version, &vce_feature);
 203    if (r) {
 204       fprintf(stderr, "amdgpu: amdgpu_query_firmware_version(vce) failed.\n");
 205       goto fail;
 206    }
 207
 208    /* Set chip identification. */
 209    ws->info.pci_id = ws->amdinfo.asic_id; /* TODO: is this correct? */
 210    ws->info.vce_harvest_config = ws->amdinfo.vce_harvest_config;
 211
 212    switch (ws->info.pci_id) {
 213 #define CHIPSET(pci_id, name, cfamily) case pci_id: ws->info.family = CHIP_##cfamily; break;
 214 #include "pci_ids/radeonsi_pci_ids.h"
 215 #undef CHIPSET
 216
 217    default:
 218       fprintf(stderr, "amdgpu: Invalid PCI ID.\n");
 219       goto fail;
 220    }
 221
 222    if (ws->info.family >= CHIP_VEGA10)
 223       ws->info.chip_class = GFX9;
 224    else if (ws->info.family >= CHIP_TONGA)
 225       ws->info.chip_class = VI;
 226    else if (ws->info.family >= CHIP_BONAIRE)
 227       ws->info.chip_class = CIK;
 228    else if (ws->info.family >= CHIP_TAHITI)
 229       ws->info.chip_class = SI;
 230    else {
 231       fprintf(stderr, "amdgpu: Unknown family.\n");
 232       goto fail;
 233    }
 234
 235    /* family and rev_id are for addrlib */
 236    switch (ws->info.family) {
 237    case CHIP_TAHITI:
 238       ws->family = FAMILY_SI;
 239       ws->rev_id = SI_TAHITI_P_A0;
 240       break;
 241    case CHIP_PITCAIRN:
 242       ws->family = FAMILY_SI;
 243       ws->rev_id = SI_PITCAIRN_PM_A0;
 244       break;
 245    case CHIP_VERDE:
 246       ws->family = FAMILY_SI;
 247       ws->rev_id = SI_CAPEVERDE_M_A0;
 248       break;
 249    case CHIP_OLAND:
 250       ws->family = FAMILY_SI;
 251       ws->rev_id = SI_OLAND_M_A0;
 252       break;
 253    case CHIP_HAINAN:
 254       ws->family = FAMILY_SI;
 255       ws->rev_id = SI_HAINAN_V_A0;
 256       break;
 257    case CHIP_BONAIRE:
 258       ws->family = FAMILY_CI;
 259       ws->rev_id = CI_BONAIRE_M_A0;
 260       break;
 261    case CHIP_KAVERI:
 262       ws->family = FAMILY_KV;
 263       ws->rev_id = KV_SPECTRE_A0;
 264       break;
 265    case CHIP_KABINI:
 266       ws->family = FAMILY_KV;
 267       ws->rev_id = KB_KALINDI_A0;
 268       break;
 269    case CHIP_HAWAII:
 270       ws->family = FAMILY_CI;
 271       ws->rev_id = CI_HAWAII_P_A0;
 272       break;
 273    case CHIP_MULLINS:
 274       ws->family = FAMILY_KV;
 275       ws->rev_id = ML_GODAVARI_A0;
 276       break;
 277    case CHIP_TONGA:
 278       ws->family = FAMILY_VI;
 279       ws->rev_id = VI_TONGA_P_A0;
 280       break;
 281    case CHIP_ICELAND:
 282       ws->family = FAMILY_VI;
 283       ws->rev_id = VI_ICELAND_M_A0;
 284       break;
 285    case CHIP_CARRIZO:
 286       ws->family = FAMILY_CZ;
 287       ws->rev_id = CARRIZO_A0;
 288       break;
 289    case CHIP_STONEY:
 290       ws->family = FAMILY_CZ;
 291       ws->rev_id = STONEY_A0;
 292       break;
 293    case CHIP_FIJI:
 294       ws->family = FAMILY_VI;
 295       ws->rev_id = VI_FIJI_P_A0;
 296       break;
 297    case CHIP_POLARIS10:
 298       ws->family = FAMILY_VI;
 299       ws->rev_id = VI_POLARIS10_P_A0;
 300       break;
 301    case CHIP_POLARIS11:
 302       ws->family = FAMILY_VI;
 303       ws->rev_id = VI_POLARIS11_M_A0;
 304       break;
 305    case CHIP_POLARIS12:
 306       ws->family = FAMILY_VI;
 307       ws->rev_id = VI_POLARIS12_V_A0;
 308    case CHIP_VEGA10:
 309       ws->family = FAMILY_AI;
 310       ws->rev_id = AI_VEGA10_P_A0;
 311       break;
 312    default:
 313       fprintf(stderr, "amdgpu: Unknown family.\n");
 314       goto fail;
 315    }
 316
 317    ws->addrlib = amdgpu_addr_create(ws);
 318    if (!ws->addrlib) {
 319       fprintf(stderr, "amdgpu: Cannot create addrlib.\n");
 320       goto fail;
 321    }
 322
 323    /* Set which chips have dedicated VRAM. */
 324    ws->info.has_dedicated_vram =
 325       !(ws->amdinfo.ids_flags & AMDGPU_IDS_FLAGS_FUSION);
 326
 327    /* Set hardware information. */
 328    ws->info.gart_size = gtt.heap_size;
 329    ws->info.vram_size = vram.heap_size;
 330    ws->info.vram_vis_size = vram_vis.heap_size;
 331    /* The kernel can split large buffers in VRAM but not in GTT, so large
 332     * allocations can fail or cause buffer movement failures in the kernel.
 333     */
 334    ws->info.max_alloc_size = MIN2(ws->info.vram_size * 0.9, ws->info.gart_size * 0.7);
 335    /* convert the shader clock from KHz to MHz */
 336    ws->info.max_shader_clock = ws->amdinfo.max_engine_clk / 1000;
 337    ws->info.max_se = ws->amdinfo.num_shader_engines;
 338    ws->info.max_sh_per_se = ws->amdinfo.num_shader_arrays_per_engine;
 339    ws->info.has_uvd = uvd.available_rings != 0;
 340    ws->info.uvd_fw_version =
 341          uvd.available_rings ? uvd_version : 0;
 342    ws->info.vce_fw_version =
 343          vce.available_rings ? vce_version : 0;
 344    ws->info.has_userptr = true;
 345    ws->info.num_render_backends = ws->amdinfo.rb_pipes;
 346    ws->info.clock_crystal_freq = ws->amdinfo.gpu_counter_freq;
 347    ws->info.tcc_cache_line_size = 64; /* TC L2 line size on GCN */
 348    ws->info.num_tile_pipes = cik_get_num_tile_pipes(&ws->amdinfo);
 349    ws->info.pipe_interleave_bytes = 256 << ((ws->amdinfo.gb_addr_cfg >> 4) & 0x7);
 350    ws->info.has_virtual_memory = true;
 351    ws->info.has_sdma = dma.available_rings != 0;
 352
 353    /* Get the number of good compute units. */
 354    ws->info.num_good_compute_units = 0;
 355    for (i = 0; i < ws->info.max_se; i++)
 356       for (j = 0; j < ws->info.max_sh_per_se; j++)
 357          ws->info.num_good_compute_units +=
 358             util_bitcount(ws->amdinfo.cu_bitmap[i][j]);
 359
 360    memcpy(ws->info.si_tile_mode_array, ws->amdinfo.gb_tile_mode,
 361           sizeof(ws->amdinfo.gb_tile_mode));
 362    ws->info.enabled_rb_mask = ws->amdinfo.enabled_rb_pipes_mask;
 363
 364    memcpy(ws->info.cik_macrotile_mode_array, ws->amdinfo.gb_macro_tile_mode,
 365           sizeof(ws->amdinfo.gb_macro_tile_mode));
 366
 367    ws->info.gart_page_size = alignment_info.size_remote;
 368
 369    if (ws->info.chip_class == SI)
 370       ws->info.gfx_ib_pad_with_type2 = TRUE;
 371
 372    ws->check_vm = strstr(debug_get_option("R600_DEBUG", ""), "check_vm") != NULL;
 373
 374    return true;
 375
 376 fail:
 377    if (ws->addrlib)
 378       AddrDestroy(ws->addrlib);
 379    amdgpu_device_deinitialize(ws->dev);
 380    ws->dev = NULL;
 381    return false;
 382 }
 383
 384 static void do_winsys_deinit(struct amdgpu_winsys *ws)
 385 {
 386    AddrDestroy(ws->addrlib);
 387    amdgpu_device_deinitialize(ws->dev);
 388 }
 389
 390 static void amdgpu_winsys_destroy(struct radeon_winsys *rws)
 391 {
 392    struct amdgpu_winsys *ws = (struct amdgpu_winsys*)rws;
 393
 394    if (util_queue_is_initialized(&ws->cs_queue))
 395       util_queue_destroy(&ws->cs_queue);
 396
 397    mtx_destroy(&ws->bo_fence_lock);
 398    pb_slabs_deinit(&ws->bo_slabs);
 399    pb_cache_deinit(&ws->bo_cache);
 400    mtx_destroy(&ws->global_bo_list_lock);
 401    do_winsys_deinit(ws);
 402    FREE(rws);
 403 }
 404
 405 static void amdgpu_winsys_query_info(struct radeon_winsys *rws,
 406                                      struct radeon_info *info)
 407 {
 408    *info = ((struct amdgpu_winsys *)rws)->info;
 409 }
 410
 411 static bool amdgpu_cs_request_feature(struct radeon_winsys_cs *rcs,
 412                                       enum radeon_feature_id fid,
 413                                       bool enable)
 414 {
 415    return false;
 416 }
 417
 418 static uint64_t amdgpu_query_value(struct radeon_winsys *rws,
 419                                    enum radeon_value_id value)
 420 {
 421    struct amdgpu_winsys *ws = (struct amdgpu_winsys*)rws;
 422    struct amdgpu_heap_info heap;
 423    uint64_t retval = 0;
 424
 425    switch (value) {
 426    case RADEON_REQUESTED_VRAM_MEMORY:
 427       return ws->allocated_vram;
 428    case RADEON_REQUESTED_GTT_MEMORY:
 429       return ws->allocated_gtt;
 430    case RADEON_MAPPED_VRAM:
 431       return ws->mapped_vram;
 432    case RADEON_MAPPED_GTT:
 433       return ws->mapped_gtt;
 434    case RADEON_BUFFER_WAIT_TIME_NS:
 435       return ws->buffer_wait_time;
 436    case RADEON_NUM_MAPPED_BUFFERS:
 437       return ws->num_mapped_buffers;
 438    case RADEON_TIMESTAMP:
 439       amdgpu_query_info(ws->dev, AMDGPU_INFO_TIMESTAMP, 8, &retval);
 440       return retval;
 441    case RADEON_NUM_GFX_IBS:
 442       return ws->num_gfx_IBs;
 443    case RADEON_NUM_SDMA_IBS:
 444       return ws->num_sdma_IBs;
 445    case RADEON_NUM_BYTES_MOVED:
 446       amdgpu_query_info(ws->dev, AMDGPU_INFO_NUM_BYTES_MOVED, 8, &retval);
 447       return retval;
 448    case RADEON_NUM_EVICTIONS:
 449       amdgpu_query_info(ws->dev, AMDGPU_INFO_NUM_EVICTIONS, 8, &retval);
 450       return retval;
 451    case RADEON_VRAM_USAGE:
 452       amdgpu_query_heap_info(ws->dev, AMDGPU_GEM_DOMAIN_VRAM, 0, &heap);
 453       return heap.heap_usage;
 454    case RADEON_VRAM_VIS_USAGE:
 455       amdgpu_query_heap_info(ws->dev, AMDGPU_GEM_DOMAIN_VRAM,
 456                              AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED, &heap);
 457       return heap.heap_usage;
 458    case RADEON_GTT_USAGE:
 459       amdgpu_query_heap_info(ws->dev, AMDGPU_GEM_DOMAIN_GTT, 0, &heap);
 460       return heap.heap_usage;
 461    case RADEON_GPU_TEMPERATURE:
 462    case RADEON_CURRENT_SCLK:
 463    case RADEON_CURRENT_MCLK:
 464       return 0;
 465    case RADEON_GPU_RESET_COUNTER:
 466       assert(0);
 467       return 0;
 468    case RADEON_CS_THREAD_TIME:
 469       return util_queue_get_thread_time_nano(&ws->cs_queue, 0);
 470    }
 471    return 0;
 472 }
 473
 474 static bool amdgpu_read_registers(struct radeon_winsys *rws,
 475                                   unsigned reg_offset,
 476                                   unsigned num_registers, uint32_t *out)
 477 {
 478    struct amdgpu_winsys *ws = (struct amdgpu_winsys*)rws;
 479
 480    return amdgpu_read_mm_registers(ws->dev, reg_offset / 4, num_registers,
 481                                    0xffffffff, 0, out) == 0;
 482 }
 483
 484 static unsigned hash_dev(void *key)
 485 {
 486 #if defined(PIPE_ARCH_X86_64)
 487    return pointer_to_intptr(key) ^ (pointer_to_intptr(key) >> 32);
 488 #else
 489    return pointer_to_intptr(key);
 490 #endif
 491 }
 492
 493 static int compare_dev(void *key1, void *key2)
 494 {
 495    return key1 != key2;
 496 }
 497
 498 static bool amdgpu_winsys_unref(struct radeon_winsys *rws)
 499 {
 500    struct amdgpu_winsys *ws = (struct amdgpu_winsys*)rws;
 501    bool destroy;
 502
 503    /* When the reference counter drops to zero, remove the device pointer
 504     * from the table.
 505     * This must happen while the mutex is locked, so that
 506     * amdgpu_winsys_create in another thread doesn't get the winsys
 507     * from the table when the counter drops to 0. */
 508    mtx_lock(&dev_tab_mutex);
 509
 510    destroy = pipe_reference(&ws->reference, NULL);
 511    if (destroy && dev_tab)
 512       util_hash_table_remove(dev_tab, ws->dev);
 513
 514    mtx_unlock(&dev_tab_mutex);
 515    return destroy;
 516 }
 517
 518 PUBLIC struct radeon_winsys *
 519 amdgpu_winsys_create(int fd, radeon_screen_create_t screen_create)
 520 {
 521    struct amdgpu_winsys *ws;
 522    drmVersionPtr version = drmGetVersion(fd);
 523    amdgpu_device_handle dev;
 524    uint32_t drm_major, drm_minor, r;
 525
 526    /* The DRM driver version of amdgpu is 3.x.x. */
 527    if (version->version_major != 3) {
 528       drmFreeVersion(version);
 529       return NULL;
 530    }
 531    drmFreeVersion(version);
 532
 533    /* Look up the winsys from the dev table. */
 534    mtx_lock(&dev_tab_mutex);
 535    if (!dev_tab)
 536       dev_tab = util_hash_table_create(hash_dev, compare_dev);
 537
 538    /* Initialize the amdgpu device. This should always return the same pointer
 539     * for the same fd. */
 540    r = amdgpu_device_initialize(fd, &drm_major, &drm_minor, &dev);
 541    if (r) {
 542       mtx_unlock(&dev_tab_mutex);
 543       fprintf(stderr, "amdgpu: amdgpu_device_initialize failed.\n");
 544       return NULL;
 545    }
 546
 547    /* Lookup a winsys if we have already created one for this device. */
 548    ws = util_hash_table_get(dev_tab, dev);
 549    if (ws) {
 550       pipe_reference(NULL, &ws->reference);
 551       mtx_unlock(&dev_tab_mutex);
 552       return &ws->base;
 553    }
 554
 555    /* Create a new winsys. */
 556    ws = CALLOC_STRUCT(amdgpu_winsys);
 557    if (!ws)
 558       goto fail;
 559
 560    ws->dev = dev;
 561    ws->info.drm_major = drm_major;
 562    ws->info.drm_minor = drm_minor;
 563
 564    if (!do_winsys_init(ws, fd))
 565       goto fail_alloc;
 566
 567    /* Create managers. */
 568    pb_cache_init(&ws->bo_cache, 500000, ws->check_vm ? 1.0f : 2.0f, 0,
 569                  (ws->info.vram_size + ws->info.gart_size) / 8,
 570                  amdgpu_bo_destroy, amdgpu_bo_can_reclaim);
 571
 572    if (!pb_slabs_init(&ws->bo_slabs,
 573                       AMDGPU_SLAB_MIN_SIZE_LOG2, AMDGPU_SLAB_MAX_SIZE_LOG2,
 574                       12, /* number of heaps (domain/flags combinations) */
 575                       ws,
 576                       amdgpu_bo_can_reclaim_slab,
 577                       amdgpu_bo_slab_alloc,
 578                       amdgpu_bo_slab_free))
 579       goto fail_cache;
 580
 581    ws->info.min_alloc_size = 1 << AMDGPU_SLAB_MIN_SIZE_LOG2;
 582
 583    /* init reference */
 584    pipe_reference_init(&ws->reference, 1);
 585
 586    /* Set functions. */
 587    ws->base.unref = amdgpu_winsys_unref;
 588    ws->base.destroy = amdgpu_winsys_destroy;
 589    ws->base.query_info = amdgpu_winsys_query_info;
 590    ws->base.cs_request_feature = amdgpu_cs_request_feature;
 591    ws->base.query_value = amdgpu_query_value;
 592    ws->base.read_registers = amdgpu_read_registers;
 593
 594    amdgpu_bo_init_functions(ws);
 595    amdgpu_cs_init_functions(ws);
 596    amdgpu_surface_init_functions(ws);
 597
 598    LIST_INITHEAD(&ws->global_bo_list);
 599    (void) mtx_init(&ws->global_bo_list_lock, mtx_plain);
 600    (void) mtx_init(&ws->bo_fence_lock, mtx_plain);
 601
 602    if (!util_queue_init(&ws->cs_queue, "amdgpu_cs", 8, 1)) {
 603       amdgpu_winsys_destroy(&ws->base);
 604       mtx_unlock(&dev_tab_mutex);
 605       return NULL;
 606    }
 607
 608    /* Create the screen at the end. The winsys must be initialized
 609     * completely.
 610     *
 611     * Alternatively, we could create the screen based on "ws->gen"
 612     * and link all drivers into one binary blob. */
 613    ws->base.screen = screen_create(&ws->base);
 614    if (!ws->base.screen) {
 615       amdgpu_winsys_destroy(&ws->base);
 616       mtx_unlock(&dev_tab_mutex);
 617       return NULL;
 618    }
 619
 620    util_hash_table_set(dev_tab, dev, ws);
 621
 622    /* We must unlock the mutex once the winsys is fully initialized, so that
 623     * other threads attempting to create the winsys from the same fd will
 624     * get a fully initialized winsys and not just half-way initialized. */
 625    mtx_unlock(&dev_tab_mutex);
 626
 627    return &ws->base;
 628
 629 fail_cache:
 630    pb_cache_deinit(&ws->bo_cache);
 631    do_winsys_deinit(ws);
 632 fail_alloc:
 633    FREE(ws);
 634 fail:
 635    mtx_unlock(&dev_tab_mutex);
 636    return NULL;
 637 }