2 * Copyright © 2009 Corbin Simpson <MostAwesomeDude@gmail.com>
3 * Copyright © 2009 Joakim Sindholt <opensource@zhasha.com>
4 * Copyright © 2011 Marek Olšák <maraeo@gmail.com>
5 * Copyright © 2015 Advanced Micro Devices, Inc.
8 * Permission is hereby granted, free of charge, to any person obtaining
9 * a copy of this software and associated documentation files (the
10 * "Software"), to deal in the Software without restriction, including
11 * without limitation the rights to use, copy, modify, merge, publish,
12 * distribute, sub license, and/or sell copies of the Software, and to
13 * permit persons to whom the Software is furnished to do so, subject to
14 * the following conditions:
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
17 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
18 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
19 * NON-INFRINGEMENT. IN NO EVENT SHALL THE COPYRIGHT HOLDERS, AUTHORS
20 * AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
21 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
22 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
23 * USE OR OTHER DEALINGS IN THE SOFTWARE.
25 * The above copyright notice and this permission notice (including the
26 * next paragraph) shall be included in all copies or substantial portions
31 * Marek Olšák <maraeo@gmail.com>
34 #include "amdgpu_cs.h"
35 #include "amdgpu_public.h"
37 #include "util/u_hash_table.h"
38 #include <amdgpu_drm.h>
42 #include "amd/common/amdgpu_id.h"
43 #include "amd/common/sid.h"
44 #include "amd/common/gfx9d.h"
46 #define CIK_TILE_MODE_COLOR_2D 14
48 #define CIK__GB_TILE_MODE__PIPE_CONFIG(x) (((x) >> 6) & 0x1f)
49 #define CIK__PIPE_CONFIG__ADDR_SURF_P2 0
50 #define CIK__PIPE_CONFIG__ADDR_SURF_P4_8x16 4
51 #define CIK__PIPE_CONFIG__ADDR_SURF_P4_16x16 5
52 #define CIK__PIPE_CONFIG__ADDR_SURF_P4_16x32 6
53 #define CIK__PIPE_CONFIG__ADDR_SURF_P4_32x32 7
54 #define CIK__PIPE_CONFIG__ADDR_SURF_P8_16x16_8x16 8
55 #define CIK__PIPE_CONFIG__ADDR_SURF_P8_16x32_8x16 9
56 #define CIK__PIPE_CONFIG__ADDR_SURF_P8_32x32_8x16 10
57 #define CIK__PIPE_CONFIG__ADDR_SURF_P8_16x32_16x16 11
58 #define CIK__PIPE_CONFIG__ADDR_SURF_P8_32x32_16x16 12
59 #define CIK__PIPE_CONFIG__ADDR_SURF_P8_32x32_16x32 13
60 #define CIK__PIPE_CONFIG__ADDR_SURF_P8_32x64_32x32 14
61 #define CIK__PIPE_CONFIG__ADDR_SURF_P16_32X32_8X16 16
62 #define CIK__PIPE_CONFIG__ADDR_SURF_P16_32X32_16X16 17
64 static struct util_hash_table
*dev_tab
= NULL
;
65 static mtx_t dev_tab_mutex
= _MTX_INITIALIZER_NP
;
67 static unsigned cik_get_num_tile_pipes(struct amdgpu_gpu_info
*info
)
69 unsigned mode2d
= info
->gb_tile_mode
[CIK_TILE_MODE_COLOR_2D
];
71 switch (CIK__GB_TILE_MODE__PIPE_CONFIG(mode2d
)) {
72 case CIK__PIPE_CONFIG__ADDR_SURF_P2
:
74 case CIK__PIPE_CONFIG__ADDR_SURF_P4_8x16
:
75 case CIK__PIPE_CONFIG__ADDR_SURF_P4_16x16
:
76 case CIK__PIPE_CONFIG__ADDR_SURF_P4_16x32
:
77 case CIK__PIPE_CONFIG__ADDR_SURF_P4_32x32
:
79 case CIK__PIPE_CONFIG__ADDR_SURF_P8_16x16_8x16
:
80 case CIK__PIPE_CONFIG__ADDR_SURF_P8_16x32_8x16
:
81 case CIK__PIPE_CONFIG__ADDR_SURF_P8_32x32_8x16
:
82 case CIK__PIPE_CONFIG__ADDR_SURF_P8_16x32_16x16
:
83 case CIK__PIPE_CONFIG__ADDR_SURF_P8_32x32_16x16
:
84 case CIK__PIPE_CONFIG__ADDR_SURF_P8_32x32_16x32
:
85 case CIK__PIPE_CONFIG__ADDR_SURF_P8_32x64_32x32
:
87 case CIK__PIPE_CONFIG__ADDR_SURF_P16_32X32_8X16
:
88 case CIK__PIPE_CONFIG__ADDR_SURF_P16_32X32_16X16
:
91 fprintf(stderr
, "Invalid CIK pipe configuration, assuming P2\n");
92 assert(!"this should never occur");
97 /* Helper function to do the ioctls needed for setup and init. */
98 static bool do_winsys_init(struct amdgpu_winsys
*ws
, int fd
)
100 struct amdgpu_buffer_size_alignments alignment_info
= {};
101 struct amdgpu_heap_info vram
, vram_vis
, gtt
;
102 struct drm_amdgpu_info_hw_ip dma
= {}, uvd
= {}, vce
= {};
103 uint32_t vce_version
= 0, vce_feature
= 0, uvd_version
= 0, uvd_feature
= 0;
104 uint32_t unused_feature
;
106 drmDevicePtr devinfo
;
109 r
= drmGetDevice2(fd
, 0, &devinfo
);
111 fprintf(stderr
, "amdgpu: drmGetDevice2 failed.\n");
114 ws
->info
.pci_domain
= devinfo
->businfo
.pci
->domain
;
115 ws
->info
.pci_bus
= devinfo
->businfo
.pci
->bus
;
116 ws
->info
.pci_dev
= devinfo
->businfo
.pci
->dev
;
117 ws
->info
.pci_func
= devinfo
->businfo
.pci
->func
;
118 drmFreeDevice(&devinfo
);
120 /* Query hardware and driver information. */
121 r
= amdgpu_query_gpu_info(ws
->dev
, &ws
->amdinfo
);
123 fprintf(stderr
, "amdgpu: amdgpu_query_gpu_info failed.\n");
127 r
= amdgpu_query_buffer_size_alignment(ws
->dev
, &alignment_info
);
129 fprintf(stderr
, "amdgpu: amdgpu_query_buffer_size_alignment failed.\n");
133 r
= amdgpu_query_heap_info(ws
->dev
, AMDGPU_GEM_DOMAIN_VRAM
, 0, &vram
);
135 fprintf(stderr
, "amdgpu: amdgpu_query_heap_info(vram) failed.\n");
139 r
= amdgpu_query_heap_info(ws
->dev
, AMDGPU_GEM_DOMAIN_VRAM
,
140 AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED
,
143 fprintf(stderr
, "amdgpu: amdgpu_query_heap_info(vram_vis) failed.\n");
147 r
= amdgpu_query_heap_info(ws
->dev
, AMDGPU_GEM_DOMAIN_GTT
, 0, >t
);
149 fprintf(stderr
, "amdgpu: amdgpu_query_heap_info(gtt) failed.\n");
153 r
= amdgpu_query_hw_ip_info(ws
->dev
, AMDGPU_HW_IP_DMA
, 0, &dma
);
155 fprintf(stderr
, "amdgpu: amdgpu_query_hw_ip_info(dma) failed.\n");
159 r
= amdgpu_query_hw_ip_info(ws
->dev
, AMDGPU_HW_IP_UVD
, 0, &uvd
);
161 fprintf(stderr
, "amdgpu: amdgpu_query_hw_ip_info(uvd) failed.\n");
165 r
= amdgpu_query_firmware_version(ws
->dev
, AMDGPU_INFO_FW_GFX_ME
, 0, 0,
166 &ws
->info
.me_fw_version
, &unused_feature
);
168 fprintf(stderr
, "amdgpu: amdgpu_query_firmware_version(me) failed.\n");
172 r
= amdgpu_query_firmware_version(ws
->dev
, AMDGPU_INFO_FW_GFX_PFP
, 0, 0,
173 &ws
->info
.pfp_fw_version
, &unused_feature
);
175 fprintf(stderr
, "amdgpu: amdgpu_query_firmware_version(pfp) failed.\n");
179 r
= amdgpu_query_firmware_version(ws
->dev
, AMDGPU_INFO_FW_GFX_CE
, 0, 0,
180 &ws
->info
.ce_fw_version
, &unused_feature
);
182 fprintf(stderr
, "amdgpu: amdgpu_query_firmware_version(ce) failed.\n");
186 r
= amdgpu_query_firmware_version(ws
->dev
, AMDGPU_INFO_FW_UVD
, 0, 0,
187 &uvd_version
, &uvd_feature
);
189 fprintf(stderr
, "amdgpu: amdgpu_query_firmware_version(uvd) failed.\n");
193 r
= amdgpu_query_hw_ip_info(ws
->dev
, AMDGPU_HW_IP_VCE
, 0, &vce
);
195 fprintf(stderr
, "amdgpu: amdgpu_query_hw_ip_info(vce) failed.\n");
199 r
= amdgpu_query_firmware_version(ws
->dev
, AMDGPU_INFO_FW_VCE
, 0, 0,
200 &vce_version
, &vce_feature
);
202 fprintf(stderr
, "amdgpu: amdgpu_query_firmware_version(vce) failed.\n");
206 /* Set chip identification. */
207 ws
->info
.pci_id
= ws
->amdinfo
.asic_id
; /* TODO: is this correct? */
208 ws
->info
.vce_harvest_config
= ws
->amdinfo
.vce_harvest_config
;
210 switch (ws
->info
.pci_id
) {
211 #define CHIPSET(pci_id, name, cfamily) case pci_id: ws->info.family = CHIP_##cfamily; break;
212 #include "pci_ids/radeonsi_pci_ids.h"
216 fprintf(stderr
, "amdgpu: Invalid PCI ID.\n");
220 if (ws
->info
.family
>= CHIP_VEGA10
)
221 ws
->info
.chip_class
= GFX9
;
222 else if (ws
->info
.family
>= CHIP_TONGA
)
223 ws
->info
.chip_class
= VI
;
224 else if (ws
->info
.family
>= CHIP_BONAIRE
)
225 ws
->info
.chip_class
= CIK
;
226 else if (ws
->info
.family
>= CHIP_TAHITI
)
227 ws
->info
.chip_class
= SI
;
229 fprintf(stderr
, "amdgpu: Unknown family.\n");
233 /* LLVM 5.0 is required for GFX9. */
234 if (ws
->info
.chip_class
>= GFX9
&& HAVE_LLVM
< 0x0500) {
235 fprintf(stderr
, "amdgpu: LLVM 5.0 is required, got LLVM %i.%i\n",
236 HAVE_LLVM
>> 8, HAVE_LLVM
& 255);
240 /* family and rev_id are for addrlib */
241 switch (ws
->info
.family
) {
243 ws
->family
= FAMILY_SI
;
244 ws
->rev_id
= SI_TAHITI_P_A0
;
247 ws
->family
= FAMILY_SI
;
248 ws
->rev_id
= SI_PITCAIRN_PM_A0
;
251 ws
->family
= FAMILY_SI
;
252 ws
->rev_id
= SI_CAPEVERDE_M_A0
;
255 ws
->family
= FAMILY_SI
;
256 ws
->rev_id
= SI_OLAND_M_A0
;
259 ws
->family
= FAMILY_SI
;
260 ws
->rev_id
= SI_HAINAN_V_A0
;
263 ws
->family
= FAMILY_CI
;
264 ws
->rev_id
= CI_BONAIRE_M_A0
;
267 ws
->family
= FAMILY_KV
;
268 ws
->rev_id
= KV_SPECTRE_A0
;
271 ws
->family
= FAMILY_KV
;
272 ws
->rev_id
= KB_KALINDI_A0
;
275 ws
->family
= FAMILY_CI
;
276 ws
->rev_id
= CI_HAWAII_P_A0
;
279 ws
->family
= FAMILY_KV
;
280 ws
->rev_id
= ML_GODAVARI_A0
;
283 ws
->family
= FAMILY_VI
;
284 ws
->rev_id
= VI_TONGA_P_A0
;
287 ws
->family
= FAMILY_VI
;
288 ws
->rev_id
= VI_ICELAND_M_A0
;
291 ws
->family
= FAMILY_CZ
;
292 ws
->rev_id
= CARRIZO_A0
;
295 ws
->family
= FAMILY_CZ
;
296 ws
->rev_id
= STONEY_A0
;
299 ws
->family
= FAMILY_VI
;
300 ws
->rev_id
= VI_FIJI_P_A0
;
303 ws
->family
= FAMILY_VI
;
304 ws
->rev_id
= VI_POLARIS10_P_A0
;
307 ws
->family
= FAMILY_VI
;
308 ws
->rev_id
= VI_POLARIS11_M_A0
;
311 ws
->family
= FAMILY_VI
;
312 ws
->rev_id
= VI_POLARIS12_V_A0
;
315 ws
->family
= FAMILY_AI
;
316 ws
->rev_id
= AI_VEGA10_P_A0
;
319 fprintf(stderr
, "amdgpu: Unknown family.\n");
323 ws
->addrlib
= amdgpu_addr_create(ws
);
325 fprintf(stderr
, "amdgpu: Cannot create addrlib.\n");
329 /* Set which chips have dedicated VRAM. */
330 ws
->info
.has_dedicated_vram
=
331 !(ws
->amdinfo
.ids_flags
& AMDGPU_IDS_FLAGS_FUSION
);
333 /* Set hardware information. */
334 ws
->info
.gart_size
= gtt
.heap_size
;
335 ws
->info
.vram_size
= vram
.heap_size
;
336 ws
->info
.vram_vis_size
= vram_vis
.heap_size
;
337 /* The kernel can split large buffers in VRAM but not in GTT, so large
338 * allocations can fail or cause buffer movement failures in the kernel.
340 ws
->info
.max_alloc_size
= MIN2(ws
->info
.vram_size
* 0.9, ws
->info
.gart_size
* 0.7);
341 /* convert the shader clock from KHz to MHz */
342 ws
->info
.max_shader_clock
= ws
->amdinfo
.max_engine_clk
/ 1000;
343 ws
->info
.max_se
= ws
->amdinfo
.num_shader_engines
;
344 ws
->info
.max_sh_per_se
= ws
->amdinfo
.num_shader_arrays_per_engine
;
345 ws
->info
.has_uvd
= uvd
.available_rings
!= 0;
346 ws
->info
.uvd_fw_version
=
347 uvd
.available_rings
? uvd_version
: 0;
348 ws
->info
.vce_fw_version
=
349 vce
.available_rings
? vce_version
: 0;
350 ws
->info
.has_userptr
= true;
351 ws
->info
.num_render_backends
= ws
->amdinfo
.rb_pipes
;
352 ws
->info
.clock_crystal_freq
= ws
->amdinfo
.gpu_counter_freq
;
353 ws
->info
.tcc_cache_line_size
= 64; /* TC L2 line size on GCN */
354 if (ws
->info
.chip_class
== GFX9
) {
355 ws
->info
.num_tile_pipes
= 1 << G_0098F8_NUM_PIPES(ws
->amdinfo
.gb_addr_cfg
);
356 ws
->info
.pipe_interleave_bytes
=
357 256 << G_0098F8_PIPE_INTERLEAVE_SIZE_GFX9(ws
->amdinfo
.gb_addr_cfg
);
359 ws
->info
.num_tile_pipes
= cik_get_num_tile_pipes(&ws
->amdinfo
);
360 ws
->info
.pipe_interleave_bytes
=
361 256 << G_0098F8_PIPE_INTERLEAVE_SIZE_GFX6(ws
->amdinfo
.gb_addr_cfg
);
363 ws
->info
.has_virtual_memory
= true;
364 ws
->info
.has_sdma
= dma
.available_rings
!= 0;
366 /* Get the number of good compute units. */
367 ws
->info
.num_good_compute_units
= 0;
368 for (i
= 0; i
< ws
->info
.max_se
; i
++)
369 for (j
= 0; j
< ws
->info
.max_sh_per_se
; j
++)
370 ws
->info
.num_good_compute_units
+=
371 util_bitcount(ws
->amdinfo
.cu_bitmap
[i
][j
]);
373 memcpy(ws
->info
.si_tile_mode_array
, ws
->amdinfo
.gb_tile_mode
,
374 sizeof(ws
->amdinfo
.gb_tile_mode
));
375 ws
->info
.enabled_rb_mask
= ws
->amdinfo
.enabled_rb_pipes_mask
;
377 memcpy(ws
->info
.cik_macrotile_mode_array
, ws
->amdinfo
.gb_macro_tile_mode
,
378 sizeof(ws
->amdinfo
.gb_macro_tile_mode
));
380 ws
->info
.gart_page_size
= alignment_info
.size_remote
;
382 if (ws
->info
.chip_class
== SI
)
383 ws
->info
.gfx_ib_pad_with_type2
= TRUE
;
385 ws
->check_vm
= strstr(debug_get_option("R600_DEBUG", ""), "check_vm") != NULL
;
391 AddrDestroy(ws
->addrlib
);
392 amdgpu_device_deinitialize(ws
->dev
);
397 static void do_winsys_deinit(struct amdgpu_winsys
*ws
)
399 AddrDestroy(ws
->addrlib
);
400 amdgpu_device_deinitialize(ws
->dev
);
403 static void amdgpu_winsys_destroy(struct radeon_winsys
*rws
)
405 struct amdgpu_winsys
*ws
= (struct amdgpu_winsys
*)rws
;
407 if (util_queue_is_initialized(&ws
->cs_queue
))
408 util_queue_destroy(&ws
->cs_queue
);
410 mtx_destroy(&ws
->bo_fence_lock
);
411 pb_slabs_deinit(&ws
->bo_slabs
);
412 pb_cache_deinit(&ws
->bo_cache
);
413 mtx_destroy(&ws
->global_bo_list_lock
);
414 do_winsys_deinit(ws
);
418 static void amdgpu_winsys_query_info(struct radeon_winsys
*rws
,
419 struct radeon_info
*info
)
421 *info
= ((struct amdgpu_winsys
*)rws
)->info
;
424 static bool amdgpu_cs_request_feature(struct radeon_winsys_cs
*rcs
,
425 enum radeon_feature_id fid
,
431 static uint64_t amdgpu_query_value(struct radeon_winsys
*rws
,
432 enum radeon_value_id value
)
434 struct amdgpu_winsys
*ws
= (struct amdgpu_winsys
*)rws
;
435 struct amdgpu_heap_info heap
;
439 case RADEON_REQUESTED_VRAM_MEMORY
:
440 return ws
->allocated_vram
;
441 case RADEON_REQUESTED_GTT_MEMORY
:
442 return ws
->allocated_gtt
;
443 case RADEON_MAPPED_VRAM
:
444 return ws
->mapped_vram
;
445 case RADEON_MAPPED_GTT
:
446 return ws
->mapped_gtt
;
447 case RADEON_BUFFER_WAIT_TIME_NS
:
448 return ws
->buffer_wait_time
;
449 case RADEON_NUM_MAPPED_BUFFERS
:
450 return ws
->num_mapped_buffers
;
451 case RADEON_TIMESTAMP
:
452 amdgpu_query_info(ws
->dev
, AMDGPU_INFO_TIMESTAMP
, 8, &retval
);
454 case RADEON_NUM_GFX_IBS
:
455 return ws
->num_gfx_IBs
;
456 case RADEON_NUM_SDMA_IBS
:
457 return ws
->num_sdma_IBs
;
458 case RADEON_NUM_BYTES_MOVED
:
459 amdgpu_query_info(ws
->dev
, AMDGPU_INFO_NUM_BYTES_MOVED
, 8, &retval
);
461 case RADEON_NUM_EVICTIONS
:
462 amdgpu_query_info(ws
->dev
, AMDGPU_INFO_NUM_EVICTIONS
, 8, &retval
);
464 case RADEON_VRAM_USAGE
:
465 amdgpu_query_heap_info(ws
->dev
, AMDGPU_GEM_DOMAIN_VRAM
, 0, &heap
);
466 return heap
.heap_usage
;
467 case RADEON_VRAM_VIS_USAGE
:
468 amdgpu_query_heap_info(ws
->dev
, AMDGPU_GEM_DOMAIN_VRAM
,
469 AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED
, &heap
);
470 return heap
.heap_usage
;
471 case RADEON_GTT_USAGE
:
472 amdgpu_query_heap_info(ws
->dev
, AMDGPU_GEM_DOMAIN_GTT
, 0, &heap
);
473 return heap
.heap_usage
;
474 case RADEON_GPU_TEMPERATURE
:
475 amdgpu_query_sensor_info(ws
->dev
, AMDGPU_INFO_SENSOR_GPU_TEMP
, 4, &retval
);
477 case RADEON_CURRENT_SCLK
:
478 amdgpu_query_sensor_info(ws
->dev
, AMDGPU_INFO_SENSOR_GFX_SCLK
, 4, &retval
);
480 case RADEON_CURRENT_MCLK
:
481 amdgpu_query_sensor_info(ws
->dev
, AMDGPU_INFO_SENSOR_GFX_MCLK
, 4, &retval
);
483 case RADEON_GPU_RESET_COUNTER
:
486 case RADEON_CS_THREAD_TIME
:
487 return util_queue_get_thread_time_nano(&ws
->cs_queue
, 0);
492 static bool amdgpu_read_registers(struct radeon_winsys
*rws
,
494 unsigned num_registers
, uint32_t *out
)
496 struct amdgpu_winsys
*ws
= (struct amdgpu_winsys
*)rws
;
498 return amdgpu_read_mm_registers(ws
->dev
, reg_offset
/ 4, num_registers
,
499 0xffffffff, 0, out
) == 0;
502 static unsigned hash_dev(void *key
)
504 #if defined(PIPE_ARCH_X86_64)
505 return pointer_to_intptr(key
) ^ (pointer_to_intptr(key
) >> 32);
507 return pointer_to_intptr(key
);
511 static int compare_dev(void *key1
, void *key2
)
516 static bool amdgpu_winsys_unref(struct radeon_winsys
*rws
)
518 struct amdgpu_winsys
*ws
= (struct amdgpu_winsys
*)rws
;
521 /* When the reference counter drops to zero, remove the device pointer
523 * This must happen while the mutex is locked, so that
524 * amdgpu_winsys_create in another thread doesn't get the winsys
525 * from the table when the counter drops to 0. */
526 mtx_lock(&dev_tab_mutex
);
528 destroy
= pipe_reference(&ws
->reference
, NULL
);
529 if (destroy
&& dev_tab
)
530 util_hash_table_remove(dev_tab
, ws
->dev
);
532 mtx_unlock(&dev_tab_mutex
);
536 PUBLIC
struct radeon_winsys
*
537 amdgpu_winsys_create(int fd
, radeon_screen_create_t screen_create
)
539 struct amdgpu_winsys
*ws
;
540 drmVersionPtr version
= drmGetVersion(fd
);
541 amdgpu_device_handle dev
;
542 uint32_t drm_major
, drm_minor
, r
;
544 /* The DRM driver version of amdgpu is 3.x.x. */
545 if (version
->version_major
!= 3) {
546 drmFreeVersion(version
);
549 drmFreeVersion(version
);
551 /* Look up the winsys from the dev table. */
552 mtx_lock(&dev_tab_mutex
);
554 dev_tab
= util_hash_table_create(hash_dev
, compare_dev
);
556 /* Initialize the amdgpu device. This should always return the same pointer
557 * for the same fd. */
558 r
= amdgpu_device_initialize(fd
, &drm_major
, &drm_minor
, &dev
);
560 mtx_unlock(&dev_tab_mutex
);
561 fprintf(stderr
, "amdgpu: amdgpu_device_initialize failed.\n");
565 /* Lookup a winsys if we have already created one for this device. */
566 ws
= util_hash_table_get(dev_tab
, dev
);
568 pipe_reference(NULL
, &ws
->reference
);
569 mtx_unlock(&dev_tab_mutex
);
573 /* Create a new winsys. */
574 ws
= CALLOC_STRUCT(amdgpu_winsys
);
579 ws
->info
.drm_major
= drm_major
;
580 ws
->info
.drm_minor
= drm_minor
;
582 if (!do_winsys_init(ws
, fd
))
585 /* Create managers. */
586 pb_cache_init(&ws
->bo_cache
, 500000, ws
->check_vm
? 1.0f
: 2.0f
, 0,
587 (ws
->info
.vram_size
+ ws
->info
.gart_size
) / 8,
588 amdgpu_bo_destroy
, amdgpu_bo_can_reclaim
);
590 if (!pb_slabs_init(&ws
->bo_slabs
,
591 AMDGPU_SLAB_MIN_SIZE_LOG2
, AMDGPU_SLAB_MAX_SIZE_LOG2
,
592 12, /* number of heaps (domain/flags combinations) */
594 amdgpu_bo_can_reclaim_slab
,
595 amdgpu_bo_slab_alloc
,
596 amdgpu_bo_slab_free
))
599 ws
->info
.min_alloc_size
= 1 << AMDGPU_SLAB_MIN_SIZE_LOG2
;
602 pipe_reference_init(&ws
->reference
, 1);
605 ws
->base
.unref
= amdgpu_winsys_unref
;
606 ws
->base
.destroy
= amdgpu_winsys_destroy
;
607 ws
->base
.query_info
= amdgpu_winsys_query_info
;
608 ws
->base
.cs_request_feature
= amdgpu_cs_request_feature
;
609 ws
->base
.query_value
= amdgpu_query_value
;
610 ws
->base
.read_registers
= amdgpu_read_registers
;
612 amdgpu_bo_init_functions(ws
);
613 amdgpu_cs_init_functions(ws
);
614 amdgpu_surface_init_functions(ws
);
616 LIST_INITHEAD(&ws
->global_bo_list
);
617 (void) mtx_init(&ws
->global_bo_list_lock
, mtx_plain
);
618 (void) mtx_init(&ws
->bo_fence_lock
, mtx_plain
);
620 if (!util_queue_init(&ws
->cs_queue
, "amdgpu_cs", 8, 1)) {
621 amdgpu_winsys_destroy(&ws
->base
);
622 mtx_unlock(&dev_tab_mutex
);
626 /* Create the screen at the end. The winsys must be initialized
629 * Alternatively, we could create the screen based on "ws->gen"
630 * and link all drivers into one binary blob. */
631 ws
->base
.screen
= screen_create(&ws
->base
);
632 if (!ws
->base
.screen
) {
633 amdgpu_winsys_destroy(&ws
->base
);
634 mtx_unlock(&dev_tab_mutex
);
638 util_hash_table_set(dev_tab
, dev
, ws
);
640 /* We must unlock the mutex once the winsys is fully initialized, so that
641 * other threads attempting to create the winsys from the same fd will
642 * get a fully initialized winsys and not just half-way initialized. */
643 mtx_unlock(&dev_tab_mutex
);
648 pb_cache_deinit(&ws
->bo_cache
);
649 do_winsys_deinit(ws
);
653 mtx_unlock(&dev_tab_mutex
);