src/gallium/winsys/amdgpu/drm/amdgpu_winsys.c

   1 /*
   2  * Copyright © 2009 Corbin Simpson <MostAwesomeDude@gmail.com>
   3  * Copyright © 2009 Joakim Sindholt <opensource@zhasha.com>
   4  * Copyright © 2011 Marek Olšák <maraeo@gmail.com>
   5  * Copyright © 2015 Advanced Micro Devices, Inc.
   6  * All Rights Reserved.
   7  *
   8  * Permission is hereby granted, free of charge, to any person obtaining
   9  * a copy of this software and associated documentation files (the
  10  * "Software"), to deal in the Software without restriction, including
  11  * without limitation the rights to use, copy, modify, merge, publish,
  12  * distribute, sub license, and/or sell copies of the Software, and to
  13  * permit persons to whom the Software is furnished to do so, subject to
  14  * the following conditions:
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  17  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
  18  * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  19  * NON-INFRINGEMENT. IN NO EVENT SHALL THE COPYRIGHT HOLDERS, AUTHORS
  20  * AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  21  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  22  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
  23  * USE OR OTHER DEALINGS IN THE SOFTWARE.
  24  *
  25  * The above copyright notice and this permission notice (including the
  26  * next paragraph) shall be included in all copies or substantial portions
  27  * of the Software.
  28  */
  29 /*
  30  * Authors:
  31  *      Marek Olšák <maraeo@gmail.com>
  32  */
  33
  34 #include "amdgpu_cs.h"
  35 #include "amdgpu_public.h"
  36
  37 #include "util/u_hash_table.h"
  38 #include <amdgpu_drm.h>
  39 #include <xf86drm.h>
  40 #include <stdio.h>
  41 #include <sys/stat.h>
  42 #include "amd/common/amdgpu_id.h"
  43 #include "amd/common/sid.h"
  44 #include "amd/common/gfx9d.h"
  45
  46 static struct util_hash_table *dev_tab = NULL;
  47 static mtx_t dev_tab_mutex = _MTX_INITIALIZER_NP;
  48
  49 /* Helper function to do the ioctls needed for setup and init. */
  50 static bool do_winsys_init(struct amdgpu_winsys *ws, int fd)
  51 {
  52    if (!ac_query_gpu_info(fd, ws->dev, &ws->info, &ws->amdinfo))
  53       goto fail;
  54
  55    /* LLVM 5.0 is required for GFX9. */
  56    if (ws->info.chip_class >= GFX9 && HAVE_LLVM < 0x0500) {
  57       fprintf(stderr, "amdgpu: LLVM 5.0 is required, got LLVM %i.%i\n",
  58               HAVE_LLVM >> 8, HAVE_LLVM & 255);
  59       goto fail;
  60    }
  61
  62    ws->addrlib = amdgpu_addr_create(&ws->info, &ws->amdinfo);
  63    if (!ws->addrlib) {
  64       fprintf(stderr, "amdgpu: Cannot create addrlib.\n");
  65       goto fail;
  66    }
  67
  68    ws->check_vm = strstr(debug_get_option("R600_DEBUG", ""), "check_vm") != NULL;
  69
  70    return true;
  71
  72 fail:
  73    amdgpu_device_deinitialize(ws->dev);
  74    ws->dev = NULL;
  75    return false;
  76 }
  77
  78 static void do_winsys_deinit(struct amdgpu_winsys *ws)
  79 {
  80    AddrDestroy(ws->addrlib);
  81    amdgpu_device_deinitialize(ws->dev);
  82 }
  83
  84 static void amdgpu_winsys_destroy(struct radeon_winsys *rws)
  85 {
  86    struct amdgpu_winsys *ws = (struct amdgpu_winsys*)rws;
  87
  88    if (util_queue_is_initialized(&ws->cs_queue))
  89       util_queue_destroy(&ws->cs_queue);
  90
  91    mtx_destroy(&ws->bo_fence_lock);
  92    pb_slabs_deinit(&ws->bo_slabs);
  93    pb_cache_deinit(&ws->bo_cache);
  94    mtx_destroy(&ws->global_bo_list_lock);
  95    do_winsys_deinit(ws);
  96    FREE(rws);
  97 }
  98
  99 static void amdgpu_winsys_query_info(struct radeon_winsys *rws,
 100                                      struct radeon_info *info)
 101 {
 102    *info = ((struct amdgpu_winsys *)rws)->info;
 103 }
 104
 105 static bool amdgpu_cs_request_feature(struct radeon_winsys_cs *rcs,
 106                                       enum radeon_feature_id fid,
 107                                       bool enable)
 108 {
 109    return false;
 110 }
 111
 112 static uint64_t amdgpu_query_value(struct radeon_winsys *rws,
 113                                    enum radeon_value_id value)
 114 {
 115    struct amdgpu_winsys *ws = (struct amdgpu_winsys*)rws;
 116    struct amdgpu_heap_info heap;
 117    uint64_t retval = 0;
 118
 119    switch (value) {
 120    case RADEON_REQUESTED_VRAM_MEMORY:
 121       return ws->allocated_vram;
 122    case RADEON_REQUESTED_GTT_MEMORY:
 123       return ws->allocated_gtt;
 124    case RADEON_MAPPED_VRAM:
 125       return ws->mapped_vram;
 126    case RADEON_MAPPED_GTT:
 127       return ws->mapped_gtt;
 128    case RADEON_BUFFER_WAIT_TIME_NS:
 129       return ws->buffer_wait_time;
 130    case RADEON_NUM_MAPPED_BUFFERS:
 131       return ws->num_mapped_buffers;
 132    case RADEON_TIMESTAMP:
 133       amdgpu_query_info(ws->dev, AMDGPU_INFO_TIMESTAMP, 8, &retval);
 134       return retval;
 135    case RADEON_NUM_GFX_IBS:
 136       return ws->num_gfx_IBs;
 137    case RADEON_NUM_SDMA_IBS:
 138       return ws->num_sdma_IBs;
 139    case RADEON_NUM_BYTES_MOVED:
 140       amdgpu_query_info(ws->dev, AMDGPU_INFO_NUM_BYTES_MOVED, 8, &retval);
 141       return retval;
 142    case RADEON_NUM_EVICTIONS:
 143       amdgpu_query_info(ws->dev, AMDGPU_INFO_NUM_EVICTIONS, 8, &retval);
 144       return retval;
 145    case RADEON_VRAM_USAGE:
 146       amdgpu_query_heap_info(ws->dev, AMDGPU_GEM_DOMAIN_VRAM, 0, &heap);
 147       return heap.heap_usage;
 148    case RADEON_VRAM_VIS_USAGE:
 149       amdgpu_query_heap_info(ws->dev, AMDGPU_GEM_DOMAIN_VRAM,
 150                              AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED, &heap);
 151       return heap.heap_usage;
 152    case RADEON_GTT_USAGE:
 153       amdgpu_query_heap_info(ws->dev, AMDGPU_GEM_DOMAIN_GTT, 0, &heap);
 154       return heap.heap_usage;
 155    case RADEON_GPU_TEMPERATURE:
 156       amdgpu_query_sensor_info(ws->dev, AMDGPU_INFO_SENSOR_GPU_TEMP, 4, &retval);
 157       return retval;
 158    case RADEON_CURRENT_SCLK:
 159       amdgpu_query_sensor_info(ws->dev, AMDGPU_INFO_SENSOR_GFX_SCLK, 4, &retval);
 160       return retval;
 161    case RADEON_CURRENT_MCLK:
 162       amdgpu_query_sensor_info(ws->dev, AMDGPU_INFO_SENSOR_GFX_MCLK, 4, &retval);
 163       return retval;
 164    case RADEON_GPU_RESET_COUNTER:
 165       assert(0);
 166       return 0;
 167    case RADEON_CS_THREAD_TIME:
 168       return util_queue_get_thread_time_nano(&ws->cs_queue, 0);
 169    }
 170    return 0;
 171 }
 172
 173 static bool amdgpu_read_registers(struct radeon_winsys *rws,
 174                                   unsigned reg_offset,
 175                                   unsigned num_registers, uint32_t *out)
 176 {
 177    struct amdgpu_winsys *ws = (struct amdgpu_winsys*)rws;
 178
 179    return amdgpu_read_mm_registers(ws->dev, reg_offset / 4, num_registers,
 180                                    0xffffffff, 0, out) == 0;
 181 }
 182
 183 static unsigned hash_dev(void *key)
 184 {
 185 #if defined(PIPE_ARCH_X86_64)
 186    return pointer_to_intptr(key) ^ (pointer_to_intptr(key) >> 32);
 187 #else
 188    return pointer_to_intptr(key);
 189 #endif
 190 }
 191
 192 static int compare_dev(void *key1, void *key2)
 193 {
 194    return key1 != key2;
 195 }
 196
 197 static bool amdgpu_winsys_unref(struct radeon_winsys *rws)
 198 {
 199    struct amdgpu_winsys *ws = (struct amdgpu_winsys*)rws;
 200    bool destroy;
 201
 202    /* When the reference counter drops to zero, remove the device pointer
 203     * from the table.
 204     * This must happen while the mutex is locked, so that
 205     * amdgpu_winsys_create in another thread doesn't get the winsys
 206     * from the table when the counter drops to 0. */
 207    mtx_lock(&dev_tab_mutex);
 208
 209    destroy = pipe_reference(&ws->reference, NULL);
 210    if (destroy && dev_tab)
 211       util_hash_table_remove(dev_tab, ws->dev);
 212
 213    mtx_unlock(&dev_tab_mutex);
 214    return destroy;
 215 }
 216
 217 PUBLIC struct radeon_winsys *
 218 amdgpu_winsys_create(int fd, radeon_screen_create_t screen_create)
 219 {
 220    struct amdgpu_winsys *ws;
 221    drmVersionPtr version = drmGetVersion(fd);
 222    amdgpu_device_handle dev;
 223    uint32_t drm_major, drm_minor, r;
 224
 225    /* The DRM driver version of amdgpu is 3.x.x. */
 226    if (version->version_major != 3) {
 227       drmFreeVersion(version);
 228       return NULL;
 229    }
 230    drmFreeVersion(version);
 231
 232    /* Look up the winsys from the dev table. */
 233    mtx_lock(&dev_tab_mutex);
 234    if (!dev_tab)
 235       dev_tab = util_hash_table_create(hash_dev, compare_dev);
 236
 237    /* Initialize the amdgpu device. This should always return the same pointer
 238     * for the same fd. */
 239    r = amdgpu_device_initialize(fd, &drm_major, &drm_minor, &dev);
 240    if (r) {
 241       mtx_unlock(&dev_tab_mutex);
 242       fprintf(stderr, "amdgpu: amdgpu_device_initialize failed.\n");
 243       return NULL;
 244    }
 245
 246    /* Lookup a winsys if we have already created one for this device. */
 247    ws = util_hash_table_get(dev_tab, dev);
 248    if (ws) {
 249       pipe_reference(NULL, &ws->reference);
 250       mtx_unlock(&dev_tab_mutex);
 251       return &ws->base;
 252    }
 253
 254    /* Create a new winsys. */
 255    ws = CALLOC_STRUCT(amdgpu_winsys);
 256    if (!ws)
 257       goto fail;
 258
 259    ws->dev = dev;
 260    ws->info.drm_major = drm_major;
 261    ws->info.drm_minor = drm_minor;
 262
 263    if (!do_winsys_init(ws, fd))
 264       goto fail_alloc;
 265
 266    /* Create managers. */
 267    pb_cache_init(&ws->bo_cache, 500000, ws->check_vm ? 1.0f : 2.0f, 0,
 268                  (ws->info.vram_size + ws->info.gart_size) / 8,
 269                  amdgpu_bo_destroy, amdgpu_bo_can_reclaim);
 270
 271    if (!pb_slabs_init(&ws->bo_slabs,
 272                       AMDGPU_SLAB_MIN_SIZE_LOG2, AMDGPU_SLAB_MAX_SIZE_LOG2,
 273                       12, /* number of heaps (domain/flags combinations) */
 274                       ws,
 275                       amdgpu_bo_can_reclaim_slab,
 276                       amdgpu_bo_slab_alloc,
 277                       amdgpu_bo_slab_free))
 278       goto fail_cache;
 279
 280    ws->info.min_alloc_size = 1 << AMDGPU_SLAB_MIN_SIZE_LOG2;
 281
 282    /* init reference */
 283    pipe_reference_init(&ws->reference, 1);
 284
 285    /* Set functions. */
 286    ws->base.unref = amdgpu_winsys_unref;
 287    ws->base.destroy = amdgpu_winsys_destroy;
 288    ws->base.query_info = amdgpu_winsys_query_info;
 289    ws->base.cs_request_feature = amdgpu_cs_request_feature;
 290    ws->base.query_value = amdgpu_query_value;
 291    ws->base.read_registers = amdgpu_read_registers;
 292
 293    amdgpu_bo_init_functions(ws);
 294    amdgpu_cs_init_functions(ws);
 295    amdgpu_surface_init_functions(ws);
 296
 297    LIST_INITHEAD(&ws->global_bo_list);
 298    (void) mtx_init(&ws->global_bo_list_lock, mtx_plain);
 299    (void) mtx_init(&ws->bo_fence_lock, mtx_plain);
 300
 301    if (!util_queue_init(&ws->cs_queue, "amdgpu_cs", 8, 1)) {
 302       amdgpu_winsys_destroy(&ws->base);
 303       mtx_unlock(&dev_tab_mutex);
 304       return NULL;
 305    }
 306
 307    /* Create the screen at the end. The winsys must be initialized
 308     * completely.
 309     *
 310     * Alternatively, we could create the screen based on "ws->gen"
 311     * and link all drivers into one binary blob. */
 312    ws->base.screen = screen_create(&ws->base);
 313    if (!ws->base.screen) {
 314       amdgpu_winsys_destroy(&ws->base);
 315       mtx_unlock(&dev_tab_mutex);
 316       return NULL;
 317    }
 318
 319    util_hash_table_set(dev_tab, dev, ws);
 320
 321    /* We must unlock the mutex once the winsys is fully initialized, so that
 322     * other threads attempting to create the winsys from the same fd will
 323     * get a fully initialized winsys and not just half-way initialized. */
 324    mtx_unlock(&dev_tab_mutex);
 325
 326    return &ws->base;
 327
 328 fail_cache:
 329    pb_cache_deinit(&ws->bo_cache);
 330    do_winsys_deinit(ws);
 331 fail_alloc:
 332    FREE(ws);
 333 fail:
 334    mtx_unlock(&dev_tab_mutex);
 335    return NULL;
 336 }