src/gallium/winsys/amdgpu/drm/amdgpu_winsys.c

   1 /*
   2  * Copyright © 2009 Corbin Simpson <MostAwesomeDude@gmail.com>
   3  * Copyright © 2009 Joakim Sindholt <opensource@zhasha.com>
   4  * Copyright © 2011 Marek Olšák <maraeo@gmail.com>
   5  * Copyright © 2015 Advanced Micro Devices, Inc.
   6  * All Rights Reserved.
   7  *
   8  * Permission is hereby granted, free of charge, to any person obtaining
   9  * a copy of this software and associated documentation files (the
  10  * "Software"), to deal in the Software without restriction, including
  11  * without limitation the rights to use, copy, modify, merge, publish,
  12  * distribute, sub license, and/or sell copies of the Software, and to
  13  * permit persons to whom the Software is furnished to do so, subject to
  14  * the following conditions:
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  17  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
  18  * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  19  * NON-INFRINGEMENT. IN NO EVENT SHALL THE COPYRIGHT HOLDERS, AUTHORS
  20  * AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  21  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  22  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
  23  * USE OR OTHER DEALINGS IN THE SOFTWARE.
  24  *
  25  * The above copyright notice and this permission notice (including the
  26  * next paragraph) shall be included in all copies or substantial portions
  27  * of the Software.
  28  */
  29 /*
  30  * Authors:
  31  *      Marek Olšák <maraeo@gmail.com>
  32  */
  33
  34 #include "amdgpu_cs.h"
  35 #include "amdgpu_public.h"
  36
  37 #include "util/u_hash_table.h"
  38 #include <amdgpu_drm.h>
  39 #include <xf86drm.h>
  40 #include <stdio.h>
  41 #include <sys/stat.h>
  42 #include "amd/common/amdgpu_id.h"
  43 #include "amd/common/sid.h"
  44 #include "amd/common/gfx9d.h"
  45
  46 #define CIK_TILE_MODE_COLOR_2D                  14
  47
  48 #define CIK__GB_TILE_MODE__PIPE_CONFIG(x)        (((x) >> 6) & 0x1f)
  49 #define     CIK__PIPE_CONFIG__ADDR_SURF_P2               0
  50 #define     CIK__PIPE_CONFIG__ADDR_SURF_P4_8x16          4
  51 #define     CIK__PIPE_CONFIG__ADDR_SURF_P4_16x16         5
  52 #define     CIK__PIPE_CONFIG__ADDR_SURF_P4_16x32         6
  53 #define     CIK__PIPE_CONFIG__ADDR_SURF_P4_32x32         7
  54 #define     CIK__PIPE_CONFIG__ADDR_SURF_P8_16x16_8x16    8
  55 #define     CIK__PIPE_CONFIG__ADDR_SURF_P8_16x32_8x16    9
  56 #define     CIK__PIPE_CONFIG__ADDR_SURF_P8_32x32_8x16    10
  57 #define     CIK__PIPE_CONFIG__ADDR_SURF_P8_16x32_16x16   11
  58 #define     CIK__PIPE_CONFIG__ADDR_SURF_P8_32x32_16x16   12
  59 #define     CIK__PIPE_CONFIG__ADDR_SURF_P8_32x32_16x32   13
  60 #define     CIK__PIPE_CONFIG__ADDR_SURF_P8_32x64_32x32   14
  61 #define     CIK__PIPE_CONFIG__ADDR_SURF_P16_32X32_8X16   16
  62 #define     CIK__PIPE_CONFIG__ADDR_SURF_P16_32X32_16X16  17
  63
  64 #ifndef AMDGPU_INFO_NUM_EVICTIONS
  65 #define AMDGPU_INFO_NUM_EVICTIONS               0x18
  66 #endif
  67
  68 static struct util_hash_table *dev_tab = NULL;
  69 static mtx_t dev_tab_mutex = _MTX_INITIALIZER_NP;
  70
  71 static unsigned cik_get_num_tile_pipes(struct amdgpu_gpu_info *info)
  72 {
  73    unsigned mode2d = info->gb_tile_mode[CIK_TILE_MODE_COLOR_2D];
  74
  75    switch (CIK__GB_TILE_MODE__PIPE_CONFIG(mode2d)) {
  76    case CIK__PIPE_CONFIG__ADDR_SURF_P2:
  77        return 2;
  78    case CIK__PIPE_CONFIG__ADDR_SURF_P4_8x16:
  79    case CIK__PIPE_CONFIG__ADDR_SURF_P4_16x16:
  80    case CIK__PIPE_CONFIG__ADDR_SURF_P4_16x32:
  81    case CIK__PIPE_CONFIG__ADDR_SURF_P4_32x32:
  82        return 4;
  83    case CIK__PIPE_CONFIG__ADDR_SURF_P8_16x16_8x16:
  84    case CIK__PIPE_CONFIG__ADDR_SURF_P8_16x32_8x16:
  85    case CIK__PIPE_CONFIG__ADDR_SURF_P8_32x32_8x16:
  86    case CIK__PIPE_CONFIG__ADDR_SURF_P8_16x32_16x16:
  87    case CIK__PIPE_CONFIG__ADDR_SURF_P8_32x32_16x16:
  88    case CIK__PIPE_CONFIG__ADDR_SURF_P8_32x32_16x32:
  89    case CIK__PIPE_CONFIG__ADDR_SURF_P8_32x64_32x32:
  90        return 8;
  91    case CIK__PIPE_CONFIG__ADDR_SURF_P16_32X32_8X16:
  92    case CIK__PIPE_CONFIG__ADDR_SURF_P16_32X32_16X16:
  93        return 16;
  94    default:
  95        fprintf(stderr, "Invalid CIK pipe configuration, assuming P2\n");
  96        assert(!"this should never occur");
  97        return 2;
  98    }
  99 }
 100
 101 /* Helper function to do the ioctls needed for setup and init. */
 102 static bool do_winsys_init(struct amdgpu_winsys *ws, int fd)
 103 {
 104    struct amdgpu_buffer_size_alignments alignment_info = {};
 105    struct amdgpu_heap_info vram, vram_vis, gtt;
 106    struct drm_amdgpu_info_hw_ip dma = {}, uvd = {}, vce = {};
 107    uint32_t vce_version = 0, vce_feature = 0, uvd_version = 0, uvd_feature = 0;
 108    uint32_t unused_feature;
 109    int r, i, j;
 110    drmDevicePtr devinfo;
 111
 112    /* Get PCI info. */
 113    r = drmGetDevice2(fd, 0, &devinfo);
 114    if (r) {
 115       fprintf(stderr, "amdgpu: drmGetDevice2 failed.\n");
 116       goto fail;
 117    }
 118    ws->info.pci_domain = devinfo->businfo.pci->domain;
 119    ws->info.pci_bus = devinfo->businfo.pci->bus;
 120    ws->info.pci_dev = devinfo->businfo.pci->dev;
 121    ws->info.pci_func = devinfo->businfo.pci->func;
 122    drmFreeDevice(&devinfo);
 123
 124    /* Query hardware and driver information. */
 125    r = amdgpu_query_gpu_info(ws->dev, &ws->amdinfo);
 126    if (r) {
 127       fprintf(stderr, "amdgpu: amdgpu_query_gpu_info failed.\n");
 128       goto fail;
 129    }
 130
 131    r = amdgpu_query_buffer_size_alignment(ws->dev, &alignment_info);
 132    if (r) {
 133       fprintf(stderr, "amdgpu: amdgpu_query_buffer_size_alignment failed.\n");
 134       goto fail;
 135    }
 136
 137    r = amdgpu_query_heap_info(ws->dev, AMDGPU_GEM_DOMAIN_VRAM, 0, &vram);
 138    if (r) {
 139       fprintf(stderr, "amdgpu: amdgpu_query_heap_info(vram) failed.\n");
 140       goto fail;
 141    }
 142
 143    r = amdgpu_query_heap_info(ws->dev, AMDGPU_GEM_DOMAIN_VRAM,
 144                               AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED,
 145                               &vram_vis);
 146    if (r) {
 147       fprintf(stderr, "amdgpu: amdgpu_query_heap_info(vram_vis) failed.\n");
 148       goto fail;
 149    }
 150
 151    r = amdgpu_query_heap_info(ws->dev, AMDGPU_GEM_DOMAIN_GTT, 0, &gtt);
 152    if (r) {
 153       fprintf(stderr, "amdgpu: amdgpu_query_heap_info(gtt) failed.\n");
 154       goto fail;
 155    }
 156
 157    r = amdgpu_query_hw_ip_info(ws->dev, AMDGPU_HW_IP_DMA, 0, &dma);
 158    if (r) {
 159       fprintf(stderr, "amdgpu: amdgpu_query_hw_ip_info(dma) failed.\n");
 160       goto fail;
 161    }
 162
 163    r = amdgpu_query_hw_ip_info(ws->dev, AMDGPU_HW_IP_UVD, 0, &uvd);
 164    if (r) {
 165       fprintf(stderr, "amdgpu: amdgpu_query_hw_ip_info(uvd) failed.\n");
 166       goto fail;
 167    }
 168
 169    r = amdgpu_query_firmware_version(ws->dev, AMDGPU_INFO_FW_GFX_ME, 0, 0,
 170                                      &ws->info.me_fw_version, &unused_feature);
 171    if (r) {
 172       fprintf(stderr, "amdgpu: amdgpu_query_firmware_version(me) failed.\n");
 173       goto fail;
 174    }
 175
 176    r = amdgpu_query_firmware_version(ws->dev, AMDGPU_INFO_FW_GFX_PFP, 0, 0,
 177                                      &ws->info.pfp_fw_version, &unused_feature);
 178    if (r) {
 179       fprintf(stderr, "amdgpu: amdgpu_query_firmware_version(pfp) failed.\n");
 180       goto fail;
 181    }
 182
 183    r = amdgpu_query_firmware_version(ws->dev, AMDGPU_INFO_FW_GFX_CE, 0, 0,
 184                                      &ws->info.ce_fw_version, &unused_feature);
 185    if (r) {
 186       fprintf(stderr, "amdgpu: amdgpu_query_firmware_version(ce) failed.\n");
 187       goto fail;
 188    }
 189
 190    r = amdgpu_query_firmware_version(ws->dev, AMDGPU_INFO_FW_UVD, 0, 0,
 191                                      &uvd_version, &uvd_feature);
 192    if (r) {
 193       fprintf(stderr, "amdgpu: amdgpu_query_firmware_version(uvd) failed.\n");
 194       goto fail;
 195    }
 196
 197    r = amdgpu_query_hw_ip_info(ws->dev, AMDGPU_HW_IP_VCE, 0, &vce);
 198    if (r) {
 199       fprintf(stderr, "amdgpu: amdgpu_query_hw_ip_info(vce) failed.\n");
 200       goto fail;
 201    }
 202
 203    r = amdgpu_query_firmware_version(ws->dev, AMDGPU_INFO_FW_VCE, 0, 0,
 204                                      &vce_version, &vce_feature);
 205    if (r) {
 206       fprintf(stderr, "amdgpu: amdgpu_query_firmware_version(vce) failed.\n");
 207       goto fail;
 208    }
 209
 210    /* Set chip identification. */
 211    ws->info.pci_id = ws->amdinfo.asic_id; /* TODO: is this correct? */
 212    ws->info.vce_harvest_config = ws->amdinfo.vce_harvest_config;
 213
 214    switch (ws->info.pci_id) {
 215 #define CHIPSET(pci_id, name, cfamily) case pci_id: ws->info.family = CHIP_##cfamily; break;
 216 #include "pci_ids/radeonsi_pci_ids.h"
 217 #undef CHIPSET
 218
 219    default:
 220       fprintf(stderr, "amdgpu: Invalid PCI ID.\n");
 221       goto fail;
 222    }
 223
 224    if (ws->info.family >= CHIP_VEGA10)
 225       ws->info.chip_class = GFX9;
 226    else if (ws->info.family >= CHIP_TONGA)
 227       ws->info.chip_class = VI;
 228    else if (ws->info.family >= CHIP_BONAIRE)
 229       ws->info.chip_class = CIK;
 230    else if (ws->info.family >= CHIP_TAHITI)
 231       ws->info.chip_class = SI;
 232    else {
 233       fprintf(stderr, "amdgpu: Unknown family.\n");
 234       goto fail;
 235    }
 236
 237    /* LLVM 5.0 is required for GFX9. */
 238    if (ws->info.chip_class >= GFX9 && HAVE_LLVM < 0x0500) {
 239       fprintf(stderr, "amdgpu: LLVM 5.0 is required, got LLVM %i.%i\n",
 240               HAVE_LLVM >> 8, HAVE_LLVM & 255);
 241       goto fail;
 242    }
 243
 244    /* family and rev_id are for addrlib */
 245    switch (ws->info.family) {
 246    case CHIP_TAHITI:
 247       ws->family = FAMILY_SI;
 248       ws->rev_id = SI_TAHITI_P_A0;
 249       break;
 250    case CHIP_PITCAIRN:
 251       ws->family = FAMILY_SI;
 252       ws->rev_id = SI_PITCAIRN_PM_A0;
 253       break;
 254    case CHIP_VERDE:
 255       ws->family = FAMILY_SI;
 256       ws->rev_id = SI_CAPEVERDE_M_A0;
 257       break;
 258    case CHIP_OLAND:
 259       ws->family = FAMILY_SI;
 260       ws->rev_id = SI_OLAND_M_A0;
 261       break;
 262    case CHIP_HAINAN:
 263       ws->family = FAMILY_SI;
 264       ws->rev_id = SI_HAINAN_V_A0;
 265       break;
 266    case CHIP_BONAIRE:
 267       ws->family = FAMILY_CI;
 268       ws->rev_id = CI_BONAIRE_M_A0;
 269       break;
 270    case CHIP_KAVERI:
 271       ws->family = FAMILY_KV;
 272       ws->rev_id = KV_SPECTRE_A0;
 273       break;
 274    case CHIP_KABINI:
 275       ws->family = FAMILY_KV;
 276       ws->rev_id = KB_KALINDI_A0;
 277       break;
 278    case CHIP_HAWAII:
 279       ws->family = FAMILY_CI;
 280       ws->rev_id = CI_HAWAII_P_A0;
 281       break;
 282    case CHIP_MULLINS:
 283       ws->family = FAMILY_KV;
 284       ws->rev_id = ML_GODAVARI_A0;
 285       break;
 286    case CHIP_TONGA:
 287       ws->family = FAMILY_VI;
 288       ws->rev_id = VI_TONGA_P_A0;
 289       break;
 290    case CHIP_ICELAND:
 291       ws->family = FAMILY_VI;
 292       ws->rev_id = VI_ICELAND_M_A0;
 293       break;
 294    case CHIP_CARRIZO:
 295       ws->family = FAMILY_CZ;
 296       ws->rev_id = CARRIZO_A0;
 297       break;
 298    case CHIP_STONEY:
 299       ws->family = FAMILY_CZ;
 300       ws->rev_id = STONEY_A0;
 301       break;
 302    case CHIP_FIJI:
 303       ws->family = FAMILY_VI;
 304       ws->rev_id = VI_FIJI_P_A0;
 305       break;
 306    case CHIP_POLARIS10:
 307       ws->family = FAMILY_VI;
 308       ws->rev_id = VI_POLARIS10_P_A0;
 309       break;
 310    case CHIP_POLARIS11:
 311       ws->family = FAMILY_VI;
 312       ws->rev_id = VI_POLARIS11_M_A0;
 313       break;
 314    case CHIP_POLARIS12:
 315       ws->family = FAMILY_VI;
 316       ws->rev_id = VI_POLARIS12_V_A0;
 317    case CHIP_VEGA10:
 318       ws->family = FAMILY_AI;
 319       ws->rev_id = AI_VEGA10_P_A0;
 320       break;
 321    default:
 322       fprintf(stderr, "amdgpu: Unknown family.\n");
 323       goto fail;
 324    }
 325
 326    ws->addrlib = amdgpu_addr_create(ws);
 327    if (!ws->addrlib) {
 328       fprintf(stderr, "amdgpu: Cannot create addrlib.\n");
 329       goto fail;
 330    }
 331
 332    /* Set which chips have dedicated VRAM. */
 333    ws->info.has_dedicated_vram =
 334       !(ws->amdinfo.ids_flags & AMDGPU_IDS_FLAGS_FUSION);
 335
 336    /* Set hardware information. */
 337    ws->info.gart_size = gtt.heap_size;
 338    ws->info.vram_size = vram.heap_size;
 339    ws->info.vram_vis_size = vram_vis.heap_size;
 340    /* The kernel can split large buffers in VRAM but not in GTT, so large
 341     * allocations can fail or cause buffer movement failures in the kernel.
 342     */
 343    ws->info.max_alloc_size = MIN2(ws->info.vram_size * 0.9, ws->info.gart_size * 0.7);
 344    /* convert the shader clock from KHz to MHz */
 345    ws->info.max_shader_clock = ws->amdinfo.max_engine_clk / 1000;
 346    ws->info.max_se = ws->amdinfo.num_shader_engines;
 347    ws->info.max_sh_per_se = ws->amdinfo.num_shader_arrays_per_engine;
 348    ws->info.has_uvd = uvd.available_rings != 0;
 349    ws->info.uvd_fw_version =
 350          uvd.available_rings ? uvd_version : 0;
 351    ws->info.vce_fw_version =
 352          vce.available_rings ? vce_version : 0;
 353    ws->info.has_userptr = true;
 354    ws->info.num_render_backends = ws->amdinfo.rb_pipes;
 355    ws->info.clock_crystal_freq = ws->amdinfo.gpu_counter_freq;
 356    ws->info.tcc_cache_line_size = 64; /* TC L2 line size on GCN */
 357    if (ws->info.chip_class == GFX9) {
 358       ws->info.num_tile_pipes = 1 << G_0098F8_NUM_PIPES(ws->amdinfo.gb_addr_cfg);
 359       ws->info.pipe_interleave_bytes =
 360          256 << G_0098F8_PIPE_INTERLEAVE_SIZE_GFX9(ws->amdinfo.gb_addr_cfg);
 361    } else {
 362       ws->info.num_tile_pipes = cik_get_num_tile_pipes(&ws->amdinfo);
 363       ws->info.pipe_interleave_bytes =
 364          256 << G_0098F8_PIPE_INTERLEAVE_SIZE_GFX6(ws->amdinfo.gb_addr_cfg);
 365    }
 366    ws->info.has_virtual_memory = true;
 367    ws->info.has_sdma = dma.available_rings != 0;
 368
 369    /* Get the number of good compute units. */
 370    ws->info.num_good_compute_units = 0;
 371    for (i = 0; i < ws->info.max_se; i++)
 372       for (j = 0; j < ws->info.max_sh_per_se; j++)
 373          ws->info.num_good_compute_units +=
 374             util_bitcount(ws->amdinfo.cu_bitmap[i][j]);
 375
 376    memcpy(ws->info.si_tile_mode_array, ws->amdinfo.gb_tile_mode,
 377           sizeof(ws->amdinfo.gb_tile_mode));
 378    ws->info.enabled_rb_mask = ws->amdinfo.enabled_rb_pipes_mask;
 379
 380    memcpy(ws->info.cik_macrotile_mode_array, ws->amdinfo.gb_macro_tile_mode,
 381           sizeof(ws->amdinfo.gb_macro_tile_mode));
 382
 383    ws->info.gart_page_size = alignment_info.size_remote;
 384
 385    if (ws->info.chip_class == SI)
 386       ws->info.gfx_ib_pad_with_type2 = TRUE;
 387
 388    ws->check_vm = strstr(debug_get_option("R600_DEBUG", ""), "check_vm") != NULL;
 389
 390    return true;
 391
 392 fail:
 393    if (ws->addrlib)
 394       AddrDestroy(ws->addrlib);
 395    amdgpu_device_deinitialize(ws->dev);
 396    ws->dev = NULL;
 397    return false;
 398 }
 399
 400 static void do_winsys_deinit(struct amdgpu_winsys *ws)
 401 {
 402    AddrDestroy(ws->addrlib);
 403    amdgpu_device_deinitialize(ws->dev);
 404 }
 405
 406 static void amdgpu_winsys_destroy(struct radeon_winsys *rws)
 407 {
 408    struct amdgpu_winsys *ws = (struct amdgpu_winsys*)rws;
 409
 410    if (util_queue_is_initialized(&ws->cs_queue))
 411       util_queue_destroy(&ws->cs_queue);
 412
 413    mtx_destroy(&ws->bo_fence_lock);
 414    pb_slabs_deinit(&ws->bo_slabs);
 415    pb_cache_deinit(&ws->bo_cache);
 416    mtx_destroy(&ws->global_bo_list_lock);
 417    do_winsys_deinit(ws);
 418    FREE(rws);
 419 }
 420
 421 static void amdgpu_winsys_query_info(struct radeon_winsys *rws,
 422                                      struct radeon_info *info)
 423 {
 424    *info = ((struct amdgpu_winsys *)rws)->info;
 425 }
 426
 427 static bool amdgpu_cs_request_feature(struct radeon_winsys_cs *rcs,
 428                                       enum radeon_feature_id fid,
 429                                       bool enable)
 430 {
 431    return false;
 432 }
 433
 434 static uint64_t amdgpu_query_value(struct radeon_winsys *rws,
 435                                    enum radeon_value_id value)
 436 {
 437    struct amdgpu_winsys *ws = (struct amdgpu_winsys*)rws;
 438    struct amdgpu_heap_info heap;
 439    uint64_t retval = 0;
 440
 441    switch (value) {
 442    case RADEON_REQUESTED_VRAM_MEMORY:
 443       return ws->allocated_vram;
 444    case RADEON_REQUESTED_GTT_MEMORY:
 445       return ws->allocated_gtt;
 446    case RADEON_MAPPED_VRAM:
 447       return ws->mapped_vram;
 448    case RADEON_MAPPED_GTT:
 449       return ws->mapped_gtt;
 450    case RADEON_BUFFER_WAIT_TIME_NS:
 451       return ws->buffer_wait_time;
 452    case RADEON_NUM_MAPPED_BUFFERS:
 453       return ws->num_mapped_buffers;
 454    case RADEON_TIMESTAMP:
 455       amdgpu_query_info(ws->dev, AMDGPU_INFO_TIMESTAMP, 8, &retval);
 456       return retval;
 457    case RADEON_NUM_GFX_IBS:
 458       return ws->num_gfx_IBs;
 459    case RADEON_NUM_SDMA_IBS:
 460       return ws->num_sdma_IBs;
 461    case RADEON_NUM_BYTES_MOVED:
 462       amdgpu_query_info(ws->dev, AMDGPU_INFO_NUM_BYTES_MOVED, 8, &retval);
 463       return retval;
 464    case RADEON_NUM_EVICTIONS:
 465       amdgpu_query_info(ws->dev, AMDGPU_INFO_NUM_EVICTIONS, 8, &retval);
 466       return retval;
 467    case RADEON_VRAM_USAGE:
 468       amdgpu_query_heap_info(ws->dev, AMDGPU_GEM_DOMAIN_VRAM, 0, &heap);
 469       return heap.heap_usage;
 470    case RADEON_VRAM_VIS_USAGE:
 471       amdgpu_query_heap_info(ws->dev, AMDGPU_GEM_DOMAIN_VRAM,
 472                              AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED, &heap);
 473       return heap.heap_usage;
 474    case RADEON_GTT_USAGE:
 475       amdgpu_query_heap_info(ws->dev, AMDGPU_GEM_DOMAIN_GTT, 0, &heap);
 476       return heap.heap_usage;
 477    case RADEON_GPU_TEMPERATURE:
 478    case RADEON_CURRENT_SCLK:
 479    case RADEON_CURRENT_MCLK:
 480       return 0;
 481    case RADEON_GPU_RESET_COUNTER:
 482       assert(0);
 483       return 0;
 484    case RADEON_CS_THREAD_TIME:
 485       return util_queue_get_thread_time_nano(&ws->cs_queue, 0);
 486    }
 487    return 0;
 488 }
 489
 490 static bool amdgpu_read_registers(struct radeon_winsys *rws,
 491                                   unsigned reg_offset,
 492                                   unsigned num_registers, uint32_t *out)
 493 {
 494    struct amdgpu_winsys *ws = (struct amdgpu_winsys*)rws;
 495
 496    return amdgpu_read_mm_registers(ws->dev, reg_offset / 4, num_registers,
 497                                    0xffffffff, 0, out) == 0;
 498 }
 499
 500 static unsigned hash_dev(void *key)
 501 {
 502 #if defined(PIPE_ARCH_X86_64)
 503    return pointer_to_intptr(key) ^ (pointer_to_intptr(key) >> 32);
 504 #else
 505    return pointer_to_intptr(key);
 506 #endif
 507 }
 508
 509 static int compare_dev(void *key1, void *key2)
 510 {
 511    return key1 != key2;
 512 }
 513
 514 static bool amdgpu_winsys_unref(struct radeon_winsys *rws)
 515 {
 516    struct amdgpu_winsys *ws = (struct amdgpu_winsys*)rws;
 517    bool destroy;
 518
 519    /* When the reference counter drops to zero, remove the device pointer
 520     * from the table.
 521     * This must happen while the mutex is locked, so that
 522     * amdgpu_winsys_create in another thread doesn't get the winsys
 523     * from the table when the counter drops to 0. */
 524    mtx_lock(&dev_tab_mutex);
 525
 526    destroy = pipe_reference(&ws->reference, NULL);
 527    if (destroy && dev_tab)
 528       util_hash_table_remove(dev_tab, ws->dev);
 529
 530    mtx_unlock(&dev_tab_mutex);
 531    return destroy;
 532 }
 533
 534 PUBLIC struct radeon_winsys *
 535 amdgpu_winsys_create(int fd, radeon_screen_create_t screen_create)
 536 {
 537    struct amdgpu_winsys *ws;
 538    drmVersionPtr version = drmGetVersion(fd);
 539    amdgpu_device_handle dev;
 540    uint32_t drm_major, drm_minor, r;
 541
 542    /* The DRM driver version of amdgpu is 3.x.x. */
 543    if (version->version_major != 3) {
 544       drmFreeVersion(version);
 545       return NULL;
 546    }
 547    drmFreeVersion(version);
 548
 549    /* Look up the winsys from the dev table. */
 550    mtx_lock(&dev_tab_mutex);
 551    if (!dev_tab)
 552       dev_tab = util_hash_table_create(hash_dev, compare_dev);
 553
 554    /* Initialize the amdgpu device. This should always return the same pointer
 555     * for the same fd. */
 556    r = amdgpu_device_initialize(fd, &drm_major, &drm_minor, &dev);
 557    if (r) {
 558       mtx_unlock(&dev_tab_mutex);
 559       fprintf(stderr, "amdgpu: amdgpu_device_initialize failed.\n");
 560       return NULL;
 561    }
 562
 563    /* Lookup a winsys if we have already created one for this device. */
 564    ws = util_hash_table_get(dev_tab, dev);
 565    if (ws) {
 566       pipe_reference(NULL, &ws->reference);
 567       mtx_unlock(&dev_tab_mutex);
 568       return &ws->base;
 569    }
 570
 571    /* Create a new winsys. */
 572    ws = CALLOC_STRUCT(amdgpu_winsys);
 573    if (!ws)
 574       goto fail;
 575
 576    ws->dev = dev;
 577    ws->info.drm_major = drm_major;
 578    ws->info.drm_minor = drm_minor;
 579
 580    if (!do_winsys_init(ws, fd))
 581       goto fail_alloc;
 582
 583    /* Create managers. */
 584    pb_cache_init(&ws->bo_cache, 500000, ws->check_vm ? 1.0f : 2.0f, 0,
 585                  (ws->info.vram_size + ws->info.gart_size) / 8,
 586                  amdgpu_bo_destroy, amdgpu_bo_can_reclaim);
 587
 588    if (!pb_slabs_init(&ws->bo_slabs,
 589                       AMDGPU_SLAB_MIN_SIZE_LOG2, AMDGPU_SLAB_MAX_SIZE_LOG2,
 590                       12, /* number of heaps (domain/flags combinations) */
 591                       ws,
 592                       amdgpu_bo_can_reclaim_slab,
 593                       amdgpu_bo_slab_alloc,
 594                       amdgpu_bo_slab_free))
 595       goto fail_cache;
 596
 597    ws->info.min_alloc_size = 1 << AMDGPU_SLAB_MIN_SIZE_LOG2;
 598
 599    /* init reference */
 600    pipe_reference_init(&ws->reference, 1);
 601
 602    /* Set functions. */
 603    ws->base.unref = amdgpu_winsys_unref;
 604    ws->base.destroy = amdgpu_winsys_destroy;
 605    ws->base.query_info = amdgpu_winsys_query_info;
 606    ws->base.cs_request_feature = amdgpu_cs_request_feature;
 607    ws->base.query_value = amdgpu_query_value;
 608    ws->base.read_registers = amdgpu_read_registers;
 609
 610    amdgpu_bo_init_functions(ws);
 611    amdgpu_cs_init_functions(ws);
 612    amdgpu_surface_init_functions(ws);
 613
 614    LIST_INITHEAD(&ws->global_bo_list);
 615    (void) mtx_init(&ws->global_bo_list_lock, mtx_plain);
 616    (void) mtx_init(&ws->bo_fence_lock, mtx_plain);
 617
 618    if (!util_queue_init(&ws->cs_queue, "amdgpu_cs", 8, 1)) {
 619       amdgpu_winsys_destroy(&ws->base);
 620       mtx_unlock(&dev_tab_mutex);
 621       return NULL;
 622    }
 623
 624    /* Create the screen at the end. The winsys must be initialized
 625     * completely.
 626     *
 627     * Alternatively, we could create the screen based on "ws->gen"
 628     * and link all drivers into one binary blob. */
 629    ws->base.screen = screen_create(&ws->base);
 630    if (!ws->base.screen) {
 631       amdgpu_winsys_destroy(&ws->base);
 632       mtx_unlock(&dev_tab_mutex);
 633       return NULL;
 634    }
 635
 636    util_hash_table_set(dev_tab, dev, ws);
 637
 638    /* We must unlock the mutex once the winsys is fully initialized, so that
 639     * other threads attempting to create the winsys from the same fd will
 640     * get a fully initialized winsys and not just half-way initialized. */
 641    mtx_unlock(&dev_tab_mutex);
 642
 643    return &ws->base;
 644
 645 fail_cache:
 646    pb_cache_deinit(&ws->bo_cache);
 647    do_winsys_deinit(ws);
 648 fail_alloc:
 649    FREE(ws);
 650 fail:
 651    mtx_unlock(&dev_tab_mutex);
 652    return NULL;
 653 }