src/gallium/winsys/amdgpu/drm/amdgpu_winsys.c

   1 /*
   2  * Copyright © 2009 Corbin Simpson <MostAwesomeDude@gmail.com>
   3  * Copyright © 2009 Joakim Sindholt <opensource@zhasha.com>
   4  * Copyright © 2011 Marek Olšák <maraeo@gmail.com>
   5  * Copyright © 2015 Advanced Micro Devices, Inc.
   6  * All Rights Reserved.
   7  *
   8  * Permission is hereby granted, free of charge, to any person obtaining
   9  * a copy of this software and associated documentation files (the
  10  * "Software"), to deal in the Software without restriction, including
  11  * without limitation the rights to use, copy, modify, merge, publish,
  12  * distribute, sub license, and/or sell copies of the Software, and to
  13  * permit persons to whom the Software is furnished to do so, subject to
  14  * the following conditions:
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  17  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
  18  * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  19  * NON-INFRINGEMENT. IN NO EVENT SHALL THE COPYRIGHT HOLDERS, AUTHORS
  20  * AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  21  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  22  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
  23  * USE OR OTHER DEALINGS IN THE SOFTWARE.
  24  *
  25  * The above copyright notice and this permission notice (including the
  26  * next paragraph) shall be included in all copies or substantial portions
  27  * of the Software.
  28  */
  29 /*
  30  * Authors:
  31  *      Marek Olšák <maraeo@gmail.com>
  32  */
  33
  34 #include "amdgpu_cs.h"
  35 #include "amdgpu_public.h"
  36
  37 #include "util/u_hash_table.h"
  38 #include <amdgpu_drm.h>
  39 #include <xf86drm.h>
  40 #include <stdio.h>
  41 #include <sys/stat.h>
  42 #include "amd/common/amdgpu_id.h"
  43 #include "amd/common/sid.h"
  44 #include "amd/common/gfx9d.h"
  45
  46 #ifndef AMDGPU_INFO_NUM_VRAM_CPU_PAGE_FAULTS
  47 #define AMDGPU_INFO_NUM_VRAM_CPU_PAGE_FAULTS    0x1E
  48 #endif
  49
  50 static struct util_hash_table *dev_tab = NULL;
  51 static mtx_t dev_tab_mutex = _MTX_INITIALIZER_NP;
  52
  53 /* Helper function to do the ioctls needed for setup and init. */
  54 static bool do_winsys_init(struct amdgpu_winsys *ws, int fd)
  55 {
  56    if (!ac_query_gpu_info(fd, ws->dev, &ws->info, &ws->amdinfo))
  57       goto fail;
  58
  59    /* LLVM 5.0 is required for GFX9. */
  60    if (ws->info.chip_class >= GFX9 && HAVE_LLVM < 0x0500) {
  61       fprintf(stderr, "amdgpu: LLVM 5.0 is required, got LLVM %i.%i\n",
  62               HAVE_LLVM >> 8, HAVE_LLVM & 255);
  63       goto fail;
  64    }
  65
  66    ws->addrlib = amdgpu_addr_create(&ws->info, &ws->amdinfo, NULL);
  67    if (!ws->addrlib) {
  68       fprintf(stderr, "amdgpu: Cannot create addrlib.\n");
  69       goto fail;
  70    }
  71
  72    ws->check_vm = strstr(debug_get_option("R600_DEBUG", ""), "check_vm") != NULL;
  73
  74    return true;
  75
  76 fail:
  77    amdgpu_device_deinitialize(ws->dev);
  78    ws->dev = NULL;
  79    return false;
  80 }
  81
  82 static void do_winsys_deinit(struct amdgpu_winsys *ws)
  83 {
  84    AddrDestroy(ws->addrlib);
  85    amdgpu_device_deinitialize(ws->dev);
  86 }
  87
  88 static void amdgpu_winsys_destroy(struct radeon_winsys *rws)
  89 {
  90    struct amdgpu_winsys *ws = (struct amdgpu_winsys*)rws;
  91
  92    if (util_queue_is_initialized(&ws->cs_queue))
  93       util_queue_destroy(&ws->cs_queue);
  94
  95    mtx_destroy(&ws->bo_fence_lock);
  96    pb_slabs_deinit(&ws->bo_slabs);
  97    pb_cache_deinit(&ws->bo_cache);
  98    mtx_destroy(&ws->global_bo_list_lock);
  99    do_winsys_deinit(ws);
 100    FREE(rws);
 101 }
 102
 103 static void amdgpu_winsys_query_info(struct radeon_winsys *rws,
 104                                      struct radeon_info *info)
 105 {
 106    *info = ((struct amdgpu_winsys *)rws)->info;
 107 }
 108
 109 static bool amdgpu_cs_request_feature(struct radeon_winsys_cs *rcs,
 110                                       enum radeon_feature_id fid,
 111                                       bool enable)
 112 {
 113    return false;
 114 }
 115
 116 static uint64_t amdgpu_query_value(struct radeon_winsys *rws,
 117                                    enum radeon_value_id value)
 118 {
 119    struct amdgpu_winsys *ws = (struct amdgpu_winsys*)rws;
 120    struct amdgpu_heap_info heap;
 121    uint64_t retval = 0;
 122
 123    switch (value) {
 124    case RADEON_REQUESTED_VRAM_MEMORY:
 125       return ws->allocated_vram;
 126    case RADEON_REQUESTED_GTT_MEMORY:
 127       return ws->allocated_gtt;
 128    case RADEON_MAPPED_VRAM:
 129       return ws->mapped_vram;
 130    case RADEON_MAPPED_GTT:
 131       return ws->mapped_gtt;
 132    case RADEON_BUFFER_WAIT_TIME_NS:
 133       return ws->buffer_wait_time;
 134    case RADEON_NUM_MAPPED_BUFFERS:
 135       return ws->num_mapped_buffers;
 136    case RADEON_TIMESTAMP:
 137       amdgpu_query_info(ws->dev, AMDGPU_INFO_TIMESTAMP, 8, &retval);
 138       return retval;
 139    case RADEON_NUM_GFX_IBS:
 140       return ws->num_gfx_IBs;
 141    case RADEON_NUM_SDMA_IBS:
 142       return ws->num_sdma_IBs;
 143    case RADEON_GFX_BO_LIST_COUNTER:
 144       return ws->gfx_bo_list_counter;
 145    case RADEON_NUM_BYTES_MOVED:
 146       amdgpu_query_info(ws->dev, AMDGPU_INFO_NUM_BYTES_MOVED, 8, &retval);
 147       return retval;
 148    case RADEON_NUM_EVICTIONS:
 149       amdgpu_query_info(ws->dev, AMDGPU_INFO_NUM_EVICTIONS, 8, &retval);
 150       return retval;
 151    case RADEON_NUM_VRAM_CPU_PAGE_FAULTS:
 152       amdgpu_query_info(ws->dev, AMDGPU_INFO_NUM_VRAM_CPU_PAGE_FAULTS, 8, &retval);
 153       return retval;
 154    case RADEON_VRAM_USAGE:
 155       amdgpu_query_heap_info(ws->dev, AMDGPU_GEM_DOMAIN_VRAM, 0, &heap);
 156       return heap.heap_usage;
 157    case RADEON_VRAM_VIS_USAGE:
 158       amdgpu_query_heap_info(ws->dev, AMDGPU_GEM_DOMAIN_VRAM,
 159                              AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED, &heap);
 160       return heap.heap_usage;
 161    case RADEON_GTT_USAGE:
 162       amdgpu_query_heap_info(ws->dev, AMDGPU_GEM_DOMAIN_GTT, 0, &heap);
 163       return heap.heap_usage;
 164    case RADEON_GPU_TEMPERATURE:
 165       amdgpu_query_sensor_info(ws->dev, AMDGPU_INFO_SENSOR_GPU_TEMP, 4, &retval);
 166       return retval;
 167    case RADEON_CURRENT_SCLK:
 168       amdgpu_query_sensor_info(ws->dev, AMDGPU_INFO_SENSOR_GFX_SCLK, 4, &retval);
 169       return retval;
 170    case RADEON_CURRENT_MCLK:
 171       amdgpu_query_sensor_info(ws->dev, AMDGPU_INFO_SENSOR_GFX_MCLK, 4, &retval);
 172       return retval;
 173    case RADEON_GPU_RESET_COUNTER:
 174       assert(0);
 175       return 0;
 176    case RADEON_CS_THREAD_TIME:
 177       return util_queue_get_thread_time_nano(&ws->cs_queue, 0);
 178    }
 179    return 0;
 180 }
 181
 182 static bool amdgpu_read_registers(struct radeon_winsys *rws,
 183                                   unsigned reg_offset,
 184                                   unsigned num_registers, uint32_t *out)
 185 {
 186    struct amdgpu_winsys *ws = (struct amdgpu_winsys*)rws;
 187
 188    return amdgpu_read_mm_registers(ws->dev, reg_offset / 4, num_registers,
 189                                    0xffffffff, 0, out) == 0;
 190 }
 191
 192 static unsigned hash_dev(void *key)
 193 {
 194 #if defined(PIPE_ARCH_X86_64)
 195    return pointer_to_intptr(key) ^ (pointer_to_intptr(key) >> 32);
 196 #else
 197    return pointer_to_intptr(key);
 198 #endif
 199 }
 200
 201 static int compare_dev(void *key1, void *key2)
 202 {
 203    return key1 != key2;
 204 }
 205
 206 static bool amdgpu_winsys_unref(struct radeon_winsys *rws)
 207 {
 208    struct amdgpu_winsys *ws = (struct amdgpu_winsys*)rws;
 209    bool destroy;
 210
 211    /* When the reference counter drops to zero, remove the device pointer
 212     * from the table.
 213     * This must happen while the mutex is locked, so that
 214     * amdgpu_winsys_create in another thread doesn't get the winsys
 215     * from the table when the counter drops to 0. */
 216    mtx_lock(&dev_tab_mutex);
 217
 218    destroy = pipe_reference(&ws->reference, NULL);
 219    if (destroy && dev_tab)
 220       util_hash_table_remove(dev_tab, ws->dev);
 221
 222    mtx_unlock(&dev_tab_mutex);
 223    return destroy;
 224 }
 225
 226 static const char* amdgpu_get_chip_name(struct radeon_winsys *ws)
 227 {
 228    amdgpu_device_handle dev = ((struct amdgpu_winsys *)ws)->dev;
 229    return amdgpu_get_marketing_name(dev);
 230 }
 231
 232
 233 PUBLIC struct radeon_winsys *
 234 amdgpu_winsys_create(int fd, const struct pipe_screen_config *config,
 235                      radeon_screen_create_t screen_create)
 236 {
 237    struct amdgpu_winsys *ws;
 238    drmVersionPtr version = drmGetVersion(fd);
 239    amdgpu_device_handle dev;
 240    uint32_t drm_major, drm_minor, r;
 241
 242    /* The DRM driver version of amdgpu is 3.x.x. */
 243    if (version->version_major != 3) {
 244       drmFreeVersion(version);
 245       return NULL;
 246    }
 247    drmFreeVersion(version);
 248
 249    /* Look up the winsys from the dev table. */
 250    mtx_lock(&dev_tab_mutex);
 251    if (!dev_tab)
 252       dev_tab = util_hash_table_create(hash_dev, compare_dev);
 253
 254    /* Initialize the amdgpu device. This should always return the same pointer
 255     * for the same fd. */
 256    r = amdgpu_device_initialize(fd, &drm_major, &drm_minor, &dev);
 257    if (r) {
 258       mtx_unlock(&dev_tab_mutex);
 259       fprintf(stderr, "amdgpu: amdgpu_device_initialize failed.\n");
 260       return NULL;
 261    }
 262
 263    /* Lookup a winsys if we have already created one for this device. */
 264    ws = util_hash_table_get(dev_tab, dev);
 265    if (ws) {
 266       pipe_reference(NULL, &ws->reference);
 267       mtx_unlock(&dev_tab_mutex);
 268       return &ws->base;
 269    }
 270
 271    /* Create a new winsys. */
 272    ws = CALLOC_STRUCT(amdgpu_winsys);
 273    if (!ws)
 274       goto fail;
 275
 276    ws->dev = dev;
 277    ws->info.drm_major = drm_major;
 278    ws->info.drm_minor = drm_minor;
 279
 280    if (!do_winsys_init(ws, fd))
 281       goto fail_alloc;
 282
 283    /* Create managers. */
 284    pb_cache_init(&ws->bo_cache, 500000, ws->check_vm ? 1.0f : 2.0f, 0,
 285                  (ws->info.vram_size + ws->info.gart_size) / 8,
 286                  amdgpu_bo_destroy, amdgpu_bo_can_reclaim);
 287
 288    if (!pb_slabs_init(&ws->bo_slabs,
 289                       AMDGPU_SLAB_MIN_SIZE_LOG2, AMDGPU_SLAB_MAX_SIZE_LOG2,
 290                       RADEON_MAX_SLAB_HEAPS,
 291                       ws,
 292                       amdgpu_bo_can_reclaim_slab,
 293                       amdgpu_bo_slab_alloc,
 294                       amdgpu_bo_slab_free))
 295       goto fail_cache;
 296
 297    ws->info.min_alloc_size = 1 << AMDGPU_SLAB_MIN_SIZE_LOG2;
 298
 299    /* init reference */
 300    pipe_reference_init(&ws->reference, 1);
 301
 302    /* Set functions. */
 303    ws->base.unref = amdgpu_winsys_unref;
 304    ws->base.destroy = amdgpu_winsys_destroy;
 305    ws->base.query_info = amdgpu_winsys_query_info;
 306    ws->base.cs_request_feature = amdgpu_cs_request_feature;
 307    ws->base.query_value = amdgpu_query_value;
 308    ws->base.read_registers = amdgpu_read_registers;
 309    ws->base.get_chip_name = amdgpu_get_chip_name;
 310
 311    amdgpu_bo_init_functions(ws);
 312    amdgpu_cs_init_functions(ws);
 313    amdgpu_surface_init_functions(ws);
 314
 315    LIST_INITHEAD(&ws->global_bo_list);
 316    (void) mtx_init(&ws->global_bo_list_lock, mtx_plain);
 317    (void) mtx_init(&ws->bo_fence_lock, mtx_plain);
 318
 319    if (!util_queue_init(&ws->cs_queue, "amdgpu_cs", 8, 1,
 320                         UTIL_QUEUE_INIT_RESIZE_IF_FULL)) {
 321       amdgpu_winsys_destroy(&ws->base);
 322       mtx_unlock(&dev_tab_mutex);
 323       return NULL;
 324    }
 325
 326    /* Create the screen at the end. The winsys must be initialized
 327     * completely.
 328     *
 329     * Alternatively, we could create the screen based on "ws->gen"
 330     * and link all drivers into one binary blob. */
 331    ws->base.screen = screen_create(&ws->base, config);
 332    if (!ws->base.screen) {
 333       amdgpu_winsys_destroy(&ws->base);
 334       mtx_unlock(&dev_tab_mutex);
 335       return NULL;
 336    }
 337
 338    util_hash_table_set(dev_tab, dev, ws);
 339
 340    /* We must unlock the mutex once the winsys is fully initialized, so that
 341     * other threads attempting to create the winsys from the same fd will
 342     * get a fully initialized winsys and not just half-way initialized. */
 343    mtx_unlock(&dev_tab_mutex);
 344
 345    return &ws->base;
 346
 347 fail_cache:
 348    pb_cache_deinit(&ws->bo_cache);
 349    do_winsys_deinit(ws);
 350 fail_alloc:
 351    FREE(ws);
 352 fail:
 353    mtx_unlock(&dev_tab_mutex);
 354    return NULL;
 355 }