src/gallium/winsys/amdgpu/drm/amdgpu_winsys.c

   1 /*
   2  * Copyright © 2009 Corbin Simpson <MostAwesomeDude@gmail.com>
   3  * Copyright © 2009 Joakim Sindholt <opensource@zhasha.com>
   4  * Copyright © 2011 Marek Olšák <maraeo@gmail.com>
   5  * Copyright © 2015 Advanced Micro Devices, Inc.
   6  * All Rights Reserved.
   7  *
   8  * Permission is hereby granted, free of charge, to any person obtaining
   9  * a copy of this software and associated documentation files (the
  10  * "Software"), to deal in the Software without restriction, including
  11  * without limitation the rights to use, copy, modify, merge, publish,
  12  * distribute, sub license, and/or sell copies of the Software, and to
  13  * permit persons to whom the Software is furnished to do so, subject to
  14  * the following conditions:
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  17  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
  18  * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  19  * NON-INFRINGEMENT. IN NO EVENT SHALL THE COPYRIGHT HOLDERS, AUTHORS
  20  * AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  21  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  22  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
  23  * USE OR OTHER DEALINGS IN THE SOFTWARE.
  24  *
  25  * The above copyright notice and this permission notice (including the
  26  * next paragraph) shall be included in all copies or substantial portions
  27  * of the Software.
  28  */
  29 /*
  30  * Authors:
  31  *      Marek Olšák <maraeo@gmail.com>
  32  */
  33
  34 #include "amdgpu_cs.h"
  35 #include "amdgpu_public.h"
  36
  37 #include "util/u_hash_table.h"
  38 #include <amdgpu_drm.h>
  39 #include <xf86drm.h>
  40 #include <stdio.h>
  41 #include <sys/stat.h>
  42 #include "amdgpu_id.h"
  43
  44 #define CIK_TILE_MODE_COLOR_2D                  14
  45
  46 #define CIK__GB_TILE_MODE__PIPE_CONFIG(x)        (((x) >> 6) & 0x1f)
  47 #define     CIK__PIPE_CONFIG__ADDR_SURF_P2               0
  48 #define     CIK__PIPE_CONFIG__ADDR_SURF_P4_8x16          4
  49 #define     CIK__PIPE_CONFIG__ADDR_SURF_P4_16x16         5
  50 #define     CIK__PIPE_CONFIG__ADDR_SURF_P4_16x32         6
  51 #define     CIK__PIPE_CONFIG__ADDR_SURF_P4_32x32         7
  52 #define     CIK__PIPE_CONFIG__ADDR_SURF_P8_16x16_8x16    8
  53 #define     CIK__PIPE_CONFIG__ADDR_SURF_P8_16x32_8x16    9
  54 #define     CIK__PIPE_CONFIG__ADDR_SURF_P8_32x32_8x16    10
  55 #define     CIK__PIPE_CONFIG__ADDR_SURF_P8_16x32_16x16   11
  56 #define     CIK__PIPE_CONFIG__ADDR_SURF_P8_32x32_16x16   12
  57 #define     CIK__PIPE_CONFIG__ADDR_SURF_P8_32x32_16x32   13
  58 #define     CIK__PIPE_CONFIG__ADDR_SURF_P8_32x64_32x32   14
  59 #define     CIK__PIPE_CONFIG__ADDR_SURF_P16_32X32_8X16   16
  60 #define     CIK__PIPE_CONFIG__ADDR_SURF_P16_32X32_16X16  17
  61
  62 static struct util_hash_table *dev_tab = NULL;
  63 pipe_static_mutex(dev_tab_mutex);
  64
  65 static unsigned cik_get_num_tile_pipes(struct amdgpu_gpu_info *info)
  66 {
  67    unsigned mode2d = info->gb_tile_mode[CIK_TILE_MODE_COLOR_2D];
  68
  69    switch (CIK__GB_TILE_MODE__PIPE_CONFIG(mode2d)) {
  70    case CIK__PIPE_CONFIG__ADDR_SURF_P2:
  71        return 2;
  72    case CIK__PIPE_CONFIG__ADDR_SURF_P4_8x16:
  73    case CIK__PIPE_CONFIG__ADDR_SURF_P4_16x16:
  74    case CIK__PIPE_CONFIG__ADDR_SURF_P4_16x32:
  75    case CIK__PIPE_CONFIG__ADDR_SURF_P4_32x32:
  76        return 4;
  77    case CIK__PIPE_CONFIG__ADDR_SURF_P8_16x16_8x16:
  78    case CIK__PIPE_CONFIG__ADDR_SURF_P8_16x32_8x16:
  79    case CIK__PIPE_CONFIG__ADDR_SURF_P8_32x32_8x16:
  80    case CIK__PIPE_CONFIG__ADDR_SURF_P8_16x32_16x16:
  81    case CIK__PIPE_CONFIG__ADDR_SURF_P8_32x32_16x16:
  82    case CIK__PIPE_CONFIG__ADDR_SURF_P8_32x32_16x32:
  83    case CIK__PIPE_CONFIG__ADDR_SURF_P8_32x64_32x32:
  84        return 8;
  85    case CIK__PIPE_CONFIG__ADDR_SURF_P16_32X32_8X16:
  86    case CIK__PIPE_CONFIG__ADDR_SURF_P16_32X32_16X16:
  87        return 16;
  88    default:
  89        fprintf(stderr, "Invalid CIK pipe configuration, assuming P2\n");
  90        assert(!"this should never occur");
  91        return 2;
  92    }
  93 }
  94
  95 /* Helper function to do the ioctls needed for setup and init. */
  96 static boolean do_winsys_init(struct amdgpu_winsys *ws)
  97 {
  98    struct amdgpu_buffer_size_alignments alignment_info = {};
  99    struct amdgpu_heap_info vram, gtt;
 100    struct drm_amdgpu_info_hw_ip dma = {}, uvd = {}, vce = {};
 101    uint32_t vce_version = 0, vce_feature = 0;
 102    int r, i, j;
 103
 104    /* Query hardware and driver information. */
 105    r = amdgpu_query_gpu_info(ws->dev, &ws->amdinfo);
 106    if (r) {
 107       fprintf(stderr, "amdgpu: amdgpu_query_gpu_info failed.\n");
 108       goto fail;
 109    }
 110
 111    r = amdgpu_query_buffer_size_alignment(ws->dev, &alignment_info);
 112    if (r) {
 113       fprintf(stderr, "amdgpu: amdgpu_query_buffer_size_alignment failed.\n");
 114       goto fail;
 115    }
 116
 117    r = amdgpu_query_heap_info(ws->dev, AMDGPU_GEM_DOMAIN_VRAM, 0, &vram);
 118    if (r) {
 119       fprintf(stderr, "amdgpu: amdgpu_query_heap_info(vram) failed.\n");
 120       goto fail;
 121    }
 122
 123    r = amdgpu_query_heap_info(ws->dev, AMDGPU_GEM_DOMAIN_GTT, 0, &gtt);
 124    if (r) {
 125       fprintf(stderr, "amdgpu: amdgpu_query_heap_info(gtt) failed.\n");
 126       goto fail;
 127    }
 128
 129    r = amdgpu_query_hw_ip_info(ws->dev, AMDGPU_HW_IP_DMA, 0, &dma);
 130    if (r) {
 131       fprintf(stderr, "amdgpu: amdgpu_query_hw_ip_info(dma) failed.\n");
 132       goto fail;
 133    }
 134
 135    r = amdgpu_query_hw_ip_info(ws->dev, AMDGPU_HW_IP_UVD, 0, &uvd);
 136    if (r) {
 137       fprintf(stderr, "amdgpu: amdgpu_query_hw_ip_info(uvd) failed.\n");
 138       goto fail;
 139    }
 140
 141    r = amdgpu_query_hw_ip_info(ws->dev, AMDGPU_HW_IP_VCE, 0, &vce);
 142    if (r) {
 143       fprintf(stderr, "amdgpu: amdgpu_query_hw_ip_info(vce) failed.\n");
 144       goto fail;
 145    }
 146
 147    r = amdgpu_query_firmware_version(ws->dev, AMDGPU_INFO_FW_VCE, 0, 0,
 148                                      &vce_version, &vce_feature);
 149    if (r) {
 150       fprintf(stderr, "amdgpu: amdgpu_query_firmware_version(vce) failed.\n");
 151       goto fail;
 152    }
 153
 154    /* Set chip identification. */
 155    ws->info.pci_id = ws->amdinfo.asic_id; /* TODO: is this correct? */
 156    ws->info.vce_harvest_config = ws->amdinfo.vce_harvest_config;
 157
 158    switch (ws->info.pci_id) {
 159 #define CHIPSET(pci_id, name, cfamily) case pci_id: ws->info.family = CHIP_##cfamily; break;
 160 #include "pci_ids/radeonsi_pci_ids.h"
 161 #undef CHIPSET
 162
 163    default:
 164       fprintf(stderr, "amdgpu: Invalid PCI ID.\n");
 165       goto fail;
 166    }
 167
 168    if (ws->info.family >= CHIP_TONGA)
 169       ws->info.chip_class = VI;
 170    else if (ws->info.family >= CHIP_BONAIRE)
 171       ws->info.chip_class = CIK;
 172    else {
 173       fprintf(stderr, "amdgpu: Unknown family.\n");
 174       goto fail;
 175    }
 176
 177    /* LLVM 3.6 is required for VI. */
 178    if (ws->info.chip_class >= VI &&
 179        (HAVE_LLVM < 0x0306 ||
 180         (HAVE_LLVM == 0x0306 && MESA_LLVM_VERSION_PATCH < 1))) {
 181       fprintf(stderr, "amdgpu: LLVM 3.6.1 is required, got LLVM %i.%i.%i\n",
 182               HAVE_LLVM >> 8, HAVE_LLVM & 255, MESA_LLVM_VERSION_PATCH);
 183       goto fail;
 184    }
 185
 186    /* family and rev_id are for addrlib */
 187    switch (ws->info.family) {
 188    case CHIP_BONAIRE:
 189       ws->family = FAMILY_CI;
 190       ws->rev_id = CI_BONAIRE_M_A0;
 191       break;
 192    case CHIP_KAVERI:
 193       ws->family = FAMILY_KV;
 194       ws->rev_id = KV_SPECTRE_A0;
 195       break;
 196    case CHIP_KABINI:
 197       ws->family = FAMILY_KV;
 198       ws->rev_id = KB_KALINDI_A0;
 199       break;
 200    case CHIP_HAWAII:
 201       ws->family = FAMILY_CI;
 202       ws->rev_id = CI_HAWAII_P_A0;
 203       break;
 204    case CHIP_MULLINS:
 205       ws->family = FAMILY_KV;
 206       ws->rev_id = ML_GODAVARI_A0;
 207       break;
 208    case CHIP_TONGA:
 209       ws->family = FAMILY_VI;
 210       ws->rev_id = VI_TONGA_P_A0;
 211       break;
 212    case CHIP_ICELAND:
 213       ws->family = FAMILY_VI;
 214       ws->rev_id = VI_ICELAND_M_A0;
 215       break;
 216    case CHIP_CARRIZO:
 217       ws->family = FAMILY_CZ;
 218       ws->rev_id = CARRIZO_A0;
 219       break;
 220    case CHIP_STONEY:
 221       ws->family = FAMILY_CZ;
 222       ws->rev_id = STONEY_A0;
 223       break;
 224    case CHIP_FIJI:
 225       ws->family = FAMILY_VI;
 226       ws->rev_id = VI_FIJI_P_A0;
 227       break;
 228    default:
 229       fprintf(stderr, "amdgpu: Unknown family.\n");
 230       goto fail;
 231    }
 232
 233    ws->addrlib = amdgpu_addr_create(ws);
 234    if (!ws->addrlib) {
 235       fprintf(stderr, "amdgpu: Cannot create addrlib.\n");
 236       goto fail;
 237    }
 238
 239    /* Set hardware information. */
 240    ws->info.gart_size = gtt.heap_size;
 241    ws->info.vram_size = vram.heap_size;
 242    /* convert the shader clock from KHz to MHz */
 243    ws->info.max_shader_clock = ws->amdinfo.max_engine_clk / 1000;
 244    ws->info.max_se = ws->amdinfo.num_shader_engines;
 245    ws->info.max_sh_per_se = ws->amdinfo.num_shader_arrays_per_engine;
 246    ws->info.has_uvd = uvd.available_rings != 0;
 247    ws->info.vce_fw_version =
 248          vce.available_rings ? vce_version : 0;
 249    ws->info.has_userptr = TRUE;
 250    ws->info.num_render_backends = ws->amdinfo.rb_pipes;
 251    ws->info.clock_crystal_freq = ws->amdinfo.gpu_counter_freq;
 252    ws->info.num_tile_pipes = cik_get_num_tile_pipes(&ws->amdinfo);
 253    ws->info.pipe_interleave_bytes = 256 << ((ws->amdinfo.gb_addr_cfg >> 4) & 0x7);
 254    ws->info.has_virtual_memory = TRUE;
 255    ws->info.has_sdma = dma.available_rings != 0;
 256
 257    /* Get the number of good compute units. */
 258    ws->info.num_good_compute_units = 0;
 259    for (i = 0; i < ws->info.max_se; i++)
 260       for (j = 0; j < ws->info.max_sh_per_se; j++)
 261          ws->info.num_good_compute_units +=
 262             util_bitcount(ws->amdinfo.cu_bitmap[i][j]);
 263
 264    memcpy(ws->info.si_tile_mode_array, ws->amdinfo.gb_tile_mode,
 265           sizeof(ws->amdinfo.gb_tile_mode));
 266    ws->info.si_tile_mode_array_valid = TRUE;
 267    ws->info.enabled_rb_mask = ws->amdinfo.enabled_rb_pipes_mask;
 268
 269    memcpy(ws->info.cik_macrotile_mode_array, ws->amdinfo.gb_macro_tile_mode,
 270           sizeof(ws->amdinfo.gb_macro_tile_mode));
 271    ws->info.cik_macrotile_mode_array_valid = TRUE;
 272
 273    ws->gart_page_size = alignment_info.size_remote;
 274
 275    return TRUE;
 276
 277 fail:
 278    if (ws->addrlib)
 279       AddrDestroy(ws->addrlib);
 280    amdgpu_device_deinitialize(ws->dev);
 281    ws->dev = NULL;
 282    return FALSE;
 283 }
 284
 285 static void amdgpu_winsys_destroy(struct radeon_winsys *rws)
 286 {
 287    struct amdgpu_winsys *ws = (struct amdgpu_winsys*)rws;
 288
 289    pipe_mutex_destroy(ws->bo_fence_lock);
 290    pb_cache_deinit(&ws->bo_cache);
 291    pipe_mutex_destroy(ws->global_bo_list_lock);
 292    AddrDestroy(ws->addrlib);
 293    amdgpu_device_deinitialize(ws->dev);
 294    FREE(rws);
 295 }
 296
 297 static void amdgpu_winsys_query_info(struct radeon_winsys *rws,
 298                                      struct radeon_info *info)
 299 {
 300    *info = ((struct amdgpu_winsys *)rws)->info;
 301 }
 302
 303 static boolean amdgpu_cs_request_feature(struct radeon_winsys_cs *rcs,
 304                                          enum radeon_feature_id fid,
 305                                          boolean enable)
 306 {
 307    return FALSE;
 308 }
 309
 310 static uint64_t amdgpu_query_value(struct radeon_winsys *rws,
 311                                    enum radeon_value_id value)
 312 {
 313    struct amdgpu_winsys *ws = (struct amdgpu_winsys*)rws;
 314    struct amdgpu_heap_info heap;
 315    uint64_t retval = 0;
 316
 317    switch (value) {
 318    case RADEON_REQUESTED_VRAM_MEMORY:
 319       return ws->allocated_vram;
 320    case RADEON_REQUESTED_GTT_MEMORY:
 321       return ws->allocated_gtt;
 322    case RADEON_BUFFER_WAIT_TIME_NS:
 323       return ws->buffer_wait_time;
 324    case RADEON_TIMESTAMP:
 325       amdgpu_query_info(ws->dev, AMDGPU_INFO_TIMESTAMP, 8, &retval);
 326       return retval;
 327    case RADEON_NUM_CS_FLUSHES:
 328       return ws->num_cs_flushes;
 329    case RADEON_NUM_BYTES_MOVED:
 330       amdgpu_query_info(ws->dev, AMDGPU_INFO_NUM_BYTES_MOVED, 8, &retval);
 331       return retval;
 332    case RADEON_VRAM_USAGE:
 333       amdgpu_query_heap_info(ws->dev, AMDGPU_GEM_DOMAIN_VRAM, 0, &heap);
 334       return heap.heap_usage;
 335    case RADEON_GTT_USAGE:
 336       amdgpu_query_heap_info(ws->dev, AMDGPU_GEM_DOMAIN_GTT, 0, &heap);
 337       return heap.heap_usage;
 338    case RADEON_GPU_TEMPERATURE:
 339    case RADEON_CURRENT_SCLK:
 340    case RADEON_CURRENT_MCLK:
 341       return 0;
 342    case RADEON_GPU_RESET_COUNTER:
 343       assert(0);
 344       return 0;
 345    }
 346    return 0;
 347 }
 348
 349 static bool amdgpu_read_registers(struct radeon_winsys *rws,
 350                                   unsigned reg_offset,
 351                                   unsigned num_registers, uint32_t *out)
 352 {
 353    struct amdgpu_winsys *ws = (struct amdgpu_winsys*)rws;
 354
 355    return amdgpu_read_mm_registers(ws->dev, reg_offset / 4, num_registers,
 356                                    0xffffffff, 0, out) == 0;
 357 }
 358
 359 static unsigned hash_dev(void *key)
 360 {
 361 #if defined(PIPE_ARCH_X86_64)
 362    return pointer_to_intptr(key) ^ (pointer_to_intptr(key) >> 32);
 363 #else
 364    return pointer_to_intptr(key);
 365 #endif
 366 }
 367
 368 static int compare_dev(void *key1, void *key2)
 369 {
 370    return key1 != key2;
 371 }
 372
 373 static bool amdgpu_winsys_unref(struct radeon_winsys *rws)
 374 {
 375    struct amdgpu_winsys *ws = (struct amdgpu_winsys*)rws;
 376    bool destroy;
 377
 378    /* When the reference counter drops to zero, remove the device pointer
 379     * from the table.
 380     * This must happen while the mutex is locked, so that
 381     * amdgpu_winsys_create in another thread doesn't get the winsys
 382     * from the table when the counter drops to 0. */
 383    pipe_mutex_lock(dev_tab_mutex);
 384
 385    destroy = pipe_reference(&ws->reference, NULL);
 386    if (destroy && dev_tab)
 387       util_hash_table_remove(dev_tab, ws->dev);
 388
 389    pipe_mutex_unlock(dev_tab_mutex);
 390    return destroy;
 391 }
 392
 393 PUBLIC struct radeon_winsys *
 394 amdgpu_winsys_create(int fd, radeon_screen_create_t screen_create)
 395 {
 396    struct amdgpu_winsys *ws;
 397    drmVersionPtr version = drmGetVersion(fd);
 398    amdgpu_device_handle dev;
 399    uint32_t drm_major, drm_minor, r;
 400
 401    /* The DRM driver version of amdgpu is 3.x.x. */
 402    if (version->version_major != 3) {
 403       drmFreeVersion(version);
 404       return NULL;
 405    }
 406    drmFreeVersion(version);
 407
 408    /* Look up the winsys from the dev table. */
 409    pipe_mutex_lock(dev_tab_mutex);
 410    if (!dev_tab)
 411       dev_tab = util_hash_table_create(hash_dev, compare_dev);
 412
 413    /* Initialize the amdgpu device. This should always return the same pointer
 414     * for the same fd. */
 415    r = amdgpu_device_initialize(fd, &drm_major, &drm_minor, &dev);
 416    if (r) {
 417       pipe_mutex_unlock(dev_tab_mutex);
 418       fprintf(stderr, "amdgpu: amdgpu_device_initialize failed.\n");
 419       return NULL;
 420    }
 421
 422    /* Lookup a winsys if we have already created one for this device. */
 423    ws = util_hash_table_get(dev_tab, dev);
 424    if (ws) {
 425       pipe_reference(NULL, &ws->reference);
 426       pipe_mutex_unlock(dev_tab_mutex);
 427       return &ws->base;
 428    }
 429
 430    /* Create a new winsys. */
 431    ws = CALLOC_STRUCT(amdgpu_winsys);
 432    if (!ws) {
 433       pipe_mutex_unlock(dev_tab_mutex);
 434       return NULL;
 435    }
 436
 437    ws->dev = dev;
 438    ws->info.drm_major = drm_major;
 439    ws->info.drm_minor = drm_minor;
 440
 441    if (!do_winsys_init(ws))
 442       goto fail;
 443
 444    /* Create managers. */
 445    pb_cache_init(&ws->bo_cache, 500000, 2.0f, 0,
 446                  (ws->info.vram_size + ws->info.gart_size) / 8,
 447                  amdgpu_bo_destroy, amdgpu_bo_can_reclaim);
 448
 449    /* init reference */
 450    pipe_reference_init(&ws->reference, 1);
 451
 452    /* Set functions. */
 453    ws->base.unref = amdgpu_winsys_unref;
 454    ws->base.destroy = amdgpu_winsys_destroy;
 455    ws->base.query_info = amdgpu_winsys_query_info;
 456    ws->base.cs_request_feature = amdgpu_cs_request_feature;
 457    ws->base.query_value = amdgpu_query_value;
 458    ws->base.read_registers = amdgpu_read_registers;
 459
 460    amdgpu_bo_init_functions(ws);
 461    amdgpu_cs_init_functions(ws);
 462    amdgpu_surface_init_functions(ws);
 463
 464    LIST_INITHEAD(&ws->global_bo_list);
 465    pipe_mutex_init(ws->global_bo_list_lock);
 466    pipe_mutex_init(ws->bo_fence_lock);
 467
 468    /* Create the screen at the end. The winsys must be initialized
 469     * completely.
 470     *
 471     * Alternatively, we could create the screen based on "ws->gen"
 472     * and link all drivers into one binary blob. */
 473    ws->base.screen = screen_create(&ws->base);
 474    if (!ws->base.screen) {
 475       amdgpu_winsys_destroy(&ws->base);
 476       pipe_mutex_unlock(dev_tab_mutex);
 477       return NULL;
 478    }
 479
 480    util_hash_table_set(dev_tab, dev, ws);
 481
 482    /* We must unlock the mutex once the winsys is fully initialized, so that
 483     * other threads attempting to create the winsys from the same fd will
 484     * get a fully initialized winsys and not just half-way initialized. */
 485    pipe_mutex_unlock(dev_tab_mutex);
 486
 487    return &ws->base;
 488
 489 fail:
 490    pipe_mutex_unlock(dev_tab_mutex);
 491    pb_cache_deinit(&ws->bo_cache);
 492    FREE(ws);
 493    return NULL;
 494 }