src/gallium/winsys/amdgpu/drm/amdgpu_winsys.c

   1 /*
   2  * Copyright © 2009 Corbin Simpson <MostAwesomeDude@gmail.com>
   3  * Copyright © 2009 Joakim Sindholt <opensource@zhasha.com>
   4  * Copyright © 2011 Marek Olšák <maraeo@gmail.com>
   5  * Copyright © 2015 Advanced Micro Devices, Inc.
   6  * All Rights Reserved.
   7  *
   8  * Permission is hereby granted, free of charge, to any person obtaining
   9  * a copy of this software and associated documentation files (the
  10  * "Software"), to deal in the Software without restriction, including
  11  * without limitation the rights to use, copy, modify, merge, publish,
  12  * distribute, sub license, and/or sell copies of the Software, and to
  13  * permit persons to whom the Software is furnished to do so, subject to
  14  * the following conditions:
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  17  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
  18  * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  19  * NON-INFRINGEMENT. IN NO EVENT SHALL THE COPYRIGHT HOLDERS, AUTHORS
  20  * AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  21  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  22  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
  23  * USE OR OTHER DEALINGS IN THE SOFTWARE.
  24  *
  25  * The above copyright notice and this permission notice (including the
  26  * next paragraph) shall be included in all copies or substantial portions
  27  * of the Software.
  28  */
  29
  30 #include "amdgpu_cs.h"
  31 #include "amdgpu_public.h"
  32
  33 #include "util/u_cpu_detect.h"
  34 #include "util/u_hash_table.h"
  35 #include "util/hash_table.h"
  36 #include "util/xmlconfig.h"
  37 #include <amdgpu_drm.h>
  38 #include <xf86drm.h>
  39 #include <stdio.h>
  40 #include <sys/stat.h>
  41 #include "amd/common/sid.h"
  42 #include "amd/common/gfx9d.h"
  43
  44 #ifndef AMDGPU_INFO_NUM_VRAM_CPU_PAGE_FAULTS
  45 #define AMDGPU_INFO_NUM_VRAM_CPU_PAGE_FAULTS    0x1E
  46 #endif
  47
  48 static struct util_hash_table *dev_tab = NULL;
  49 static simple_mtx_t dev_tab_mutex = _SIMPLE_MTX_INITIALIZER_NP;
  50
  51 DEBUG_GET_ONCE_BOOL_OPTION(all_bos, "RADEON_ALL_BOS", false)
  52
  53 /* Helper function to do the ioctls needed for setup and init. */
  54 static bool do_winsys_init(struct amdgpu_winsys *ws,
  55                            const struct pipe_screen_config *config,
  56                            int fd)
  57 {
  58    if (!ac_query_gpu_info(fd, ws->dev, &ws->info, &ws->amdinfo))
  59       goto fail;
  60
  61    ws->addrlib = amdgpu_addr_create(&ws->info, &ws->amdinfo, &ws->info.max_alignment);
  62    if (!ws->addrlib) {
  63       fprintf(stderr, "amdgpu: Cannot create addrlib.\n");
  64       goto fail;
  65    }
  66
  67    ws->check_vm = strstr(debug_get_option("R600_DEBUG", ""), "check_vm") != NULL;
  68    ws->debug_all_bos = debug_get_option_all_bos();
  69    ws->reserve_vmid = strstr(debug_get_option("R600_DEBUG", ""), "reserve_vmid") != NULL;
  70    ws->zero_all_vram_allocs = strstr(debug_get_option("R600_DEBUG", ""), "zerovram") != NULL ||
  71       driQueryOptionb(config->options, "radeonsi_zerovram");
  72
  73    return true;
  74
  75 fail:
  76    amdgpu_device_deinitialize(ws->dev);
  77    ws->dev = NULL;
  78    return false;
  79 }
  80
  81 static void do_winsys_deinit(struct amdgpu_winsys *ws)
  82 {
  83    AddrDestroy(ws->addrlib);
  84    amdgpu_device_deinitialize(ws->dev);
  85 }
  86
  87 static void amdgpu_winsys_destroy(struct radeon_winsys *rws)
  88 {
  89    struct amdgpu_winsys *ws = (struct amdgpu_winsys*)rws;
  90
  91    if (ws->reserve_vmid)
  92       amdgpu_vm_unreserve_vmid(ws->dev, 0);
  93
  94    if (util_queue_is_initialized(&ws->cs_queue))
  95       util_queue_destroy(&ws->cs_queue);
  96
  97    simple_mtx_destroy(&ws->bo_fence_lock);
  98    pb_slabs_deinit(&ws->bo_slabs);
  99    pb_cache_deinit(&ws->bo_cache);
 100    util_hash_table_destroy(ws->bo_export_table);
 101    simple_mtx_destroy(&ws->global_bo_list_lock);
 102    simple_mtx_destroy(&ws->bo_export_table_lock);
 103    do_winsys_deinit(ws);
 104    FREE(rws);
 105 }
 106
 107 static void amdgpu_winsys_query_info(struct radeon_winsys *rws,
 108                                      struct radeon_info *info)
 109 {
 110    *info = ((struct amdgpu_winsys *)rws)->info;
 111 }
 112
 113 static bool amdgpu_cs_request_feature(struct radeon_cmdbuf *rcs,
 114                                       enum radeon_feature_id fid,
 115                                       bool enable)
 116 {
 117    return false;
 118 }
 119
 120 static uint64_t amdgpu_query_value(struct radeon_winsys *rws,
 121                                    enum radeon_value_id value)
 122 {
 123    struct amdgpu_winsys *ws = (struct amdgpu_winsys*)rws;
 124    struct amdgpu_heap_info heap;
 125    uint64_t retval = 0;
 126
 127    switch (value) {
 128    case RADEON_REQUESTED_VRAM_MEMORY:
 129       return ws->allocated_vram;
 130    case RADEON_REQUESTED_GTT_MEMORY:
 131       return ws->allocated_gtt;
 132    case RADEON_MAPPED_VRAM:
 133       return ws->mapped_vram;
 134    case RADEON_MAPPED_GTT:
 135       return ws->mapped_gtt;
 136    case RADEON_BUFFER_WAIT_TIME_NS:
 137       return ws->buffer_wait_time;
 138    case RADEON_NUM_MAPPED_BUFFERS:
 139       return ws->num_mapped_buffers;
 140    case RADEON_TIMESTAMP:
 141       amdgpu_query_info(ws->dev, AMDGPU_INFO_TIMESTAMP, 8, &retval);
 142       return retval;
 143    case RADEON_NUM_GFX_IBS:
 144       return ws->num_gfx_IBs;
 145    case RADEON_NUM_SDMA_IBS:
 146       return ws->num_sdma_IBs;
 147    case RADEON_GFX_BO_LIST_COUNTER:
 148       return ws->gfx_bo_list_counter;
 149    case RADEON_GFX_IB_SIZE_COUNTER:
 150       return ws->gfx_ib_size_counter;
 151    case RADEON_NUM_BYTES_MOVED:
 152       amdgpu_query_info(ws->dev, AMDGPU_INFO_NUM_BYTES_MOVED, 8, &retval);
 153       return retval;
 154    case RADEON_NUM_EVICTIONS:
 155       amdgpu_query_info(ws->dev, AMDGPU_INFO_NUM_EVICTIONS, 8, &retval);
 156       return retval;
 157    case RADEON_NUM_VRAM_CPU_PAGE_FAULTS:
 158       amdgpu_query_info(ws->dev, AMDGPU_INFO_NUM_VRAM_CPU_PAGE_FAULTS, 8, &retval);
 159       return retval;
 160    case RADEON_VRAM_USAGE:
 161       amdgpu_query_heap_info(ws->dev, AMDGPU_GEM_DOMAIN_VRAM, 0, &heap);
 162       return heap.heap_usage;
 163    case RADEON_VRAM_VIS_USAGE:
 164       amdgpu_query_heap_info(ws->dev, AMDGPU_GEM_DOMAIN_VRAM,
 165                              AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED, &heap);
 166       return heap.heap_usage;
 167    case RADEON_GTT_USAGE:
 168       amdgpu_query_heap_info(ws->dev, AMDGPU_GEM_DOMAIN_GTT, 0, &heap);
 169       return heap.heap_usage;
 170    case RADEON_GPU_TEMPERATURE:
 171       amdgpu_query_sensor_info(ws->dev, AMDGPU_INFO_SENSOR_GPU_TEMP, 4, &retval);
 172       return retval;
 173    case RADEON_CURRENT_SCLK:
 174       amdgpu_query_sensor_info(ws->dev, AMDGPU_INFO_SENSOR_GFX_SCLK, 4, &retval);
 175       return retval;
 176    case RADEON_CURRENT_MCLK:
 177       amdgpu_query_sensor_info(ws->dev, AMDGPU_INFO_SENSOR_GFX_MCLK, 4, &retval);
 178       return retval;
 179    case RADEON_GPU_RESET_COUNTER:
 180       assert(0);
 181       return 0;
 182    case RADEON_CS_THREAD_TIME:
 183       return util_queue_get_thread_time_nano(&ws->cs_queue, 0);
 184    }
 185    return 0;
 186 }
 187
 188 static bool amdgpu_read_registers(struct radeon_winsys *rws,
 189                                   unsigned reg_offset,
 190                                   unsigned num_registers, uint32_t *out)
 191 {
 192    struct amdgpu_winsys *ws = (struct amdgpu_winsys*)rws;
 193
 194    return amdgpu_read_mm_registers(ws->dev, reg_offset / 4, num_registers,
 195                                    0xffffffff, 0, out) == 0;
 196 }
 197
 198 static unsigned hash_pointer(void *key)
 199 {
 200    return _mesa_hash_pointer(key);
 201 }
 202
 203 static int compare_pointers(void *key1, void *key2)
 204 {
 205    return key1 != key2;
 206 }
 207
 208 static bool amdgpu_winsys_unref(struct radeon_winsys *rws)
 209 {
 210    struct amdgpu_winsys *ws = (struct amdgpu_winsys*)rws;
 211    bool destroy;
 212
 213    /* When the reference counter drops to zero, remove the device pointer
 214     * from the table.
 215     * This must happen while the mutex is locked, so that
 216     * amdgpu_winsys_create in another thread doesn't get the winsys
 217     * from the table when the counter drops to 0. */
 218    simple_mtx_lock(&dev_tab_mutex);
 219
 220    destroy = pipe_reference(&ws->reference, NULL);
 221    if (destroy && dev_tab) {
 222       util_hash_table_remove(dev_tab, ws->dev);
 223       if (util_hash_table_count(dev_tab) == 0) {
 224          util_hash_table_destroy(dev_tab);
 225          dev_tab = NULL;
 226       }
 227    }
 228
 229    simple_mtx_unlock(&dev_tab_mutex);
 230    return destroy;
 231 }
 232
 233 static const char* amdgpu_get_chip_name(struct radeon_winsys *ws)
 234 {
 235    amdgpu_device_handle dev = ((struct amdgpu_winsys *)ws)->dev;
 236    return amdgpu_get_marketing_name(dev);
 237 }
 238
 239 static void amdgpu_pin_threads_to_L3_cache(struct radeon_winsys *rws,
 240                                            unsigned cache)
 241 {
 242    struct amdgpu_winsys *ws = (struct amdgpu_winsys*)rws;
 243
 244    util_pin_thread_to_L3(ws->cs_queue.threads[0], cache,
 245                          util_cpu_caps.cores_per_L3);
 246 }
 247
 248 PUBLIC struct radeon_winsys *
 249 amdgpu_winsys_create(int fd, const struct pipe_screen_config *config,
 250                      radeon_screen_create_t screen_create)
 251 {
 252    struct amdgpu_winsys *ws;
 253    drmVersionPtr version = drmGetVersion(fd);
 254    amdgpu_device_handle dev;
 255    uint32_t drm_major, drm_minor, r;
 256
 257    /* The DRM driver version of amdgpu is 3.x.x. */
 258    if (version->version_major != 3) {
 259       drmFreeVersion(version);
 260       return NULL;
 261    }
 262    drmFreeVersion(version);
 263
 264    /* Look up the winsys from the dev table. */
 265    simple_mtx_lock(&dev_tab_mutex);
 266    if (!dev_tab)
 267       dev_tab = util_hash_table_create(hash_pointer, compare_pointers);
 268
 269    /* Initialize the amdgpu device. This should always return the same pointer
 270     * for the same fd. */
 271    r = amdgpu_device_initialize(fd, &drm_major, &drm_minor, &dev);
 272    if (r) {
 273       simple_mtx_unlock(&dev_tab_mutex);
 274       fprintf(stderr, "amdgpu: amdgpu_device_initialize failed.\n");
 275       return NULL;
 276    }
 277
 278    /* Lookup a winsys if we have already created one for this device. */
 279    ws = util_hash_table_get(dev_tab, dev);
 280    if (ws) {
 281       pipe_reference(NULL, &ws->reference);
 282       simple_mtx_unlock(&dev_tab_mutex);
 283
 284       /* Release the device handle, because we don't need it anymore.
 285        * This function is returning an existing winsys instance, which
 286        * has its own device handle.
 287        */
 288       amdgpu_device_deinitialize(dev);
 289       return &ws->base;
 290    }
 291
 292    /* Create a new winsys. */
 293    ws = CALLOC_STRUCT(amdgpu_winsys);
 294    if (!ws)
 295       goto fail;
 296
 297    ws->dev = dev;
 298    ws->info.drm_major = drm_major;
 299    ws->info.drm_minor = drm_minor;
 300
 301    if (!do_winsys_init(ws, config, fd))
 302       goto fail_alloc;
 303
 304    /* Create managers. */
 305    pb_cache_init(&ws->bo_cache, RADEON_MAX_CACHED_HEAPS,
 306                  500000, ws->check_vm ? 1.0f : 2.0f, 0,
 307                  (ws->info.vram_size + ws->info.gart_size) / 8,
 308                  amdgpu_bo_destroy, amdgpu_bo_can_reclaim);
 309
 310    if (!pb_slabs_init(&ws->bo_slabs,
 311                       AMDGPU_SLAB_MIN_SIZE_LOG2, AMDGPU_SLAB_MAX_SIZE_LOG2,
 312                       RADEON_MAX_SLAB_HEAPS,
 313                       ws,
 314                       amdgpu_bo_can_reclaim_slab,
 315                       amdgpu_bo_slab_alloc,
 316                       amdgpu_bo_slab_free))
 317       goto fail_cache;
 318
 319    ws->info.min_alloc_size = 1 << AMDGPU_SLAB_MIN_SIZE_LOG2;
 320
 321    /* init reference */
 322    pipe_reference_init(&ws->reference, 1);
 323
 324    /* Set functions. */
 325    ws->base.unref = amdgpu_winsys_unref;
 326    ws->base.destroy = amdgpu_winsys_destroy;
 327    ws->base.query_info = amdgpu_winsys_query_info;
 328    ws->base.cs_request_feature = amdgpu_cs_request_feature;
 329    ws->base.query_value = amdgpu_query_value;
 330    ws->base.read_registers = amdgpu_read_registers;
 331    ws->base.get_chip_name = amdgpu_get_chip_name;
 332    ws->base.pin_threads_to_L3_cache = amdgpu_pin_threads_to_L3_cache;
 333
 334    amdgpu_bo_init_functions(ws);
 335    amdgpu_cs_init_functions(ws);
 336    amdgpu_surface_init_functions(ws);
 337
 338    LIST_INITHEAD(&ws->global_bo_list);
 339    ws->bo_export_table = util_hash_table_create(hash_pointer, compare_pointers);
 340
 341    (void) simple_mtx_init(&ws->global_bo_list_lock, mtx_plain);
 342    (void) simple_mtx_init(&ws->bo_fence_lock, mtx_plain);
 343    (void) simple_mtx_init(&ws->bo_export_table_lock, mtx_plain);
 344
 345    if (!util_queue_init(&ws->cs_queue, "cs", 8, 1,
 346                         UTIL_QUEUE_INIT_RESIZE_IF_FULL)) {
 347       amdgpu_winsys_destroy(&ws->base);
 348       simple_mtx_unlock(&dev_tab_mutex);
 349       return NULL;
 350    }
 351
 352    /* Create the screen at the end. The winsys must be initialized
 353     * completely.
 354     *
 355     * Alternatively, we could create the screen based on "ws->gen"
 356     * and link all drivers into one binary blob. */
 357    ws->base.screen = screen_create(&ws->base, config);
 358    if (!ws->base.screen) {
 359       amdgpu_winsys_destroy(&ws->base);
 360       simple_mtx_unlock(&dev_tab_mutex);
 361       return NULL;
 362    }
 363
 364    util_hash_table_set(dev_tab, dev, ws);
 365
 366    if (ws->reserve_vmid) {
 367            r = amdgpu_vm_reserve_vmid(dev, 0);
 368            if (r) {
 369                 fprintf(stderr, "amdgpu: amdgpu_vm_reserve_vmid failed. (%i)\n", r);
 370                 goto fail_cache;
 371            }
 372    }
 373
 374    /* We must unlock the mutex once the winsys is fully initialized, so that
 375     * other threads attempting to create the winsys from the same fd will
 376     * get a fully initialized winsys and not just half-way initialized. */
 377    simple_mtx_unlock(&dev_tab_mutex);
 378
 379    return &ws->base;
 380
 381 fail_cache:
 382    pb_cache_deinit(&ws->bo_cache);
 383    do_winsys_deinit(ws);
 384 fail_alloc:
 385    FREE(ws);
 386 fail:
 387    simple_mtx_unlock(&dev_tab_mutex);
 388    return NULL;
 389 }