src/gallium/winsys/amdgpu/drm/amdgpu_winsys.c

   1 /*
   2  * Copyright © 2009 Corbin Simpson <MostAwesomeDude@gmail.com>
   3  * Copyright © 2009 Joakim Sindholt <opensource@zhasha.com>
   4  * Copyright © 2011 Marek Olšák <maraeo@gmail.com>
   5  * Copyright © 2015 Advanced Micro Devices, Inc.
   6  * All Rights Reserved.
   7  *
   8  * Permission is hereby granted, free of charge, to any person obtaining
   9  * a copy of this software and associated documentation files (the
  10  * "Software"), to deal in the Software without restriction, including
  11  * without limitation the rights to use, copy, modify, merge, publish,
  12  * distribute, sub license, and/or sell copies of the Software, and to
  13  * permit persons to whom the Software is furnished to do so, subject to
  14  * the following conditions:
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  17  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
  18  * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  19  * NON-INFRINGEMENT. IN NO EVENT SHALL THE COPYRIGHT HOLDERS, AUTHORS
  20  * AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  21  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  22  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
  23  * USE OR OTHER DEALINGS IN THE SOFTWARE.
  24  *
  25  * The above copyright notice and this permission notice (including the
  26  * next paragraph) shall be included in all copies or substantial portions
  27  * of the Software.
  28  */
  29 /*
  30  * Authors:
  31  *      Marek Olšák <maraeo@gmail.com>
  32  */
  33
  34 #include "amdgpu_cs.h"
  35 #include "amdgpu_public.h"
  36
  37 #include "util/u_hash_table.h"
  38 #include <amdgpu_drm.h>
  39 #include <xf86drm.h>
  40 #include <stdio.h>
  41 #include <sys/stat.h>
  42 #include "amd/common/amdgpu_id.h"
  43 #include "amd/common/sid.h"
  44 #include "amd/common/gfx9d.h"
  45
  46 #ifndef AMDGPU_INFO_NUM_VRAM_CPU_PAGE_FAULTS
  47 #define AMDGPU_INFO_NUM_VRAM_CPU_PAGE_FAULTS    0x1E
  48 #endif
  49
  50 static struct util_hash_table *dev_tab = NULL;
  51 static mtx_t dev_tab_mutex = _MTX_INITIALIZER_NP;
  52
  53 DEBUG_GET_ONCE_BOOL_OPTION(all_bos, "RADEON_ALL_BOS", false)
  54
  55 /* Helper function to do the ioctls needed for setup and init. */
  56 static bool do_winsys_init(struct amdgpu_winsys *ws, int fd)
  57 {
  58    if (!ac_query_gpu_info(fd, ws->dev, &ws->info, &ws->amdinfo))
  59       goto fail;
  60
  61    /* LLVM 5.0 is required for GFX9. */
  62    if (ws->info.chip_class >= GFX9 && HAVE_LLVM < 0x0500) {
  63       fprintf(stderr, "amdgpu: LLVM 5.0 is required, got LLVM %i.%i\n",
  64               HAVE_LLVM >> 8, HAVE_LLVM & 255);
  65       goto fail;
  66    }
  67
  68    ws->addrlib = amdgpu_addr_create(&ws->info, &ws->amdinfo, &ws->info.max_alignment);
  69    if (!ws->addrlib) {
  70       fprintf(stderr, "amdgpu: Cannot create addrlib.\n");
  71       goto fail;
  72    }
  73
  74    ws->check_vm = strstr(debug_get_option("R600_DEBUG", ""), "check_vm") != NULL;
  75    ws->debug_all_bos = debug_get_option_all_bos();
  76    ws->reserve_vmid = strstr(debug_get_option("R600_DEBUG", ""), "reserve_vmid") != NULL;
  77
  78    return true;
  79
  80 fail:
  81    amdgpu_device_deinitialize(ws->dev);
  82    ws->dev = NULL;
  83    return false;
  84 }
  85
  86 static void do_winsys_deinit(struct amdgpu_winsys *ws)
  87 {
  88    AddrDestroy(ws->addrlib);
  89    amdgpu_device_deinitialize(ws->dev);
  90 }
  91
  92 static void amdgpu_winsys_destroy(struct radeon_winsys *rws)
  93 {
  94    struct amdgpu_winsys *ws = (struct amdgpu_winsys*)rws;
  95
  96    if (util_queue_is_initialized(&ws->cs_queue))
  97       util_queue_destroy(&ws->cs_queue);
  98
  99    mtx_destroy(&ws->bo_fence_lock);
 100    pb_slabs_deinit(&ws->bo_slabs);
 101    pb_cache_deinit(&ws->bo_cache);
 102    mtx_destroy(&ws->global_bo_list_lock);
 103    do_winsys_deinit(ws);
 104    FREE(rws);
 105 }
 106
 107 static void amdgpu_winsys_query_info(struct radeon_winsys *rws,
 108                                      struct radeon_info *info)
 109 {
 110    *info = ((struct amdgpu_winsys *)rws)->info;
 111 }
 112
 113 static bool amdgpu_cs_request_feature(struct radeon_winsys_cs *rcs,
 114                                       enum radeon_feature_id fid,
 115                                       bool enable)
 116 {
 117    return false;
 118 }
 119
 120 static uint64_t amdgpu_query_value(struct radeon_winsys *rws,
 121                                    enum radeon_value_id value)
 122 {
 123    struct amdgpu_winsys *ws = (struct amdgpu_winsys*)rws;
 124    struct amdgpu_heap_info heap;
 125    uint64_t retval = 0;
 126
 127    switch (value) {
 128    case RADEON_REQUESTED_VRAM_MEMORY:
 129       return ws->allocated_vram;
 130    case RADEON_REQUESTED_GTT_MEMORY:
 131       return ws->allocated_gtt;
 132    case RADEON_MAPPED_VRAM:
 133       return ws->mapped_vram;
 134    case RADEON_MAPPED_GTT:
 135       return ws->mapped_gtt;
 136    case RADEON_BUFFER_WAIT_TIME_NS:
 137       return ws->buffer_wait_time;
 138    case RADEON_NUM_MAPPED_BUFFERS:
 139       return ws->num_mapped_buffers;
 140    case RADEON_TIMESTAMP:
 141       amdgpu_query_info(ws->dev, AMDGPU_INFO_TIMESTAMP, 8, &retval);
 142       return retval;
 143    case RADEON_NUM_GFX_IBS:
 144       return ws->num_gfx_IBs;
 145    case RADEON_NUM_SDMA_IBS:
 146       return ws->num_sdma_IBs;
 147    case RADEON_GFX_BO_LIST_COUNTER:
 148       return ws->gfx_bo_list_counter;
 149    case RADEON_GFX_IB_SIZE_COUNTER:
 150       return ws->gfx_ib_size_counter;
 151    case RADEON_NUM_BYTES_MOVED:
 152       amdgpu_query_info(ws->dev, AMDGPU_INFO_NUM_BYTES_MOVED, 8, &retval);
 153       return retval;
 154    case RADEON_NUM_EVICTIONS:
 155       amdgpu_query_info(ws->dev, AMDGPU_INFO_NUM_EVICTIONS, 8, &retval);
 156       return retval;
 157    case RADEON_NUM_VRAM_CPU_PAGE_FAULTS:
 158       amdgpu_query_info(ws->dev, AMDGPU_INFO_NUM_VRAM_CPU_PAGE_FAULTS, 8, &retval);
 159       return retval;
 160    case RADEON_VRAM_USAGE:
 161       amdgpu_query_heap_info(ws->dev, AMDGPU_GEM_DOMAIN_VRAM, 0, &heap);
 162       return heap.heap_usage;
 163    case RADEON_VRAM_VIS_USAGE:
 164       amdgpu_query_heap_info(ws->dev, AMDGPU_GEM_DOMAIN_VRAM,
 165                              AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED, &heap);
 166       return heap.heap_usage;
 167    case RADEON_GTT_USAGE:
 168       amdgpu_query_heap_info(ws->dev, AMDGPU_GEM_DOMAIN_GTT, 0, &heap);
 169       return heap.heap_usage;
 170    case RADEON_GPU_TEMPERATURE:
 171       amdgpu_query_sensor_info(ws->dev, AMDGPU_INFO_SENSOR_GPU_TEMP, 4, &retval);
 172       return retval;
 173    case RADEON_CURRENT_SCLK:
 174       amdgpu_query_sensor_info(ws->dev, AMDGPU_INFO_SENSOR_GFX_SCLK, 4, &retval);
 175       return retval;
 176    case RADEON_CURRENT_MCLK:
 177       amdgpu_query_sensor_info(ws->dev, AMDGPU_INFO_SENSOR_GFX_MCLK, 4, &retval);
 178       return retval;
 179    case RADEON_GPU_RESET_COUNTER:
 180       assert(0);
 181       return 0;
 182    case RADEON_CS_THREAD_TIME:
 183       return util_queue_get_thread_time_nano(&ws->cs_queue, 0);
 184    }
 185    return 0;
 186 }
 187
 188 static bool amdgpu_read_registers(struct radeon_winsys *rws,
 189                                   unsigned reg_offset,
 190                                   unsigned num_registers, uint32_t *out)
 191 {
 192    struct amdgpu_winsys *ws = (struct amdgpu_winsys*)rws;
 193
 194    return amdgpu_read_mm_registers(ws->dev, reg_offset / 4, num_registers,
 195                                    0xffffffff, 0, out) == 0;
 196 }
 197
 198 static unsigned hash_dev(void *key)
 199 {
 200 #if defined(PIPE_ARCH_X86_64)
 201    return pointer_to_intptr(key) ^ (pointer_to_intptr(key) >> 32);
 202 #else
 203    return pointer_to_intptr(key);
 204 #endif
 205 }
 206
 207 static int compare_dev(void *key1, void *key2)
 208 {
 209    return key1 != key2;
 210 }
 211
 212 static bool amdgpu_winsys_unref(struct radeon_winsys *rws)
 213 {
 214    struct amdgpu_winsys *ws = (struct amdgpu_winsys*)rws;
 215    bool destroy;
 216
 217    /* When the reference counter drops to zero, remove the device pointer
 218     * from the table.
 219     * This must happen while the mutex is locked, so that
 220     * amdgpu_winsys_create in another thread doesn't get the winsys
 221     * from the table when the counter drops to 0. */
 222    mtx_lock(&dev_tab_mutex);
 223
 224    destroy = pipe_reference(&ws->reference, NULL);
 225    if (destroy && dev_tab)
 226       util_hash_table_remove(dev_tab, ws->dev);
 227
 228    mtx_unlock(&dev_tab_mutex);
 229    return destroy;
 230 }
 231
 232 static const char* amdgpu_get_chip_name(struct radeon_winsys *ws)
 233 {
 234    amdgpu_device_handle dev = ((struct amdgpu_winsys *)ws)->dev;
 235    return amdgpu_get_marketing_name(dev);
 236 }
 237
 238
 239 PUBLIC struct radeon_winsys *
 240 amdgpu_winsys_create(int fd, const struct pipe_screen_config *config,
 241                      radeon_screen_create_t screen_create)
 242 {
 243    struct amdgpu_winsys *ws;
 244    drmVersionPtr version = drmGetVersion(fd);
 245    amdgpu_device_handle dev;
 246    uint32_t drm_major, drm_minor, r;
 247
 248    /* The DRM driver version of amdgpu is 3.x.x. */
 249    if (version->version_major != 3) {
 250       drmFreeVersion(version);
 251       return NULL;
 252    }
 253    drmFreeVersion(version);
 254
 255    /* Look up the winsys from the dev table. */
 256    mtx_lock(&dev_tab_mutex);
 257    if (!dev_tab)
 258       dev_tab = util_hash_table_create(hash_dev, compare_dev);
 259
 260    /* Initialize the amdgpu device. This should always return the same pointer
 261     * for the same fd. */
 262    r = amdgpu_device_initialize(fd, &drm_major, &drm_minor, &dev);
 263    if (r) {
 264       mtx_unlock(&dev_tab_mutex);
 265       fprintf(stderr, "amdgpu: amdgpu_device_initialize failed.\n");
 266       return NULL;
 267    }
 268
 269    /* Lookup a winsys if we have already created one for this device. */
 270    ws = util_hash_table_get(dev_tab, dev);
 271    if (ws) {
 272       pipe_reference(NULL, &ws->reference);
 273       mtx_unlock(&dev_tab_mutex);
 274       return &ws->base;
 275    }
 276
 277    /* Create a new winsys. */
 278    ws = CALLOC_STRUCT(amdgpu_winsys);
 279    if (!ws)
 280       goto fail;
 281
 282    ws->dev = dev;
 283    ws->info.drm_major = drm_major;
 284    ws->info.drm_minor = drm_minor;
 285
 286    if (!do_winsys_init(ws, fd))
 287       goto fail_alloc;
 288
 289    /* Create managers. */
 290    pb_cache_init(&ws->bo_cache, 500000, ws->check_vm ? 1.0f : 2.0f, 0,
 291                  (ws->info.vram_size + ws->info.gart_size) / 8,
 292                  amdgpu_bo_destroy, amdgpu_bo_can_reclaim);
 293
 294    if (!pb_slabs_init(&ws->bo_slabs,
 295                       AMDGPU_SLAB_MIN_SIZE_LOG2, AMDGPU_SLAB_MAX_SIZE_LOG2,
 296                       RADEON_MAX_SLAB_HEAPS,
 297                       ws,
 298                       amdgpu_bo_can_reclaim_slab,
 299                       amdgpu_bo_slab_alloc,
 300                       amdgpu_bo_slab_free))
 301       goto fail_cache;
 302
 303    ws->info.min_alloc_size = 1 << AMDGPU_SLAB_MIN_SIZE_LOG2;
 304
 305    /* init reference */
 306    pipe_reference_init(&ws->reference, 1);
 307
 308    /* Set functions. */
 309    ws->base.unref = amdgpu_winsys_unref;
 310    ws->base.destroy = amdgpu_winsys_destroy;
 311    ws->base.query_info = amdgpu_winsys_query_info;
 312    ws->base.cs_request_feature = amdgpu_cs_request_feature;
 313    ws->base.query_value = amdgpu_query_value;
 314    ws->base.read_registers = amdgpu_read_registers;
 315    ws->base.get_chip_name = amdgpu_get_chip_name;
 316
 317    amdgpu_bo_init_functions(ws);
 318    amdgpu_cs_init_functions(ws);
 319    amdgpu_surface_init_functions(ws);
 320
 321    LIST_INITHEAD(&ws->global_bo_list);
 322    (void) mtx_init(&ws->global_bo_list_lock, mtx_plain);
 323    (void) mtx_init(&ws->bo_fence_lock, mtx_plain);
 324
 325    if (!util_queue_init(&ws->cs_queue, "amdgpu_cs", 8, 1,
 326                         UTIL_QUEUE_INIT_RESIZE_IF_FULL)) {
 327       amdgpu_winsys_destroy(&ws->base);
 328       mtx_unlock(&dev_tab_mutex);
 329       return NULL;
 330    }
 331
 332    /* Create the screen at the end. The winsys must be initialized
 333     * completely.
 334     *
 335     * Alternatively, we could create the screen based on "ws->gen"
 336     * and link all drivers into one binary blob. */
 337    ws->base.screen = screen_create(&ws->base, config);
 338    if (!ws->base.screen) {
 339       amdgpu_winsys_destroy(&ws->base);
 340       mtx_unlock(&dev_tab_mutex);
 341       return NULL;
 342    }
 343
 344    util_hash_table_set(dev_tab, dev, ws);
 345
 346    /* We must unlock the mutex once the winsys is fully initialized, so that
 347     * other threads attempting to create the winsys from the same fd will
 348     * get a fully initialized winsys and not just half-way initialized. */
 349    mtx_unlock(&dev_tab_mutex);
 350
 351    return &ws->base;
 352
 353 fail_cache:
 354    pb_cache_deinit(&ws->bo_cache);
 355    do_winsys_deinit(ws);
 356 fail_alloc:
 357    FREE(ws);
 358 fail:
 359    mtx_unlock(&dev_tab_mutex);
 360    return NULL;
 361 }