2 * Copyright © 2009 Corbin Simpson
3 * Copyright © 2015 Advanced Micro Devices, Inc.
6 * Permission is hereby granted, free of charge, to any person obtaining
7 * a copy of this software and associated documentation files (the
8 * "Software"), to deal in the Software without restriction, including
9 * without limitation the rights to use, copy, modify, merge, publish,
10 * distribute, sub license, and/or sell copies of the Software, and to
11 * permit persons to whom the Software is furnished to do so, subject to
12 * the following conditions:
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
15 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
16 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
17 * NON-INFRINGEMENT. IN NO EVENT SHALL THE COPYRIGHT HOLDERS, AUTHORS
18 * AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
20 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
23 * The above copyright notice and this permission notice (including the
24 * next paragraph) shall be included in all copies or substantial portions
28 #ifndef AMDGPU_WINSYS_H
29 #define AMDGPU_WINSYS_H
31 #include "pipebuffer/pb_cache.h"
32 #include "pipebuffer/pb_slab.h"
33 #include "gallium/drivers/radeon/radeon_winsys.h"
34 #include "addrlib/inc/addrinterface.h"
35 #include "util/simple_mtx.h"
36 #include "util/u_queue.h"
41 #define NUM_SLAB_ALLOCATORS 3
43 struct amdgpu_winsys
{
44 struct pipe_reference reference
;
46 /* File descriptor which was passed to amdgpu_device_initialize */
49 struct pb_cache bo_cache
;
51 /* Each slab buffer can only contain suballocations of equal sizes, so we
52 * need to layer the allocators, so that we don't waste too much memory.
54 struct pb_slabs bo_slabs
[NUM_SLAB_ALLOCATORS
];
56 amdgpu_device_handle dev
;
58 simple_mtx_t bo_fence_lock
;
60 int num_cs
; /* The number of command streams created. */
61 unsigned num_total_rejected_cs
;
62 uint32_t surf_index_color
;
63 uint32_t surf_index_fmask
;
64 uint32_t next_bo_unique_id
;
65 uint64_t allocated_vram
;
66 uint64_t allocated_gtt
;
69 uint64_t buffer_wait_time
; /* time spent in buffer_wait in ns */
71 uint64_t num_sdma_IBs
;
72 uint64_t num_mapped_buffers
;
73 uint64_t gfx_bo_list_counter
;
74 uint64_t gfx_ib_size_counter
;
76 struct radeon_info info
;
78 /* multithreaded IB submission */
79 struct util_queue cs_queue
;
81 struct amdgpu_gpu_info amdinfo
;
87 bool zero_all_vram_allocs
;
89 /* List of all allocated buffers */
90 simple_mtx_t global_bo_list_lock
;
91 struct list_head global_bo_list
;
94 /* Single-linked list of all structs amdgpu_screen_winsys referencing this
95 * struct amdgpu_winsys
97 simple_mtx_t sws_list_lock
;
98 struct amdgpu_screen_winsys
*sws_list
;
100 /* For returning the same amdgpu_winsys_bo instance for exported
101 * and re-imported buffers. */
102 struct hash_table
*bo_export_table
;
103 simple_mtx_t bo_export_table_lock
;
106 struct amdgpu_screen_winsys
{
107 struct radeon_winsys base
;
108 struct amdgpu_winsys
*aws
;
110 struct pipe_reference reference
;
111 struct amdgpu_screen_winsys
*next
;
113 /* Maps a BO to its KMS handle valid for this DRM file descriptor
114 * Protected by amdgpu_winsys::sws_list_lock
116 struct hash_table
*kms_handles
;
119 static inline struct amdgpu_screen_winsys
*
120 amdgpu_screen_winsys(struct radeon_winsys
*base
)
122 return (struct amdgpu_screen_winsys
*)base
;
125 static inline struct amdgpu_winsys
*
126 amdgpu_winsys(struct radeon_winsys
*base
)
128 return amdgpu_screen_winsys(base
)->aws
;
131 void amdgpu_surface_init_functions(struct amdgpu_screen_winsys
*ws
);