src/gallium/winsys/amdgpu/drm/amdgpu_winsys.h

   1 /*
   2  * Copyright © 2009 Corbin Simpson
   3  * Copyright © 2015 Advanced Micro Devices, Inc.
   4  * All Rights Reserved.
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining
   7  * a copy of this software and associated documentation files (the
   8  * "Software"), to deal in the Software without restriction, including
   9  * without limitation the rights to use, copy, modify, merge, publish,
  10  * distribute, sub license, and/or sell copies of the Software, and to
  11  * permit persons to whom the Software is furnished to do so, subject to
  12  * the following conditions:
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  15  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
  16  * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  17  * NON-INFRINGEMENT. IN NO EVENT SHALL THE COPYRIGHT HOLDERS, AUTHORS
  18  * AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  20  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
  21  * USE OR OTHER DEALINGS IN THE SOFTWARE.
  22  *
  23  * The above copyright notice and this permission notice (including the
  24  * next paragraph) shall be included in all copies or substantial portions
  25  * of the Software.
  26  */
  27 /*
  28  * Authors:
  29  *      Marek Olšák <maraeo@gmail.com>
  30  */
  31
  32 #ifndef AMDGPU_WINSYS_H
  33 #define AMDGPU_WINSYS_H
  34
  35 #include "pipebuffer/pb_cache.h"
  36 #include "pipebuffer/pb_slab.h"
  37 #include "gallium/drivers/radeon/radeon_winsys.h"
  38 #include "addrlib/addrinterface.h"
  39 #include "util/u_queue.h"
  40 #include <amdgpu.h>
  41
  42 struct amdgpu_cs;
  43
  44 #define AMDGPU_SLAB_MIN_SIZE_LOG2   9  /* 512 bytes */
  45 #define AMDGPU_SLAB_MAX_SIZE_LOG2   16 /* 64 KB */
  46 #define AMDGPU_SLAB_BO_SIZE_LOG2    17 /* 128 KB */
  47
  48 struct amdgpu_winsys {
  49    struct radeon_winsys base;
  50    struct pipe_reference reference;
  51    struct pb_cache bo_cache;
  52    struct pb_slabs bo_slabs;
  53
  54    amdgpu_device_handle dev;
  55
  56    mtx_t bo_fence_lock;
  57
  58    int num_cs; /* The number of command streams created. */
  59    unsigned num_total_rejected_cs;
  60    uint32_t surf_index_color;
  61    uint32_t surf_index_fmask;
  62    uint32_t next_bo_unique_id;
  63    uint64_t allocated_vram;
  64    uint64_t allocated_gtt;
  65    uint64_t mapped_vram;
  66    uint64_t mapped_gtt;
  67    uint64_t buffer_wait_time; /* time spent in buffer_wait in ns */
  68    uint64_t num_gfx_IBs;
  69    uint64_t num_sdma_IBs;
  70    uint64_t num_mapped_buffers;
  71    uint64_t gfx_bo_list_counter;
  72    uint64_t gfx_ib_size_counter;
  73
  74    struct radeon_info info;
  75
  76    /* multithreaded IB submission */
  77    struct util_queue cs_queue;
  78
  79    struct amdgpu_gpu_info amdinfo;
  80    ADDR_HANDLE addrlib;
  81
  82    bool check_vm;
  83    bool debug_all_bos;
  84
  85    /* List of all allocated buffers */
  86    mtx_t global_bo_list_lock;
  87    struct list_head global_bo_list;
  88    unsigned num_buffers;
  89 };
  90
  91 static inline struct amdgpu_winsys *
  92 amdgpu_winsys(struct radeon_winsys *base)
  93 {
  94    return (struct amdgpu_winsys*)base;
  95 }
  96
  97 void amdgpu_surface_init_functions(struct amdgpu_winsys *ws);
  98
  99 #endif