src/gallium/winsys/dri/intel/server/i830_common.h

   1 /**************************************************************************
   2
   3 Copyright 2001 VA Linux Systems Inc., Fremont, California.
   4 Copyright 2002 Tungsten Graphics Inc., Cedar Park, Texas.
   5
   6 All Rights Reserved.
   7
   8 Permission is hereby granted, free of charge, to any person obtaining a
   9 copy of this software and associated documentation files (the "Software"),
  10 to deal in the Software without restriction, including without limitation
  11 on the rights to use, copy, modify, merge, publish, distribute, sub
  12 license, and/or sell copies of the Software, and to permit persons to whom
  13 the Software is furnished to do so, subject to the following conditions:
  14
  15 The above copyright notice and this permission notice (including the next
  16 paragraph) shall be included in all copies or substantial portions of the
  17 Software.
  18
  19 THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  20 IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  21 FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
  22 ATI, VA LINUX SYSTEMS AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
  23 DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
  24 OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
  25 USE OR OTHER DEALINGS IN THE SOFTWARE.
  26
  27 **************************************************************************/
  28
  29
  30 #ifndef _I830_COMMON_H_
  31 #define _I830_COMMON_H_
  32
  33
  34 #define I830_NR_TEX_REGIONS 255 /* maximum due to use of chars for next/prev */
  35 #define I830_LOG_MIN_TEX_REGION_SIZE 14
  36
  37
  38 /* Driver specific DRM command indices
  39  * NOTE: these are not OS specific, but they are driver specific
  40  */
  41 #define DRM_I830_INIT                     0x00
  42 #define DRM_I830_FLUSH                    0x01
  43 #define DRM_I830_FLIP                     0x02
  44 #define DRM_I830_BATCHBUFFER              0x03
  45 #define DRM_I830_IRQ_EMIT                 0x04
  46 #define DRM_I830_IRQ_WAIT                 0x05
  47 #define DRM_I830_GETPARAM                 0x06
  48 #define DRM_I830_SETPARAM                 0x07
  49 #define DRM_I830_ALLOC                    0x08
  50 #define DRM_I830_FREE                     0x09
  51 #define DRM_I830_INIT_HEAP                0x0a
  52 #define DRM_I830_CMDBUFFER                0x0b
  53 #define DRM_I830_DESTROY_HEAP             0x0c
  54 #define DRM_I830_SET_VBLANK_PIPE          0x0d
  55 #define DRM_I830_GET_VBLANK_PIPE          0x0e
  56 #define DRM_I830_MMIO                     0x10
  57
  58 typedef struct {
  59    enum {
  60       I830_INIT_DMA = 0x01,
  61       I830_CLEANUP_DMA = 0x02,
  62       I830_RESUME_DMA = 0x03
  63    } func;
  64    unsigned int mmio_offset;
  65    int sarea_priv_offset;
  66    unsigned int ring_start;
  67    unsigned int ring_end;
  68    unsigned int ring_size;
  69    unsigned int front_offset;
  70    unsigned int back_offset;
  71    unsigned int depth_offset;
  72    unsigned int w;
  73    unsigned int h;
  74    unsigned int pitch;
  75    unsigned int pitch_bits;
  76    unsigned int back_pitch;
  77    unsigned int depth_pitch;
  78    unsigned int cpp;
  79    unsigned int chipset;
  80 } drmI830Init;
  81
  82 typedef struct {
  83         drmTextureRegion texList[I830_NR_TEX_REGIONS+1];
  84         int last_upload;        /* last time texture was uploaded */
  85         int last_enqueue;       /* last time a buffer was enqueued */
  86         int last_dispatch;      /* age of the most recently dispatched buffer */
  87         int ctxOwner;           /* last context to upload state */
  88         /** Last context that used the buffer manager. */
  89         int texAge;
  90         int pf_enabled;         /* is pageflipping allowed? */
  91         int pf_active;
  92         int pf_current_page;    /* which buffer is being displayed? */
  93         int perf_boxes;         /* performance boxes to be displayed */
  94         int width, height;      /* screen size in pixels */
  95
  96         drm_handle_t front_handle;
  97         int front_offset;
  98         int front_size;
  99
 100         drm_handle_t back_handle;
 101         int back_offset;
 102         int back_size;
 103
 104         drm_handle_t depth_handle;
 105         int depth_offset;
 106         int depth_size;
 107
 108         drm_handle_t tex_handle;
 109         int tex_offset;
 110         int tex_size;
 111         int log_tex_granularity;
 112         int pitch;
 113         int rotation;           /* 0, 90, 180 or 270 */
 114         int rotated_offset;
 115         int rotated_size;
 116         int rotated_pitch;
 117         int virtualX, virtualY;
 118
 119         unsigned int front_tiled;
 120         unsigned int back_tiled;
 121         unsigned int depth_tiled;
 122         unsigned int rotated_tiled;
 123         unsigned int rotated2_tiled;
 124
 125         int planeA_x;
 126         int planeA_y;
 127         int planeA_w;
 128         int planeA_h;
 129         int planeB_x;
 130         int planeB_y;
 131         int planeB_w;
 132         int planeB_h;
 133
 134         /* Triple buffering */
 135         drm_handle_t third_handle;
 136         int third_offset;
 137         int third_size;
 138         unsigned int third_tiled;
 139
 140         /* buffer object handles for the static buffers.  May change
 141          * over the lifetime of the client, though it doesn't in our current
 142          * implementation.
 143          */
 144         unsigned int front_bo_handle;
 145         unsigned int back_bo_handle;
 146         unsigned int third_bo_handle;
 147         unsigned int depth_bo_handle;
 148 } drmI830Sarea;
 149
 150 /* Flags for perf_boxes
 151  */
 152 #define I830_BOX_RING_EMPTY    0x1 /* populated by kernel */
 153 #define I830_BOX_FLIP          0x2 /* populated by kernel */
 154 #define I830_BOX_WAIT          0x4 /* populated by kernel & client */
 155 #define I830_BOX_TEXTURE_LOAD  0x8 /* populated by kernel */
 156 #define I830_BOX_LOST_CONTEXT  0x10 /* populated by client */
 157
 158
 159 typedef struct {
 160         int start;              /* agp offset */
 161         int used;               /* nr bytes in use */
 162         int DR1;                /* hw flags for GFX_OP_DRAWRECT_INFO */
 163         int DR4;                /* window origin for GFX_OP_DRAWRECT_INFO*/
 164         int num_cliprects;      /* mulitpass with multiple cliprects? */
 165         drm_clip_rect_t *cliprects; /* pointer to userspace cliprects */
 166 } drmI830BatchBuffer;
 167
 168 typedef struct {
 169         char *buf;              /* agp offset */
 170         int sz;                 /* nr bytes in use */
 171         int DR1;                /* hw flags for GFX_OP_DRAWRECT_INFO */
 172         int DR4;                /* window origin for GFX_OP_DRAWRECT_INFO*/
 173         int num_cliprects;      /* mulitpass with multiple cliprects? */
 174         drm_clip_rect_t *cliprects; /* pointer to userspace cliprects */
 175 } drmI830CmdBuffer;
 176
 177 typedef struct {
 178         int *irq_seq;
 179 } drmI830IrqEmit;
 180
 181 typedef struct {
 182         int irq_seq;
 183 } drmI830IrqWait;
 184
 185 typedef struct {
 186         int param;
 187         int *value;
 188 } drmI830GetParam;
 189
 190 #define I830_PARAM_IRQ_ACTIVE     1
 191 #define I830_PARAM_ALLOW_BATCHBUFFER   2
 192
 193 typedef struct {
 194         int param;
 195         int value;
 196 } drmI830SetParam;
 197
 198 #define I830_SETPARAM_USE_MI_BATCHBUFFER_START  1
 199 #define I830_SETPARAM_TEX_LRU_LOG_GRANULARITY   2
 200 #define I830_SETPARAM_ALLOW_BATCHBUFFER         3
 201
 202
 203 /* A memory manager for regions of shared memory:
 204  */
 205 #define I830_MEM_REGION_AGP 1
 206
 207 typedef struct {
 208         int region;
 209         int alignment;
 210         int size;
 211         int *region_offset;     /* offset from start of fb or agp */
 212 } drmI830MemAlloc;
 213
 214 typedef struct {
 215         int region;
 216         int region_offset;
 217 } drmI830MemFree;
 218
 219 typedef struct {
 220         int region;
 221         int size;
 222         int start;
 223 } drmI830MemInitHeap;
 224
 225 typedef struct {
 226         int region;
 227 } drmI830MemDestroyHeap;
 228
 229 #define DRM_I830_VBLANK_PIPE_A  1
 230 #define DRM_I830_VBLANK_PIPE_B  2
 231
 232 typedef struct {
 233         int pipe;
 234 } drmI830VBlankPipe;
 235
 236 #define MMIO_READ  0
 237 #define MMIO_WRITE 1
 238
 239 #define MMIO_REGS_IA_PRIMATIVES_COUNT           0
 240 #define MMIO_REGS_IA_VERTICES_COUNT             1
 241 #define MMIO_REGS_VS_INVOCATION_COUNT           2
 242 #define MMIO_REGS_GS_PRIMITIVES_COUNT           3
 243 #define MMIO_REGS_GS_INVOCATION_COUNT           4
 244 #define MMIO_REGS_CL_PRIMITIVES_COUNT           5
 245 #define MMIO_REGS_CL_INVOCATION_COUNT           6
 246 #define MMIO_REGS_PS_INVOCATION_COUNT           7
 247 #define MMIO_REGS_PS_DEPTH_COUNT                8
 248
 249 typedef struct {
 250         unsigned int read_write:1;
 251         unsigned int reg:31;
 252         void __user *data;
 253 } drmI830MMIO;
 254
 255 #endif /* _I830_DRM_H_ */