src/gallium/winsys/drm/nouveau/nv04_surface.c

   1 #include "pipe/p_context.h"
   2 #include "pipe/p_format.h"
   3
   4 #include "nouveau_context.h"
   5
   6 static INLINE int log2i(int i)
   7 {
   8         int r = 0;
   9
  10         if (i & 0xffff0000) {
  11                 i >>= 16;
  12                 r += 16;
  13         }
  14         if (i & 0x0000ff00) {
  15                 i >>= 8;
  16                 r += 8;
  17         }
  18         if (i & 0x000000f0) {
  19                 i >>= 4;
  20                 r += 4;
  21         }
  22         if (i & 0x0000000c) {
  23                 i >>= 2;
  24                 r += 2;
  25         }
  26         if (i & 0x00000002) {
  27                 r += 1;
  28         }
  29         return r;
  30 }
  31
  32 static INLINE int
  33 nv04_surface_format(enum pipe_format format)
  34 {
  35         switch (format) {
  36         case PIPE_FORMAT_A8_UNORM:
  37                 return NV04_CONTEXT_SURFACES_2D_FORMAT_Y8;
  38         case PIPE_FORMAT_R5G6B5_UNORM:
  39                 return NV04_CONTEXT_SURFACES_2D_FORMAT_R5G6B5;
  40         case PIPE_FORMAT_A8R8G8B8_UNORM:
  41         case PIPE_FORMAT_Z24S8_UNORM:
  42                 return NV04_CONTEXT_SURFACES_2D_FORMAT_Y32;
  43         default:
  44                 return -1;
  45         }
  46 }
  47
  48 static INLINE int
  49 nv04_rect_format(enum pipe_format format)
  50 {
  51         switch (format) {
  52         case PIPE_FORMAT_A8_UNORM:
  53                 return NV04_GDI_RECTANGLE_TEXT_COLOR_FORMAT_A8R8G8B8;
  54         case PIPE_FORMAT_R5G6B5_UNORM:
  55                 return NV04_GDI_RECTANGLE_TEXT_COLOR_FORMAT_A16R5G6B5;
  56         case PIPE_FORMAT_A8R8G8B8_UNORM:
  57         case PIPE_FORMAT_Z24S8_UNORM:
  58                 return NV04_GDI_RECTANGLE_TEXT_COLOR_FORMAT_A8R8G8B8;
  59         default:
  60                 return -1;
  61         }
  62 }
  63
  64 static void
  65 nv04_surface_copy_m2mf(struct nouveau_context *nv, unsigned dx, unsigned dy,
  66                        unsigned sx, unsigned sy, unsigned w, unsigned h)
  67 {
  68         struct nouveau_channel *chan = nv->nvc->channel;
  69         struct pipe_surface *dst = nv->surf_dst;
  70         struct pipe_surface *src = nv->surf_src;
  71         unsigned dst_offset, src_offset;
  72
  73         dst_offset = dst->offset + (dy * dst->stride) + (dx * dst->block.size);
  74         src_offset = src->offset + (sy * src->stride) + (sx * src->block.size);
  75
  76         while (h) {
  77                 int count = (h > 2047) ? 2047 : h;
  78
  79                 BEGIN_RING(chan, nv->nvc->NvM2MF,
  80                            NV04_MEMORY_TO_MEMORY_FORMAT_OFFSET_IN, 8);
  81                 OUT_RELOCl(chan, nouveau_buffer(src->buffer)->bo, src_offset,
  82                            NOUVEAU_BO_VRAM | NOUVEAU_BO_GART | NOUVEAU_BO_RD);
  83                 OUT_RELOCl(chan, nouveau_buffer(dst->buffer)->bo, dst_offset,
  84                            NOUVEAU_BO_VRAM | NOUVEAU_BO_GART | NOUVEAU_BO_WR);
  85                 OUT_RING  (chan, src->stride);
  86                 OUT_RING  (chan, dst->stride);
  87                 OUT_RING  (chan, w * src->block.size);
  88                 OUT_RING  (chan, count);
  89                 OUT_RING  (chan, 0x0101);
  90                 OUT_RING  (chan, 0);
  91
  92                 h -= count;
  93                 src_offset += src->stride * count;
  94                 dst_offset += dst->stride * count;
  95         }
  96 }
  97
  98 static void
  99 nv04_surface_copy_blit(struct nouveau_context *nv, unsigned dx, unsigned dy,
 100                        unsigned sx, unsigned sy, unsigned w, unsigned h)
 101 {
 102         struct nouveau_channel *chan = nv->nvc->channel;
 103
 104         BEGIN_RING(chan, nv->nvc->NvImageBlit, 0x0300, 3);
 105         OUT_RING  (chan, (sy << 16) | sx);
 106         OUT_RING  (chan, (dy << 16) | dx);
 107         OUT_RING  (chan, ( h << 16) |  w);
 108 }
 109
 110 static int
 111 nv04_surface_copy_prep_swizzled(struct nouveau_context *nv,
 112                                 struct pipe_surface *dst,
 113                                 struct pipe_surface *src)
 114 {
 115         struct nouveau_channel *chan = nv->nvc->channel;
 116
 117         BEGIN_RING(chan, nv->nvc->NvSwzSurf,
 118                    NV04_SWIZZLED_SURFACE_FORMAT, 2);
 119         /* FIXME: read destination format from somewhere */
 120         OUT_RING  (chan,
 121                 NV04_SWIZZLED_SURFACE_FORMAT_COLOR_A8R8G8B8
 122                 | (log2i(dst->width)<<NV04_SWIZZLED_SURFACE_FORMAT_BASE_SIZE_U_SHIFT)
 123                 | (log2i(dst->height)<<NV04_SWIZZLED_SURFACE_FORMAT_BASE_SIZE_V_SHIFT) );
 124         OUT_RELOCo(chan, nouveau_buffer(dst->buffer)->bo,
 125                    NOUVEAU_BO_GART | NOUVEAU_BO_VRAM | NOUVEAU_BO_WR);
 126
 127         BEGIN_RING(chan, nv->nvc->NvSIFM, NV04_SCALED_IMAGE_FROM_MEMORY_COLOR_CONVERSION, 13);
 128         OUT_RING  (chan, NV04_SCALED_IMAGE_FROM_MEMORY_COLOR_CONVERSION_TRUNCATE);
 129         /* FIXME: read source format from somewhere */
 130         OUT_RING  (chan, NV04_SCALED_IMAGE_FROM_MEMORY_COLOR_FORMAT_A8R8G8B8);
 131         OUT_RING  (chan, NV04_SCALED_IMAGE_FROM_MEMORY_OPERATION_SRCCOPY);
 132         OUT_RING  (chan, 0);
 133         OUT_RING  (chan, (src->height<<16) | src->width);
 134         OUT_RING  (chan, 0);
 135         OUT_RING  (chan, (src->height<<16) | src->width);
 136         OUT_RING  (chan, 1<<20);
 137         OUT_RING  (chan, 1<<20);
 138         OUT_RING  (chan, (src->height<<16) | src->width);
 139         OUT_RING  (chan,
 140                 src->stride
 141                 | NV04_SCALED_IMAGE_FROM_MEMORY_FORMAT_ORIGIN_CENTER
 142                 | NV04_SCALED_IMAGE_FROM_MEMORY_FORMAT_FILTER_POINT_SAMPLE);
 143         OUT_RELOCo(chan, nouveau_buffer(src->buffer)->bo,
 144                    NOUVEAU_BO_GART | NOUVEAU_BO_VRAM | NOUVEAU_BO_WR);
 145         OUT_RING  (chan, 0);
 146
 147         BEGIN_RING(chan, nv->nvc->NvM2MF,
 148                    NV04_MEMORY_TO_MEMORY_FORMAT_DMA_BUFFER_IN, 2);
 149         OUT_RELOCo(chan, nouveau_buffer(src->buffer)->bo,
 150                    NOUVEAU_BO_GART | NOUVEAU_BO_VRAM | NOUVEAU_BO_RD);
 151         OUT_RELOCo(chan, nouveau_buffer(dst->buffer)->bo,
 152                    NOUVEAU_BO_GART | NOUVEAU_BO_VRAM | NOUVEAU_BO_WR);
 153
 154         nv->surface_copy = nv04_surface_copy_m2mf;
 155         nv->surf_dst = dst;
 156         nv->surf_src = src;
 157         return 0;
 158 }
 159
 160 static int
 161 nv04_surface_copy_prep(struct nouveau_context *nv, struct pipe_surface *dst,
 162                        struct pipe_surface *src)
 163 {
 164         struct nouveau_channel *chan = nv->nvc->channel;
 165         int format;
 166
 167         if (src->format != dst->format)
 168                 return 1;
 169
 170         /* Setup transfer to swizzle the texture to vram if needed */
 171         /* FIXME/TODO: check proper limits of this operation */
 172         if (nouveau_buffer(dst->buffer)->bo->flags & NOUVEAU_BO_SWIZZLED) {
 173                 /* FIXME: Disable it for the moment */
 174                 /*return nv04_surface_copy_prep_swizzled(nv, dst, src);*/
 175         }
 176
 177         /* NV_CONTEXT_SURFACES_2D has buffer alignment restrictions, fallback
 178          * to NV_MEMORY_TO_MEMORY_FORMAT in this case.
 179          */
 180         if ((src->offset & 63) || (dst->offset & 63)) {
 181                 BEGIN_RING(nv->nvc->channel, nv->nvc->NvM2MF,
 182                            NV04_MEMORY_TO_MEMORY_FORMAT_DMA_BUFFER_IN, 2);
 183                 OUT_RELOCo(chan, nouveau_buffer(src->buffer)->bo,
 184                            NOUVEAU_BO_GART | NOUVEAU_BO_VRAM | NOUVEAU_BO_RD);
 185                 OUT_RELOCo(chan, nouveau_buffer(dst->buffer)->bo,
 186                            NOUVEAU_BO_GART | NOUVEAU_BO_VRAM | NOUVEAU_BO_WR);
 187
 188                 nv->surface_copy = nv04_surface_copy_m2mf;
 189                 nv->surf_dst = dst;
 190                 nv->surf_src = src;
 191                 return 0;
 192
 193         }
 194
 195         if ((format = nv04_surface_format(dst->format)) < 0) {
 196                 NOUVEAU_ERR("Bad surface format 0x%x\n", dst->format);
 197                 return 1;
 198         }
 199         nv->surface_copy = nv04_surface_copy_blit;
 200
 201         BEGIN_RING(chan, nv->nvc->NvCtxSurf2D,
 202                    NV04_CONTEXT_SURFACES_2D_DMA_IMAGE_SOURCE, 2);
 203         OUT_RELOCo(chan, nouveau_buffer(src->buffer)->bo,
 204                    NOUVEAU_BO_VRAM | NOUVEAU_BO_RD);
 205         OUT_RELOCo(chan, nouveau_buffer(dst->buffer)->bo,
 206                    NOUVEAU_BO_VRAM | NOUVEAU_BO_WR);
 207
 208         BEGIN_RING(chan, nv->nvc->NvCtxSurf2D,
 209                    NV04_CONTEXT_SURFACES_2D_FORMAT, 4);
 210         OUT_RING  (chan, format);
 211         OUT_RING  (chan, (dst->stride << 16) | src->stride);
 212         OUT_RELOCl(chan, nouveau_buffer(src->buffer)->bo, src->offset,
 213                    NOUVEAU_BO_VRAM | NOUVEAU_BO_RD);
 214         OUT_RELOCl(chan, nouveau_buffer(dst->buffer)->bo, dst->offset,
 215                    NOUVEAU_BO_VRAM | NOUVEAU_BO_WR);
 216
 217         return 0;
 218 }
 219
 220 static void
 221 nv04_surface_copy_done(struct nouveau_context *nv)
 222 {
 223         FIRE_RING(nv->nvc->channel);
 224 }
 225
 226 static int
 227 nv04_surface_fill(struct nouveau_context *nv, struct pipe_surface *dst,
 228                   unsigned dx, unsigned dy, unsigned w, unsigned h,
 229                   unsigned value)
 230 {
 231         struct nouveau_channel *chan = nv->nvc->channel;
 232         struct nouveau_grobj *surf2d = nv->nvc->NvCtxSurf2D;
 233         struct nouveau_grobj *rect = nv->nvc->NvGdiRect;
 234         int cs2d_format, gdirect_format;
 235
 236         if ((cs2d_format = nv04_surface_format(dst->format)) < 0) {
 237                 NOUVEAU_ERR("Bad format = %d\n", dst->format);
 238                 return 1;
 239         }
 240
 241         if ((gdirect_format = nv04_rect_format(dst->format)) < 0) {
 242                 NOUVEAU_ERR("Bad format = %d\n", dst->format);
 243                 return 1;
 244         }
 245
 246         BEGIN_RING(chan, surf2d, NV04_CONTEXT_SURFACES_2D_DMA_IMAGE_SOURCE, 2);
 247         OUT_RELOCo(chan, nouveau_buffer(dst->buffer)->bo,
 248                    NOUVEAU_BO_VRAM | NOUVEAU_BO_WR);
 249         OUT_RELOCo(chan, nouveau_buffer(dst->buffer)->bo,
 250                    NOUVEAU_BO_VRAM | NOUVEAU_BO_WR);
 251         BEGIN_RING(chan, surf2d, NV04_CONTEXT_SURFACES_2D_FORMAT, 4);
 252         OUT_RING  (chan, cs2d_format);
 253         OUT_RING  (chan, (dst->stride << 16) | dst->stride);
 254         OUT_RELOCl(chan, nouveau_buffer(dst->buffer)->bo, dst->offset,
 255                    NOUVEAU_BO_VRAM | NOUVEAU_BO_WR);
 256         OUT_RELOCl(chan, nouveau_buffer(dst->buffer)->bo, dst->offset,
 257                    NOUVEAU_BO_VRAM | NOUVEAU_BO_WR);
 258
 259         BEGIN_RING(chan, rect, NV04_GDI_RECTANGLE_TEXT_COLOR_FORMAT, 1);
 260         OUT_RING  (chan, gdirect_format);
 261         BEGIN_RING(chan, rect, NV04_GDI_RECTANGLE_TEXT_COLOR1_A, 1);
 262         OUT_RING  (chan, value);
 263         BEGIN_RING(chan, rect,
 264                    NV04_GDI_RECTANGLE_TEXT_UNCLIPPED_RECTANGLE_POINT(0), 2);
 265         OUT_RING  (chan, (dx << 16) | dy);
 266         OUT_RING  (chan, ( w << 16) |  h);
 267
 268         FIRE_RING(chan);
 269         return 0;
 270 }
 271
 272 int
 273 nouveau_surface_channel_create_nv04(struct nouveau_channel_context *nvc)
 274 {
 275         struct nouveau_channel *chan = nvc->channel;
 276         unsigned chipset = nvc->channel->device->chipset, class;
 277         int ret;
 278
 279         if ((ret = nouveau_grobj_alloc(chan, nvc->next_handle++, 0x39,
 280                                        &nvc->NvM2MF))) {
 281                 NOUVEAU_ERR("Error creating m2mf object: %d\n", ret);
 282                 return 1;
 283         }
 284         BIND_RING (chan, nvc->NvM2MF, nvc->next_subchannel++);
 285         BEGIN_RING(chan, nvc->NvM2MF,
 286                    NV04_MEMORY_TO_MEMORY_FORMAT_DMA_NOTIFY, 1);
 287         OUT_RING  (chan, nvc->sync_notifier->handle);
 288
 289         class = chipset < 0x10 ? NV04_CONTEXT_SURFACES_2D :
 290                                  NV10_CONTEXT_SURFACES_2D;
 291         if ((ret = nouveau_grobj_alloc(chan, nvc->next_handle++, class,
 292                                        &nvc->NvCtxSurf2D))) {
 293                 NOUVEAU_ERR("Error creating 2D surface object: %d\n", ret);
 294                 return 1;
 295         }
 296         BIND_RING (chan, nvc->NvCtxSurf2D, nvc->next_subchannel++);
 297         BEGIN_RING(chan, nvc->NvCtxSurf2D,
 298                    NV04_CONTEXT_SURFACES_2D_DMA_IMAGE_SOURCE, 2);
 299         OUT_RING  (chan, nvc->channel->vram->handle);
 300         OUT_RING  (chan, nvc->channel->vram->handle);
 301
 302         class = chipset < 0x10 ? NV04_IMAGE_BLIT : NV12_IMAGE_BLIT;
 303         if ((ret = nouveau_grobj_alloc(chan, nvc->next_handle++, class,
 304                                        &nvc->NvImageBlit))) {
 305                 NOUVEAU_ERR("Error creating blit object: %d\n", ret);
 306                 return 1;
 307         }
 308         BIND_RING (chan, nvc->NvImageBlit, nvc->next_subchannel++);
 309         BEGIN_RING(chan, nvc->NvImageBlit, NV04_IMAGE_BLIT_DMA_NOTIFY, 1);
 310         OUT_RING  (chan, nvc->sync_notifier->handle);
 311         BEGIN_RING(chan, nvc->NvImageBlit, NV04_IMAGE_BLIT_SURFACE, 1);
 312         OUT_RING  (chan, nvc->NvCtxSurf2D->handle);
 313         BEGIN_RING(chan, nvc->NvImageBlit, NV04_IMAGE_BLIT_OPERATION, 1);
 314         OUT_RING  (chan, NV04_IMAGE_BLIT_OPERATION_SRCCOPY);
 315
 316         class = NV04_GDI_RECTANGLE_TEXT;
 317         if ((ret = nouveau_grobj_alloc(chan, nvc->next_handle++, class,
 318                                        &nvc->NvGdiRect))) {
 319                 NOUVEAU_ERR("Error creating rect object: %d\n", ret);
 320                 return 1;
 321         }
 322         BIND_RING (chan, nvc->NvGdiRect, nvc->next_subchannel++);
 323         BEGIN_RING(chan, nvc->NvGdiRect, NV04_GDI_RECTANGLE_TEXT_DMA_NOTIFY, 1);
 324         OUT_RING  (chan, nvc->sync_notifier->handle);
 325         BEGIN_RING(chan, nvc->NvGdiRect, NV04_GDI_RECTANGLE_TEXT_SURFACE, 1);
 326         OUT_RING  (chan, nvc->NvCtxSurf2D->handle);
 327         BEGIN_RING(chan, nvc->NvGdiRect, NV04_GDI_RECTANGLE_TEXT_OPERATION, 1);
 328         OUT_RING  (chan, NV04_GDI_RECTANGLE_TEXT_OPERATION_SRCCOPY);
 329         BEGIN_RING(chan, nvc->NvGdiRect,
 330                    NV04_GDI_RECTANGLE_TEXT_MONOCHROME_FORMAT, 1);
 331         OUT_RING  (chan, NV04_GDI_RECTANGLE_TEXT_MONOCHROME_FORMAT_LE);
 332
 333         switch (chipset & 0xf0) {
 334         case 0x00:
 335         case 0x10:
 336                 class = NV04_SWIZZLED_SURFACE;
 337                 break;
 338         case 0x20:
 339                 class = NV20_SWIZZLED_SURFACE;
 340                 break;
 341         case 0x30:
 342                 class = NV30_SWIZZLED_SURFACE;
 343                 break;
 344         case 0x40:
 345         case 0x60:
 346                 class = NV40_SWIZZLED_SURFACE;
 347                 break;
 348         default:
 349                 /* Famous last words: this really can't happen.. */
 350                 assert(0);
 351                 break;
 352         }
 353
 354         ret = nouveau_grobj_alloc(chan, nvc->next_handle++, class,
 355                                   &nvc->NvSwzSurf);
 356         if (ret) {
 357                 NOUVEAU_ERR("Error creating swizzled surface: %d\n", ret);
 358                 return 1;
 359         }
 360
 361         BIND_RING (chan, nvc->NvSwzSurf, nvc->next_subchannel++);
 362         BEGIN_RING(chan, nvc->NvSwzSurf, NV04_SWIZZLED_SURFACE_DMA_NOTIFY, 1);
 363         OUT_RING  (chan, nvc->sync_notifier->handle);
 364         BEGIN_RING(chan, nvc->NvSwzSurf, NV04_SWIZZLED_SURFACE_DMA_IMAGE, 1);
 365         OUT_RING  (chan, nvc->channel->vram->handle);
 366
 367         if (chipset < 0x10) {
 368                 class = NV04_SCALED_IMAGE_FROM_MEMORY;
 369         } else
 370         if (chipset < 0x40) {
 371                 class = NV10_SCALED_IMAGE_FROM_MEMORY;
 372         } else {
 373                 class = NV40_SCALED_IMAGE_FROM_MEMORY;
 374         }
 375
 376         ret = nouveau_grobj_alloc(chan, nvc->next_handle++, class,
 377                                   &nvc->NvSIFM);
 378         if (ret) {
 379                 NOUVEAU_ERR("Error creating scaled image object: %d\n", ret);
 380                 return 1;
 381         }
 382
 383         BIND_RING (chan, nvc->NvSIFM, nvc->next_subchannel++);
 384         BEGIN_RING(chan, nvc->NvSIFM, NV04_SCALED_IMAGE_FROM_MEMORY_DMA_NOTIFY, 1);
 385         OUT_RING  (chan, 0);
 386         BEGIN_RING(chan, nvc->NvSIFM, NV04_SCALED_IMAGE_FROM_MEMORY_DMA_IMAGE, 1);
 387         OUT_RING  (chan, nvc->channel->vram->handle);
 388         BEGIN_RING(chan, nvc->NvSIFM, NV04_SCALED_IMAGE_FROM_MEMORY_SURFACE, 1);
 389         OUT_RING  (chan, nvc->NvSwzSurf->handle);
 390         BEGIN_RING(chan, nvc->NvSIFM, NV04_SCALED_IMAGE_FROM_MEMORY_PATTERN, 1);
 391         OUT_RING  (chan, 0);
 392         BEGIN_RING(chan, nvc->NvSIFM, NV04_SCALED_IMAGE_FROM_MEMORY_ROP, 1);
 393         OUT_RING  (chan, 0);
 394         BEGIN_RING(chan, nvc->NvSIFM, NV04_SCALED_IMAGE_FROM_MEMORY_BETA1, 1);
 395         OUT_RING  (chan, 0);
 396         BEGIN_RING(chan, nvc->NvSIFM, NV04_SCALED_IMAGE_FROM_MEMORY_BETA4, 1);
 397         OUT_RING  (chan, 0);
 398         BEGIN_RING(chan, nvc->NvSIFM, NV04_SCALED_IMAGE_FROM_MEMORY_OPERATION, 1);
 399         OUT_RING  (chan, NV04_SCALED_IMAGE_FROM_MEMORY_OPERATION_SRCCOPY);
 400
 401         return 0;
 402 }
 403
 404 int
 405 nouveau_surface_init_nv04(struct nouveau_context *nv)
 406 {
 407         nv->surface_copy_prep = nv04_surface_copy_prep;
 408         nv->surface_copy = nv04_surface_copy_blit;
 409         nv->surface_copy_done = nv04_surface_copy_done;
 410         nv->surface_fill = nv04_surface_fill;
 411         return 0;
 412 }
 413