src/gallium/winsys/drm/radeon/core/radeon_buffer.c

   1 /*
   2  * Copyright © 2008 Jérôme Glisse
   3  *             2009 Corbin Simpson
   4  * All Rights Reserved.
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining
   7  * a copy of this software and associated documentation files (the
   8  * "Software"), to deal in the Software without restriction, including
   9  * without limitation the rights to use, copy, modify, merge, publish,
  10  * distribute, sub license, and/or sell copies of the Software, and to
  11  * permit persons to whom the Software is furnished to do so, subject to
  12  * the following conditions:
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  15  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
  16  * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  17  * NON-INFRINGEMENT. IN NO EVENT SHALL THE COPYRIGHT HOLDERS, AUTHORS
  18  * AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  20  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
  21  * USE OR OTHER DEALINGS IN THE SOFTWARE.
  22  *
  23  * The above copyright notice and this permission notice (including the
  24  * next paragraph) shall be included in all copies or substantial portions
  25  * of the Software.
  26  */
  27 /*
  28  * Authors:
  29  *      Jérôme Glisse <glisse@freedesktop.org>
  30  *      Corbin Simpson <MostAwesomeDude@gmail.com>
  31  */
  32
  33 #include "radeon_buffer.h"
  34
  35 #include "radeon_bo_gem.h"
  36 #include "softpipe/sp_texture.h"
  37 #include "r300_context.h"
  38 #include "util/u_format.h"
  39 #include "util/u_math.h"
  40 #include <X11/Xutil.h>
  41
  42 struct radeon_vl_context
  43 {
  44     Display *display;
  45     int screen;
  46     Drawable drawable;
  47 };
  48
  49 static const char *radeon_get_name(struct pipe_winsys *ws)
  50 {
  51     return "Radeon/GEM+KMS";
  52 }
  53
  54 static struct pipe_buffer *radeon_buffer_create(struct pipe_winsys *ws,
  55                                                 unsigned alignment,
  56                                                 unsigned usage,
  57                                                 unsigned size)
  58 {
  59     struct radeon_winsys *radeon_ws = (struct radeon_winsys *)ws;
  60     struct radeon_pipe_buffer *radeon_buffer;
  61     uint32_t domain;
  62
  63     radeon_buffer = CALLOC_STRUCT(radeon_pipe_buffer);
  64     if (radeon_buffer == NULL) {
  65         return NULL;
  66     }
  67
  68     pipe_reference_init(&radeon_buffer->base.reference, 1);
  69     radeon_buffer->base.alignment = alignment;
  70     radeon_buffer->base.usage = usage;
  71     radeon_buffer->base.size = size;
  72
  73     domain = 0;
  74
  75     if (usage & PIPE_BUFFER_USAGE_PIXEL) {
  76         domain |= RADEON_GEM_DOMAIN_VRAM;
  77     }
  78     if (usage & PIPE_BUFFER_USAGE_VERTEX) {
  79         domain |= RADEON_GEM_DOMAIN_GTT;
  80     }
  81     if (usage & PIPE_BUFFER_USAGE_INDEX) {
  82         domain |= RADEON_GEM_DOMAIN_GTT;
  83     }
  84
  85     radeon_buffer->bo = radeon_bo_open(radeon_ws->priv->bom, 0, size,
  86             alignment, domain, 0);
  87     if (radeon_buffer->bo == NULL) {
  88         FREE(radeon_buffer);
  89         return NULL;
  90     }
  91     return &radeon_buffer->base;
  92 }
  93
  94 static struct pipe_buffer *radeon_buffer_user_create(struct pipe_winsys *ws,
  95                                                      void *ptr,
  96                                                      unsigned bytes)
  97 {
  98     struct radeon_pipe_buffer *radeon_buffer;
  99
 100     radeon_buffer =
 101         (struct radeon_pipe_buffer*)radeon_buffer_create(ws, 0, 0, bytes);
 102     if (radeon_buffer == NULL) {
 103         return NULL;
 104     }
 105     radeon_bo_map(radeon_buffer->bo, 1);
 106     memcpy(radeon_buffer->bo->ptr, ptr, bytes);
 107     radeon_bo_unmap(radeon_buffer->bo);
 108     return &radeon_buffer->base;
 109 }
 110
 111 static struct pipe_buffer *radeon_surface_buffer_create(struct pipe_winsys *ws,
 112                                                         unsigned width,
 113                                                         unsigned height,
 114                                                         enum pipe_format format,
 115                                                         unsigned usage,
 116                                                         unsigned tex_usage,
 117                                                         unsigned *stride)
 118 {
 119     /* Radeons enjoy things in multiples of 32. */
 120     /* XXX this can be 32 when POT */
 121     const unsigned alignment = 64;
 122     unsigned nblocksy, size;
 123
 124     nblocksy = util_format_get_nblocksy(format, height);
 125     *stride = align(util_format_get_stride(format, width), alignment);
 126     size = *stride * nblocksy;
 127
 128     return radeon_buffer_create(ws, 64, usage, size);
 129 }
 130
 131 static void radeon_buffer_del(struct pipe_buffer *buffer)
 132 {
 133     struct radeon_pipe_buffer *radeon_buffer =
 134         (struct radeon_pipe_buffer*)buffer;
 135
 136     radeon_bo_unref(radeon_buffer->bo);
 137     free(radeon_buffer);
 138 }
 139
 140 static void *radeon_buffer_map(struct pipe_winsys *ws,
 141                                struct pipe_buffer *buffer,
 142                                unsigned flags)
 143 {
 144     struct radeon_winsys_priv *priv = ((struct radeon_winsys *)ws)->priv;
 145     struct radeon_pipe_buffer *radeon_buffer =
 146         (struct radeon_pipe_buffer*)buffer;
 147     int write = 0;
 148
 149     if (radeon_bo_is_referenced_by_cs(radeon_buffer->bo, priv->cs)) {
 150         priv->flush_cb(priv->flush_data);
 151     }
 152
 153     if (flags & PIPE_BUFFER_USAGE_DONTBLOCK) {
 154         uint32_t domain;
 155
 156         if (radeon_bo_is_busy(radeon_buffer->bo, &domain))
 157             return NULL;
 158     }
 159     if (flags & PIPE_BUFFER_USAGE_CPU_WRITE) {
 160         write = 1;
 161     }
 162
 163     if (radeon_bo_map(radeon_buffer->bo, write)) {
 164         return NULL;
 165     }
 166
 167     return radeon_buffer->bo->ptr;
 168 }
 169
 170 static void radeon_buffer_unmap(struct pipe_winsys *ws,
 171                                 struct pipe_buffer *buffer)
 172 {
 173     struct radeon_pipe_buffer *radeon_buffer =
 174         (struct radeon_pipe_buffer*)buffer;
 175
 176     radeon_bo_unmap(radeon_buffer->bo);
 177 }
 178
 179 static void radeon_fence_reference(struct pipe_winsys *ws,
 180                                    struct pipe_fence_handle **ptr,
 181                                    struct pipe_fence_handle *pfence)
 182 {
 183 }
 184
 185 static int radeon_fence_signalled(struct pipe_winsys *ws,
 186                                   struct pipe_fence_handle *pfence,
 187                                   unsigned flag)
 188 {
 189     return 1;
 190 }
 191
 192 static int radeon_fence_finish(struct pipe_winsys *ws,
 193                                struct pipe_fence_handle *pfence,
 194                                unsigned flag)
 195 {
 196     return 0;
 197 }
 198
 199 static void radeon_display_surface(struct pipe_winsys *pws,
 200                                    struct pipe_surface *psurf,
 201                                    struct radeon_vl_context *rvl_ctx)
 202 {
 203     struct r300_texture *r300tex = (struct r300_texture *)(psurf->texture);
 204     XImage *ximage;
 205     void *data;
 206
 207     ximage = XCreateImage(rvl_ctx->display,
 208                           XDefaultVisual(rvl_ctx->display, rvl_ctx->screen),
 209                           XDefaultDepth(rvl_ctx->display, rvl_ctx->screen),
 210                           ZPixmap, 0,   /* format, offset */
 211                           NULL,         /* data */
 212                           0, 0,         /* size */
 213                           32,           /* bitmap_pad */
 214                           0);           /* bytes_per_line */
 215
 216     assert(ximage->format);
 217     assert(ximage->bitmap_unit);
 218
 219     data = pws->buffer_map(pws, r300tex->buffer, 0);
 220
 221     /* update XImage's fields */
 222     ximage->data = data;
 223     ximage->width = psurf->width;
 224     ximage->height = psurf->height;
 225     ximage->bytes_per_line = psurf->width * (ximage->bits_per_pixel >> 3);
 226
 227     XPutImage(rvl_ctx->display, rvl_ctx->drawable,
 228               XDefaultGC(rvl_ctx->display, rvl_ctx->screen),
 229               ximage, 0, 0, 0, 0, psurf->width, psurf->height);
 230
 231     XSync(rvl_ctx->display, 0);
 232
 233     ximage->data = NULL;
 234     XDestroyImage(ximage);
 235
 236     pws->buffer_unmap(pws, r300tex->buffer);
 237 }
 238
 239 static void radeon_flush_frontbuffer(struct pipe_winsys *pipe_winsys,
 240                                      struct pipe_surface *pipe_surface,
 241                                      void *context_private)
 242 {
 243     struct radeon_vl_context *rvl_ctx;
 244     rvl_ctx = (struct radeon_vl_context *) context_private;
 245     radeon_display_surface(pipe_winsys, pipe_surface, rvl_ctx);
 246 }
 247
 248 struct radeon_winsys* radeon_pipe_winsys(int fd)
 249 {
 250     struct radeon_winsys* radeon_ws;
 251
 252     radeon_ws = CALLOC_STRUCT(radeon_winsys);
 253     if (radeon_ws == NULL) {
 254         return NULL;
 255     }
 256
 257     radeon_ws->priv = CALLOC_STRUCT(radeon_winsys_priv);
 258     if (radeon_ws->priv == NULL) {
 259         FREE(radeon_ws);
 260         return NULL;
 261     }
 262
 263     radeon_ws->priv->fd = fd;
 264     radeon_ws->priv->bom = radeon_bo_manager_gem_ctor(fd);
 265
 266     radeon_ws->base.flush_frontbuffer = radeon_flush_frontbuffer;
 267
 268     radeon_ws->base.buffer_create = radeon_buffer_create;
 269     radeon_ws->base.user_buffer_create = radeon_buffer_user_create;
 270     radeon_ws->base.surface_buffer_create = radeon_surface_buffer_create;
 271     radeon_ws->base.buffer_map = radeon_buffer_map;
 272     radeon_ws->base.buffer_unmap = radeon_buffer_unmap;
 273     radeon_ws->base.buffer_destroy = radeon_buffer_del;
 274
 275     radeon_ws->base.fence_reference = radeon_fence_reference;
 276     radeon_ws->base.fence_signalled = radeon_fence_signalled;
 277     radeon_ws->base.fence_finish = radeon_fence_finish;
 278
 279     radeon_ws->base.get_name = radeon_get_name;
 280
 281     return radeon_ws;
 282 }
 283 #if 0
 284 static struct pipe_buffer *radeon_buffer_from_handle(struct radeon_screen *radeon_screen,
 285                                                   uint32_t handle)
 286 {
 287     struct radeon_pipe_buffer *radeon_buffer;
 288     struct radeon_bo *bo = NULL;
 289
 290     bo = radeon_bo_open(radeon_screen->bom, handle, 0, 0, 0, 0);
 291     if (bo == NULL) {
 292         return NULL;
 293     }
 294     radeon_buffer = calloc(1, sizeof(struct radeon_pipe_buffer));
 295     if (radeon_buffer == NULL) {
 296         radeon_bo_unref(bo);
 297         return NULL;
 298     }
 299     pipe_reference_init(&radeon_buffer->base.reference, 1);
 300     radeon_buffer->base.usage = PIPE_BUFFER_USAGE_PIXEL;
 301     radeon_buffer->bo = bo;
 302     return &radeon_buffer->base;
 303 }
 304
 305 struct pipe_surface *radeon_surface_from_handle(struct radeon_context *radeon_context,
 306                                              uint32_t handle,
 307                                              enum pipe_format format,
 308                                              int w, int h, int pitch)
 309 {
 310     struct pipe_screen *pipe_screen = radeon_context->pipe_screen;
 311     struct pipe_winsys *pipe_winsys = radeon_context->pipe_winsys;
 312     struct pipe_texture tmpl;
 313     struct pipe_surface *ps;
 314     struct pipe_texture *pt;
 315     struct pipe_buffer *pb;
 316
 317     pb = radeon_buffer_from_handle(radeon_context->radeon_screen, handle);
 318     if (pb == NULL) {
 319         return NULL;
 320     }
 321     memset(&tmpl, 0, sizeof(tmpl));
 322     tmpl.tex_usage = PIPE_TEXTURE_USAGE_DISPLAY_TARGET;
 323     tmpl.target = PIPE_TEXTURE_2D;
 324     tmpl.width0 = w;
 325     tmpl.height0 = h;
 326     tmpl.depth0 = 1;
 327     tmpl.format = format;
 328
 329     pt = pipe_screen->texture_blanket(pipe_screen, &tmpl, &pitch, pb);
 330     if (pt == NULL) {
 331         pipe_buffer_reference(&pb, NULL);
 332     }
 333     ps = pipe_screen->get_tex_surface(pipe_screen, pt, 0, 0, 0,
 334                                       PIPE_BUFFER_USAGE_GPU_WRITE);
 335     return ps;
 336 }
 337 #endif