Merge branch 'mesa_7_5_branch'
[mesa.git] / src / gallium / winsys / drm / radeon / core / radeon_r300.c
1 /*
2 * Copyright 2008 Corbin Simpson <MostAwesomeDude@gmail.com>
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * on the rights to use, copy, modify, merge, publish, distribute, sub
8 * license, and/or sell copies of the Software, and to permit persons to whom
9 * the Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE. */
22
23 #include "radeon_r300.h"
24
25 static boolean radeon_r300_add_buffer(struct r300_winsys* winsys,
26 struct pipe_buffer* pbuffer,
27 uint32_t rd,
28 uint32_t wd)
29 {
30 int i;
31 struct radeon_winsys_priv* priv =
32 (struct radeon_winsys_priv*)winsys->radeon_winsys;
33 struct radeon_cs_space_check* sc = priv->sc;
34 struct radeon_bo* bo = ((struct radeon_pipe_buffer*)pbuffer)->bo;
35
36 /* Check to see if this BO is already in line for validation;
37 * find a slot for it otherwise. */
38 for (i = 0; i < priv->bo_count; i++) {
39 if (sc[i].bo == bo) {
40 sc[i].read_domains |= rd;
41 sc[i].write_domain |= wd;
42 return;
43 }
44 }
45
46 if (priv->bo_count >= RADEON_MAX_BOS) {
47 /* Dohoho. Not falling for that one again. Request a flush. */
48 return FALSE;
49 }
50
51 sc[priv->bo_count].bo = bo;
52 sc[priv->bo_count].read_domains = rd;
53 sc[priv->bo_count].write_domain = wd;
54 priv->bo_count++;
55
56 return TRUE;
57 }
58
59 static boolean radeon_r300_validate(struct r300_winsys* winsys)
60 {
61 int retval, i;
62 struct radeon_winsys_priv* priv =
63 (struct radeon_winsys_priv*)winsys->radeon_winsys;
64 struct radeon_cs_space_check* sc = priv->sc;
65
66 retval = radeon_cs_space_check(priv->cs, sc, priv->bo_count);
67
68 if (retval == RADEON_CS_SPACE_OP_TO_BIG) {
69 /* We might as well HCF, since this is not going to fit in the card,
70 * period. */
71 /* XXX just drop it on the floor instead */
72 exit(1);
73 } else if (retval == RADEON_CS_SPACE_FLUSH) {
74 /* We must flush before more rendering can commence. */
75 return TRUE;
76 }
77
78 /* XXX should probably be its own function */
79 for (i = 0; i < priv->bo_count; i++) {
80 if (sc[i].read_domains && sc[i].write_domain) {
81 /* Cute, cute. We need to flush first. */
82 debug_printf("radeon: BO %p can't be read and written; "
83 "requesting flush.\n", sc[i].bo);
84 return TRUE;
85 }
86 }
87
88 /* Things are fine, we can proceed as normal. */
89 return FALSE;
90 }
91
92 static boolean radeon_r300_check_cs(struct r300_winsys* winsys, int size)
93 {
94 /* XXX check size here, lazy ass! */
95 /* XXX also validate buffers */
96 return TRUE;
97 }
98
99 static void radeon_r300_begin_cs(struct r300_winsys* winsys,
100 int size,
101 const char* file,
102 const char* function,
103 int line)
104 {
105 struct radeon_winsys_priv* priv =
106 (struct radeon_winsys_priv*)winsys->radeon_winsys;
107
108 radeon_cs_begin(priv->cs, size, file, function, line);
109 }
110
111 static void radeon_r300_write_cs_dword(struct r300_winsys* winsys,
112 uint32_t dword)
113 {
114 struct radeon_winsys_priv* priv =
115 (struct radeon_winsys_priv*)winsys->radeon_winsys;
116
117 radeon_cs_write_dword(priv->cs, dword);
118 }
119
120 static void radeon_r300_write_cs_reloc(struct r300_winsys* winsys,
121 struct pipe_buffer* pbuffer,
122 uint32_t rd,
123 uint32_t wd,
124 uint32_t flags)
125 {
126 struct radeon_winsys_priv* priv =
127 (struct radeon_winsys_priv*)winsys->radeon_winsys;
128 int retval = 0;
129
130 retval = radeon_cs_write_reloc(priv->cs,
131 ((struct radeon_pipe_buffer*)pbuffer)->bo, rd, wd, flags);
132
133 if (retval) {
134 debug_printf("radeon: Relocation of %p (%d, %d, %d) failed!\n",
135 pbuffer, rd, wd, flags);
136 }
137 }
138
139 static void radeon_r300_end_cs(struct r300_winsys* winsys,
140 const char* file,
141 const char* function,
142 int line)
143 {
144 struct radeon_winsys_priv* priv =
145 (struct radeon_winsys_priv*)winsys->radeon_winsys;
146
147 radeon_cs_end(priv->cs, file, function, line);
148 }
149
150 static void radeon_r300_flush_cs(struct r300_winsys* winsys)
151 {
152 struct radeon_winsys_priv* priv =
153 (struct radeon_winsys_priv*)winsys->radeon_winsys;
154 struct radeon_cs_space_check* sc = priv->sc;
155 int retval = 1;
156
157 /* Emit the CS. */
158 retval = radeon_cs_emit(priv->cs);
159 if (retval) {
160 debug_printf("radeon: Bad CS, dumping...\n");
161 radeon_cs_print(priv->cs, stderr);
162 }
163 radeon_cs_erase(priv->cs);
164
165 /* Clean out BOs. */
166 memset(sc, 0, sizeof(struct radeon_cs_space_check) * RADEON_MAX_BOS);
167 priv->bo_count = 0;
168 }
169
170 /* Helper function to do the ioctls needed for setup and init. */
171 static void do_ioctls(struct r300_winsys* winsys, int fd)
172 {
173 struct drm_radeon_gem_info gem_info = {0};
174 drm_radeon_getparam_t gp = {0};
175 struct drm_radeon_info info = {0};
176 int target = 0;
177 int retval;
178
179 info.value = &target;
180 gp.value = &target;
181
182 /* First, get PCI ID */
183 info.request = RADEON_INFO_DEVICE_ID;
184 retval = drmCommandWriteRead(fd, DRM_RADEON_INFO, &info, sizeof(info));
185 if (retval) {
186 fprintf(stderr, "%s: New ioctl for PCI ID failed "
187 "(error number %d), trying classic ioctl...\n",
188 __FUNCTION__, retval);
189 gp.param = RADEON_PARAM_DEVICE_ID;
190 retval = drmCommandWriteRead(fd, DRM_RADEON_GETPARAM, &gp,
191 sizeof(gp));
192 if (retval) {
193 fprintf(stderr, "%s: Failed to get PCI ID, "
194 "error number %d\n", __FUNCTION__, retval);
195 exit(1);
196 }
197 }
198 winsys->pci_id = target;
199
200 /* Then, retrieve MM info */
201 retval = drmCommandWriteRead(fd, DRM_RADEON_GEM_INFO,
202 &gem_info, sizeof(gem_info));
203 if (retval) {
204 fprintf(stderr, "%s: Failed to get MM info, error number %d\n",
205 __FUNCTION__, retval);
206 exit(1);
207 }
208 winsys->gart_size = gem_info.gart_size;
209 /* XXX */
210 winsys->vram_size = gem_info.vram_visible;
211 }
212
213 struct r300_winsys*
214 radeon_create_r300_winsys(int fd, struct radeon_winsys* old_winsys)
215 {
216 struct r300_winsys* winsys = CALLOC_STRUCT(r300_winsys);
217 struct radeon_winsys_priv* priv;
218
219 if (winsys == NULL) {
220 return NULL;
221 }
222
223 priv = old_winsys->priv;
224
225 do_ioctls(winsys, fd);
226
227 priv->csm = radeon_cs_manager_gem_ctor(fd);
228
229 priv->cs = radeon_cs_create(priv->csm, 1024 * 64 / 4);
230 radeon_cs_set_limit(priv->cs,
231 RADEON_GEM_DOMAIN_GTT, winsys->gart_size);
232 radeon_cs_set_limit(priv->cs,
233 RADEON_GEM_DOMAIN_VRAM, winsys->vram_size);
234
235 winsys->add_buffer = radeon_r300_add_buffer;
236 winsys->validate = radeon_r300_validate;
237
238 winsys->check_cs = radeon_r300_check_cs;
239 winsys->begin_cs = radeon_r300_begin_cs;
240 winsys->write_cs_dword = radeon_r300_write_cs_dword;
241 winsys->write_cs_reloc = radeon_r300_write_cs_reloc;
242 winsys->end_cs = radeon_r300_end_cs;
243 winsys->flush_cs = radeon_r300_flush_cs;
244
245 memcpy(winsys, old_winsys, sizeof(struct radeon_winsys));
246
247 return winsys;
248 }