src/gallium/winsys/intel/intel_winsys.h

   1 /*
   2  * Mesa 3-D graphics library
   3  *
   4  * Copyright (C) 2012-2014 LunarG, Inc.
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a
   7  * copy of this software and associated documentation files (the "Software"),
   8  * to deal in the Software without restriction, including without limitation
   9  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  10  * and/or sell copies of the Software, and to permit persons to whom the
  11  * Software is furnished to do so, subject to the following conditions:
  12  *
  13  * The above copyright notice and this permission notice shall be included
  14  * in all copies or substantial portions of the Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  19  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  20  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  21  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  22  * DEALINGS IN THE SOFTWARE.
  23  *
  24  * Authors:
  25  *    Chia-I Wu <olv@lunarg.com>
  26  */
  27
  28 #ifndef INTEL_WINSYS_H
  29 #define INTEL_WINSYS_H
  30
  31 #include "pipe/p_compiler.h"
  32
  33 /* this is compatible with i915_drm.h's definitions */
  34 enum intel_ring_type {
  35    INTEL_RING_RENDER    = 1,
  36    INTEL_RING_BSD       = 2,
  37    INTEL_RING_BLT       = 3,
  38    INTEL_RING_VEBOX     = 4,
  39 };
  40
  41 /* this is compatible with i915_drm.h's definitions */
  42 enum intel_exec_flag {
  43    INTEL_EXEC_GEN7_SOL_RESET  = 1 << 8,
  44 };
  45
  46 /* this is compatible with i915_drm.h's definitions */
  47 enum intel_domain_flag {
  48    INTEL_DOMAIN_CPU           = 0x00000001,
  49    INTEL_DOMAIN_RENDER        = 0x00000002,
  50    INTEL_DOMAIN_SAMPLER       = 0x00000004,
  51    INTEL_DOMAIN_COMMAND       = 0x00000008,
  52    INTEL_DOMAIN_INSTRUCTION   = 0x00000010,
  53    INTEL_DOMAIN_VERTEX        = 0x00000020,
  54    INTEL_DOMAIN_GTT           = 0x00000040,
  55 };
  56
  57 /* this is compatible with i915_drm.h's definitions */
  58 enum intel_tiling_mode {
  59    INTEL_TILING_NONE = 0,
  60    INTEL_TILING_X    = 1,
  61    INTEL_TILING_Y    = 2,
  62 };
  63
  64 struct winsys_handle;
  65 struct intel_winsys;
  66 struct intel_context;
  67 struct intel_bo;
  68
  69 struct intel_winsys_info {
  70    int devid;
  71
  72    int max_batch_size;
  73    bool has_llc;
  74    bool has_address_swizzling;
  75    bool has_logical_context;
  76    bool has_ppgtt;
  77
  78    /* valid registers for intel_winsys_read_reg() */
  79    bool has_timestamp;
  80
  81    /* valid flags for intel_winsys_submit_bo() */
  82    bool has_gen7_sol_reset;
  83 };
  84
  85 struct intel_winsys *
  86 intel_winsys_create_for_fd(int fd);
  87
  88 void
  89 intel_winsys_destroy(struct intel_winsys *winsys);
  90
  91 const struct intel_winsys_info *
  92 intel_winsys_get_info(const struct intel_winsys *winsys);
  93
  94 /**
  95  * Create a logical context for use with the render ring.
  96  */
  97 struct intel_context *
  98 intel_winsys_create_context(struct intel_winsys *winsys);
  99
 100 /**
 101  * Destroy a logical context.
 102  */
 103 void
 104 intel_winsys_destroy_context(struct intel_winsys *winsys,
 105                              struct intel_context *ctx);
 106
 107 /**
 108  * Read a register.  Only registers that are considered safe, such as
 109  *
 110  *   TIMESTAMP (0x2358)
 111  *
 112  * can be read.
 113  */
 114 int
 115 intel_winsys_read_reg(struct intel_winsys *winsys,
 116                       uint32_t reg, uint64_t *val);
 117
 118 /**
 119  * Allocate a buffer object.
 120  *
 121  * \param name             Informative description of the bo.
 122  * \param tiling           Tiling mode.
 123  * \param pitch            Pitch of the bo.
 124  * \param height           Height of the bo.
 125  * \param initial_domain   Initial (write) domain.
 126  */
 127 struct intel_bo *
 128 intel_winsys_alloc_bo(struct intel_winsys *winsys,
 129                       const char *name,
 130                       enum intel_tiling_mode tiling,
 131                       unsigned long pitch,
 132                       unsigned long height,
 133                       uint32_t initial_domain);
 134
 135 /**
 136  * Allocate a linear buffer object.
 137  */
 138 static inline struct intel_bo *
 139 intel_winsys_alloc_buffer(struct intel_winsys *winsys,
 140                           const char *name,
 141                           unsigned long size,
 142                           uint32_t initial_domain)
 143 {
 144    return intel_winsys_alloc_bo(winsys, name,
 145          INTEL_TILING_NONE, size, 1, initial_domain);
 146 }
 147
 148 /**
 149  * Create a bo from a winsys handle.
 150  */
 151 struct intel_bo *
 152 intel_winsys_import_handle(struct intel_winsys *winsys,
 153                            const char *name,
 154                            const struct winsys_handle *handle,
 155                            unsigned long height,
 156                            enum intel_tiling_mode *tiling,
 157                            unsigned long *pitch);
 158
 159 /**
 160  * Export \p bo as a winsys handle for inter-process sharing.
 161  */
 162 int
 163 intel_winsys_export_handle(struct intel_winsys *winsys,
 164                            struct intel_bo *bo,
 165                            enum intel_tiling_mode tiling,
 166                            unsigned long pitch,
 167                            unsigned long height,
 168                            struct winsys_handle *handle);
 169
 170 /**
 171  * Return true when buffer objects directly specified in \p bo_array, and
 172  * those indirectly referenced by them, can fit in the aperture space.
 173  */
 174 bool
 175 intel_winsys_can_submit_bo(struct intel_winsys *winsys,
 176                            struct intel_bo **bo_array,
 177                            int count);
 178
 179 /**
 180  * Submit \p bo for execution.
 181  *
 182  * \p bo and all bos referenced by \p bo will be considered busy until all
 183  * commands are parsed and executed.  \p ctx is ignored when the bo is not
 184  * submitted to the render ring.
 185  */
 186 int
 187 intel_winsys_submit_bo(struct intel_winsys *winsys,
 188                        enum intel_ring_type ring,
 189                        struct intel_bo *bo, int used,
 190                        struct intel_context *ctx,
 191                        unsigned long flags);
 192
 193 /**
 194  * Decode the commands contained in \p bo.  For debugging.
 195  *
 196  * \param bo      Batch buffer to decode.
 197  * \param used    Size of the commands in bytes.
 198  */
 199 void
 200 intel_winsys_decode_bo(struct intel_winsys *winsys,
 201                        struct intel_bo *bo, int used);
 202
 203 /**
 204  * Increase the reference count of \p bo.
 205  */
 206 void
 207 intel_bo_reference(struct intel_bo *bo);
 208
 209 /**
 210  * Decrease the reference count of \p bo.  When the reference count reaches
 211  * zero, \p bo is destroyed.
 212  */
 213 void
 214 intel_bo_unreference(struct intel_bo *bo);
 215
 216 /**
 217  * Map \p bo for CPU access.  Recursive mapping is allowed.
 218  *
 219  * map() maps the backing store into CPU address space, cached.  It will block
 220  * if the bo is busy.  This variant allows fastest random reads and writes,
 221  * but the caller needs to handle tiling or swizzling manually if the bo is
 222  * tiled or swizzled.  If write is enabled and there is no shared last-level
 223  * cache (LLC), the CPU cache will be flushed, which is expensive.
 224  *
 225  * map_gtt() maps the bo for MMIO access, uncached but write-combined.  It
 226  * will block if the bo is busy.  This variant promises a reasonable speed for
 227  * sequential writes, but reads would be very slow.  Callers always have a
 228  * linear view of the bo.
 229  *
 230  * map_unsynchronized() is similar to map_gtt(), except that it does not
 231  * block.
 232  */
 233 void *
 234 intel_bo_map(struct intel_bo *bo, bool write_enable);
 235
 236 void *
 237 intel_bo_map_gtt(struct intel_bo *bo);
 238
 239 void *
 240 intel_bo_map_unsynchronized(struct intel_bo *bo);
 241
 242 /**
 243  * Unmap \p bo.
 244  */
 245 void
 246 intel_bo_unmap(struct intel_bo *bo);
 247
 248 /**
 249  * Write data to \p bo.
 250  */
 251 int
 252 intel_bo_pwrite(struct intel_bo *bo, unsigned long offset,
 253                 unsigned long size, const void *data);
 254
 255 /**
 256  * Read data from the bo.
 257  */
 258 int
 259 intel_bo_pread(struct intel_bo *bo, unsigned long offset,
 260                unsigned long size, void *data);
 261
 262 /**
 263  * Add \p target_bo to the relocation list.
 264  *
 265  * When \p bo is submitted for execution, and if \p target_bo has moved,
 266  * the kernel will patch \p bo at \p offset to \p target_bo->offset plus
 267  * \p target_offset.
 268  *
 269  * \p presumed_offset should be written to \p bo at \p offset.
 270  */
 271 int
 272 intel_bo_add_reloc(struct intel_bo *bo, uint32_t offset,
 273                    struct intel_bo *target_bo, uint32_t target_offset,
 274                    uint32_t read_domains, uint32_t write_domain,
 275                    uint64_t *presumed_offset);
 276
 277 /**
 278  * Return the current number of relocations.
 279  */
 280 int
 281 intel_bo_get_reloc_count(struct intel_bo *bo);
 282
 283 /**
 284  * Truncate all relocations except the first \p start ones.
 285  *
 286  * Combined with \p intel_bo_get_reloc_count(), they can be used to undo the
 287  * \p intel_bo_add_reloc() calls that were just made.
 288  */
 289 void
 290 intel_bo_truncate_relocs(struct intel_bo *bo, int start);
 291
 292 /**
 293  * Return true if \p target_bo is on the relocation list of \p bo, or on
 294  * the relocation list of some bo that is referenced by \p bo.
 295  */
 296 bool
 297 intel_bo_has_reloc(struct intel_bo *bo, struct intel_bo *target_bo);
 298
 299 /**
 300  * Wait until \bo is idle, or \p timeout nanoseconds have passed.  A
 301  * negative timeout means to wait indefinitely.
 302  *
 303  * \return 0 only when \p bo is idle
 304  */
 305 int
 306 intel_bo_wait(struct intel_bo *bo, int64_t timeout);
 307
 308 /**
 309  * Return true if \p bo is busy.
 310  */
 311 static inline bool
 312 intel_bo_is_busy(struct intel_bo *bo)
 313 {
 314    return (intel_bo_wait(bo, 0) != 0);
 315 }
 316
 317 #endif /* INTEL_WINSYS_H */