src/gallium/winsys/intel/intel_winsys.h

   1 /*
   2  * Mesa 3-D graphics library
   3  *
   4  * Copyright (C) 2012-2014 LunarG, Inc.
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a
   7  * copy of this software and associated documentation files (the "Software"),
   8  * to deal in the Software without restriction, including without limitation
   9  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  10  * and/or sell copies of the Software, and to permit persons to whom the
  11  * Software is furnished to do so, subject to the following conditions:
  12  *
  13  * The above copyright notice and this permission notice shall be included
  14  * in all copies or substantial portions of the Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  19  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  20  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  21  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  22  * DEALINGS IN THE SOFTWARE.
  23  *
  24  * Authors:
  25  *    Chia-I Wu <olv@lunarg.com>
  26  */
  27
  28 #ifndef INTEL_WINSYS_H
  29 #define INTEL_WINSYS_H
  30
  31 #include "pipe/p_compiler.h"
  32
  33 /* this is compatible with i915_drm.h's definitions */
  34 enum intel_ring_type {
  35    INTEL_RING_RENDER    = 1,
  36    INTEL_RING_BSD       = 2,
  37    INTEL_RING_BLT       = 3,
  38    INTEL_RING_VEBOX     = 4,
  39 };
  40
  41 /* this is compatible with i915_drm.h's definitions */
  42 enum intel_exec_flag {
  43    INTEL_EXEC_GEN7_SOL_RESET  = 1 << 8,
  44 };
  45
  46 /* this is compatible with i915_drm.h's definitions */
  47 enum intel_domain_flag {
  48    INTEL_DOMAIN_CPU           = 0x00000001,
  49    INTEL_DOMAIN_RENDER        = 0x00000002,
  50    INTEL_DOMAIN_SAMPLER       = 0x00000004,
  51    INTEL_DOMAIN_COMMAND       = 0x00000008,
  52    INTEL_DOMAIN_INSTRUCTION   = 0x00000010,
  53    INTEL_DOMAIN_VERTEX        = 0x00000020,
  54    INTEL_DOMAIN_GTT           = 0x00000040,
  55 };
  56
  57 /* this is compatible with i915_drm.h's definitions */
  58 enum intel_tiling_mode {
  59    INTEL_TILING_NONE = 0,
  60    INTEL_TILING_X    = 1,
  61    INTEL_TILING_Y    = 2,
  62 };
  63
  64 struct winsys_handle;
  65 struct intel_winsys;
  66 struct intel_context;
  67 struct intel_bo;
  68
  69 struct intel_winsys_info {
  70    int devid;
  71
  72    /* the sizes of the aperture in bytes */
  73    size_t aperture_total;
  74    size_t aperture_mappable;
  75
  76    int max_batch_size;
  77    bool has_llc;
  78    bool has_address_swizzling;
  79    bool has_logical_context;
  80    bool has_ppgtt;
  81
  82    /* valid registers for intel_winsys_read_reg() */
  83    bool has_timestamp;
  84
  85    /* valid flags for intel_winsys_submit_bo() */
  86    bool has_gen7_sol_reset;
  87 };
  88
  89 struct intel_winsys *
  90 intel_winsys_create_for_fd(int fd);
  91
  92 void
  93 intel_winsys_destroy(struct intel_winsys *winsys);
  94
  95 const struct intel_winsys_info *
  96 intel_winsys_get_info(const struct intel_winsys *winsys);
  97
  98 /**
  99  * Create a logical context for use with the render ring.
 100  */
 101 struct intel_context *
 102 intel_winsys_create_context(struct intel_winsys *winsys);
 103
 104 /**
 105  * Destroy a logical context.
 106  */
 107 void
 108 intel_winsys_destroy_context(struct intel_winsys *winsys,
 109                              struct intel_context *ctx);
 110
 111 /**
 112  * Read a register.  Only registers that are considered safe, such as
 113  *
 114  *   TIMESTAMP (0x2358)
 115  *
 116  * can be read.
 117  */
 118 int
 119 intel_winsys_read_reg(struct intel_winsys *winsys,
 120                       uint32_t reg, uint64_t *val);
 121
 122 /**
 123  * Allocate a buffer object.
 124  *
 125  * \param name             Informative description of the bo.
 126  * \param tiling           Tiling mode.
 127  * \param pitch            Pitch of the bo.
 128  * \param height           Height of the bo.
 129  * \param initial_domain   Initial (write) domain.
 130  */
 131 struct intel_bo *
 132 intel_winsys_alloc_bo(struct intel_winsys *winsys,
 133                       const char *name,
 134                       enum intel_tiling_mode tiling,
 135                       unsigned long pitch,
 136                       unsigned long height,
 137                       uint32_t initial_domain);
 138
 139 /**
 140  * Allocate a linear buffer object.
 141  */
 142 static inline struct intel_bo *
 143 intel_winsys_alloc_buffer(struct intel_winsys *winsys,
 144                           const char *name,
 145                           unsigned long size,
 146                           uint32_t initial_domain)
 147 {
 148    return intel_winsys_alloc_bo(winsys, name,
 149          INTEL_TILING_NONE, size, 1, initial_domain);
 150 }
 151
 152 /**
 153  * Create a bo from a winsys handle.
 154  */
 155 struct intel_bo *
 156 intel_winsys_import_handle(struct intel_winsys *winsys,
 157                            const char *name,
 158                            const struct winsys_handle *handle,
 159                            unsigned long height,
 160                            enum intel_tiling_mode *tiling,
 161                            unsigned long *pitch);
 162
 163 /**
 164  * Export \p bo as a winsys handle for inter-process sharing.
 165  */
 166 int
 167 intel_winsys_export_handle(struct intel_winsys *winsys,
 168                            struct intel_bo *bo,
 169                            enum intel_tiling_mode tiling,
 170                            unsigned long pitch,
 171                            unsigned long height,
 172                            struct winsys_handle *handle);
 173
 174 /**
 175  * Return true when buffer objects directly specified in \p bo_array, and
 176  * those indirectly referenced by them, can fit in the aperture space.
 177  */
 178 bool
 179 intel_winsys_can_submit_bo(struct intel_winsys *winsys,
 180                            struct intel_bo **bo_array,
 181                            int count);
 182
 183 /**
 184  * Submit \p bo for execution.
 185  *
 186  * \p bo and all bos referenced by \p bo will be considered busy until all
 187  * commands are parsed and executed.  \p ctx is ignored when the bo is not
 188  * submitted to the render ring.
 189  */
 190 int
 191 intel_winsys_submit_bo(struct intel_winsys *winsys,
 192                        enum intel_ring_type ring,
 193                        struct intel_bo *bo, int used,
 194                        struct intel_context *ctx,
 195                        unsigned long flags);
 196
 197 /**
 198  * Decode the commands contained in \p bo.  For debugging.
 199  *
 200  * \param bo      Batch buffer to decode.
 201  * \param used    Size of the commands in bytes.
 202  */
 203 void
 204 intel_winsys_decode_bo(struct intel_winsys *winsys,
 205                        struct intel_bo *bo, int used);
 206
 207 /**
 208  * Increase the reference count of \p bo.
 209  */
 210 void
 211 intel_bo_reference(struct intel_bo *bo);
 212
 213 /**
 214  * Decrease the reference count of \p bo.  When the reference count reaches
 215  * zero, \p bo is destroyed.
 216  */
 217 void
 218 intel_bo_unreference(struct intel_bo *bo);
 219
 220 /**
 221  * Map \p bo for CPU access.  Recursive mapping is allowed.
 222  *
 223  * map() maps the backing store into CPU address space, cached.  It will block
 224  * if the bo is busy.  This variant allows fastest random reads and writes,
 225  * but the caller needs to handle tiling or swizzling manually if the bo is
 226  * tiled or swizzled.  If write is enabled and there is no shared last-level
 227  * cache (LLC), the CPU cache will be flushed, which is expensive.
 228  *
 229  * map_gtt() maps the bo for MMIO access, uncached but write-combined.  It
 230  * will block if the bo is busy.  This variant promises a reasonable speed for
 231  * sequential writes, but reads would be very slow.  Callers always have a
 232  * linear view of the bo.
 233  *
 234  * map_unsynchronized() is similar to map_gtt(), except that it does not
 235  * block.
 236  */
 237 void *
 238 intel_bo_map(struct intel_bo *bo, bool write_enable);
 239
 240 void *
 241 intel_bo_map_gtt(struct intel_bo *bo);
 242
 243 void *
 244 intel_bo_map_unsynchronized(struct intel_bo *bo);
 245
 246 /**
 247  * Unmap \p bo.
 248  */
 249 void
 250 intel_bo_unmap(struct intel_bo *bo);
 251
 252 /**
 253  * Write data to \p bo.
 254  */
 255 int
 256 intel_bo_pwrite(struct intel_bo *bo, unsigned long offset,
 257                 unsigned long size, const void *data);
 258
 259 /**
 260  * Read data from the bo.
 261  */
 262 int
 263 intel_bo_pread(struct intel_bo *bo, unsigned long offset,
 264                unsigned long size, void *data);
 265
 266 /**
 267  * Add \p target_bo to the relocation list.
 268  *
 269  * When \p bo is submitted for execution, and if \p target_bo has moved,
 270  * the kernel will patch \p bo at \p offset to \p target_bo->offset plus
 271  * \p target_offset.
 272  *
 273  * \p presumed_offset should be written to \p bo at \p offset.
 274  */
 275 int
 276 intel_bo_add_reloc(struct intel_bo *bo, uint32_t offset,
 277                    struct intel_bo *target_bo, uint32_t target_offset,
 278                    uint32_t read_domains, uint32_t write_domain,
 279                    uint64_t *presumed_offset);
 280
 281 /**
 282  * Return the current number of relocations.
 283  */
 284 int
 285 intel_bo_get_reloc_count(struct intel_bo *bo);
 286
 287 /**
 288  * Truncate all relocations except the first \p start ones.
 289  *
 290  * Combined with \p intel_bo_get_reloc_count(), they can be used to undo the
 291  * \p intel_bo_add_reloc() calls that were just made.
 292  */
 293 void
 294 intel_bo_truncate_relocs(struct intel_bo *bo, int start);
 295
 296 /**
 297  * Return true if \p target_bo is on the relocation list of \p bo, or on
 298  * the relocation list of some bo that is referenced by \p bo.
 299  */
 300 bool
 301 intel_bo_has_reloc(struct intel_bo *bo, struct intel_bo *target_bo);
 302
 303 /**
 304  * Wait until \bo is idle, or \p timeout nanoseconds have passed.  A
 305  * negative timeout means to wait indefinitely.
 306  *
 307  * \return 0 only when \p bo is idle
 308  */
 309 int
 310 intel_bo_wait(struct intel_bo *bo, int64_t timeout);
 311
 312 /**
 313  * Return true if \p bo is busy.
 314  */
 315 static inline bool
 316 intel_bo_is_busy(struct intel_bo *bo)
 317 {
 318    return (intel_bo_wait(bo, 0) != 0);
 319 }
 320
 321 #endif /* INTEL_WINSYS_H */