src/gallium/winsys/intel/intel_winsys.h

   1 /*
   2  * Mesa 3-D graphics library
   3  *
   4  * Copyright (C) 2012-2013 LunarG, Inc.
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a
   7  * copy of this software and associated documentation files (the "Software"),
   8  * to deal in the Software without restriction, including without limitation
   9  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  10  * and/or sell copies of the Software, and to permit persons to whom the
  11  * Software is furnished to do so, subject to the following conditions:
  12  *
  13  * The above copyright notice and this permission notice shall be included
  14  * in all copies or substantial portions of the Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  19  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  20  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  21  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  22  * DEALINGS IN THE SOFTWARE.
  23  *
  24  * Authors:
  25  *    Chia-I Wu <olv@lunarg.com>
  26  */
  27
  28 #ifndef INTEL_WINSYS_H
  29 #define INTEL_WINSYS_H
  30
  31 #include "pipe/p_compiler.h"
  32
  33 /* this is compatible with i915_drm.h's definitions */
  34 enum intel_exec_flag {
  35    /* bits[2:0]: ring type */
  36    INTEL_EXEC_DEFAULT         = 0 << 0,
  37    INTEL_EXEC_RENDER          = 1 << 0,
  38    INTEL_EXEC_BSD             = 2 << 0,
  39    INTEL_EXEC_BLT             = 3 << 0,
  40
  41    /* bits[7:6]: constant buffer addressing mode */
  42
  43    /* bits[8]: reset SO write offset register on GEN7+ */
  44    INTEL_EXEC_GEN7_SOL_RESET  = 1 << 8,
  45 };
  46
  47 /* this is compatible with i915_drm.h's definitions */
  48 enum intel_domain_flag {
  49    INTEL_DOMAIN_CPU           = 0x00000001,
  50    INTEL_DOMAIN_RENDER        = 0x00000002,
  51    INTEL_DOMAIN_SAMPLER       = 0x00000004,
  52    INTEL_DOMAIN_COMMAND       = 0x00000008,
  53    INTEL_DOMAIN_INSTRUCTION   = 0x00000010,
  54    INTEL_DOMAIN_VERTEX        = 0x00000020,
  55    INTEL_DOMAIN_GTT           = 0x00000040,
  56 };
  57
  58 /* this is compatible with i915_drm.h's definitions */
  59 enum intel_tiling_mode {
  60    INTEL_TILING_NONE = 0,
  61    INTEL_TILING_X    = 1,
  62    INTEL_TILING_Y    = 2,
  63 };
  64
  65 /* this is compatible with intel_bufmgr.h's definitions */
  66 enum intel_alloc_flag {
  67    INTEL_ALLOC_FOR_RENDER     = 1 << 0,
  68 };
  69
  70 struct winsys_handle;
  71 struct intel_winsys;
  72 struct intel_context;
  73 struct intel_bo;
  74
  75 struct intel_winsys_info {
  76    int devid;
  77    bool has_llc;
  78    bool has_gen7_sol_reset;
  79    bool has_address_swizzling;
  80 };
  81
  82 struct intel_winsys *
  83 intel_winsys_create_for_fd(int fd);
  84
  85 void
  86 intel_winsys_destroy(struct intel_winsys *winsys);
  87
  88 const struct intel_winsys_info *
  89 intel_winsys_get_info(const struct intel_winsys *winsys);
  90
  91 void
  92 intel_winsys_enable_reuse(struct intel_winsys *winsys);
  93
  94 struct intel_context *
  95 intel_winsys_create_context(struct intel_winsys *winsys);
  96
  97 void
  98 intel_winsys_destroy_context(struct intel_winsys *winsys,
  99                              struct intel_context *ctx);
 100
 101 int
 102 intel_winsys_read_reg(struct intel_winsys *winsys,
 103                       uint32_t reg, uint64_t *val);
 104
 105 struct intel_bo *
 106 intel_winsys_alloc_buffer(struct intel_winsys *winsys,
 107                           const char *name,
 108                           unsigned long size,
 109                           unsigned long flags);
 110
 111 struct intel_bo *
 112 intel_winsys_alloc_texture(struct intel_winsys *winsys,
 113                            const char *name,
 114                            int width, int height, int cpp,
 115                            enum intel_tiling_mode tiling,
 116                            unsigned long flags,
 117                            unsigned long *pitch);
 118
 119 struct intel_bo *
 120 intel_winsys_import_handle(struct intel_winsys *winsys,
 121                            const char *name,
 122                            const struct winsys_handle *handle,
 123                            int width, int height, int cpp,
 124                            enum intel_tiling_mode *tiling,
 125                            unsigned long *pitch);
 126
 127 /**
 128  * Export a handle for inter-process sharing.
 129  */
 130 int
 131 intel_winsys_export_handle(struct intel_winsys *winsys,
 132                            struct intel_bo *bo,
 133                            enum intel_tiling_mode tiling,
 134                            unsigned long pitch,
 135                            struct winsys_handle *handle);
 136
 137 int
 138 intel_winsys_check_aperture_space(struct intel_winsys *winsys,
 139                                   struct intel_bo **bo_array,
 140                                   int count);
 141
 142 void
 143 intel_winsys_decode_commands(struct intel_winsys *winsys,
 144                              struct intel_bo *bo, int used);
 145
 146 void
 147 intel_bo_reference(struct intel_bo *bo);
 148
 149 void
 150 intel_bo_unreference(struct intel_bo *bo);
 151
 152 unsigned long
 153 intel_bo_get_size(const struct intel_bo *bo);
 154
 155 unsigned long
 156 intel_bo_get_offset(const struct intel_bo *bo);
 157
 158 void *
 159 intel_bo_get_virtual(const struct intel_bo *bo);
 160
 161 /**
 162  * Map/unmap \p bo for CPU access.
 163  *
 164  * map() maps the backing store into CPU address space, cached.  This
 165  * variant allows for fast random reads and writes.  But the caller needs
 166  * handle tiling or swizzling manually if the bo is tiled or swizzled.  If
 167  * write is enabled and there is no shared last-level cache (LLC), unmap()
 168  * needs to flush the cache, which is rather expensive.
 169  *
 170  * map_gtt() maps the bo for MMIO access, uncached but write-combined.
 171  * This variant promises a reasonable speed for sequential writes, but
 172  * reads would be very slow.  Callers always have a linear view of the bo.
 173  *
 174  * map_unsynchronized() is similar to map_gtt(), except that it does not
 175  * wait until the bo is idle.
 176  */
 177 int
 178 intel_bo_map(struct intel_bo *bo, bool write_enable);
 179
 180 int
 181 intel_bo_map_gtt(struct intel_bo *bo);
 182
 183 int
 184 intel_bo_map_unsynchronized(struct intel_bo *bo);
 185
 186 void
 187 intel_bo_unmap(struct intel_bo *bo);
 188
 189 /**
 190  * Move data in to or out of the bo.
 191  */
 192 int
 193 intel_bo_pwrite(struct intel_bo *bo, unsigned long offset,
 194                 unsigned long size, const void *data);
 195 int
 196 intel_bo_pread(struct intel_bo *bo, unsigned long offset,
 197                unsigned long size, void *data);
 198
 199 /**
 200  * Add \p target_bo to the relocation list.
 201  *
 202  * When \p bo is submitted for execution, and if \p target_bo has moved,
 203  * the kernel will patch \p bo at \p offset to \p target_bo->offset plus
 204  * \p target_offset.
 205  */
 206 int
 207 intel_bo_emit_reloc(struct intel_bo *bo, uint32_t offset,
 208                     struct intel_bo *target_bo, uint32_t target_offset,
 209                     uint32_t read_domains, uint32_t write_domain);
 210
 211 /**
 212  * Return the current number of relocations.
 213  */
 214 int
 215 intel_bo_get_reloc_count(struct intel_bo *bo);
 216
 217 /**
 218  * Discard all relocations except the first \p start ones.
 219  *
 220  * Combined with \p get_reloc_count(), they can be used to undo
 221  * the \p emit_reloc() calls that were just made.
 222  */
 223 void
 224 intel_bo_clear_relocs(struct intel_bo *bo, int start);
 225
 226 /**
 227  * Return true if \p target_bo is on the relocation list of \p bo, or on
 228  * the relocation list of some bo that is referenced by \p bo.
 229  */
 230 bool
 231 intel_bo_references(struct intel_bo *bo, struct intel_bo *target_bo);
 232
 233 /**
 234  * Submit \p bo for execution.
 235  *
 236  * \p bo and all bos referenced by \p bo will be considered busy until all
 237  * commands are parsed and executed.
 238  */
 239 int
 240 intel_bo_exec(struct intel_bo *bo, int used,
 241               struct intel_context *ctx, unsigned long flags);
 242
 243 /**
 244  * Wait until \bo is idle, or \p timeout nanoseconds have passed.  A
 245  * negative timeout means to wait indefinitely.
 246  *
 247  * \return 0 only when \p bo is idle
 248  */
 249 int
 250 intel_bo_wait(struct intel_bo *bo, int64_t timeout);
 251
 252 /**
 253  * Return true if \p bo is busy.
 254  */
 255 static inline bool
 256 intel_bo_is_busy(struct intel_bo *bo)
 257 {
 258    return (intel_bo_wait(bo, 0) != 0);
 259 }
 260
 261 #endif /* INTEL_WINSYS_H */