2 * Mesa 3-D graphics library
4 * Copyright (C) 2012-2014 LunarG, Inc.
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
13 * The above copyright notice and this permission notice shall be included
14 * in all copies or substantial portions of the Software.
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
21 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
22 * DEALINGS IN THE SOFTWARE.
25 * Chia-I Wu <olv@lunarg.com>
28 #ifndef INTEL_WINSYS_H
29 #define INTEL_WINSYS_H
31 #include "pipe/p_compiler.h"
33 /* this is compatible with i915_drm.h's definitions */
34 enum intel_exec_flag
{
35 /* bits[2:0]: ring type */
36 INTEL_EXEC_DEFAULT
= 0 << 0,
37 INTEL_EXEC_RENDER
= 1 << 0,
38 INTEL_EXEC_BSD
= 2 << 0,
39 INTEL_EXEC_BLT
= 3 << 0,
41 /* bits[7:6]: constant buffer addressing mode */
43 /* bits[8]: reset SO write offset register on GEN7+ */
44 INTEL_EXEC_GEN7_SOL_RESET
= 1 << 8,
47 /* this is compatible with i915_drm.h's definitions */
48 enum intel_domain_flag
{
49 INTEL_DOMAIN_CPU
= 0x00000001,
50 INTEL_DOMAIN_RENDER
= 0x00000002,
51 INTEL_DOMAIN_SAMPLER
= 0x00000004,
52 INTEL_DOMAIN_COMMAND
= 0x00000008,
53 INTEL_DOMAIN_INSTRUCTION
= 0x00000010,
54 INTEL_DOMAIN_VERTEX
= 0x00000020,
55 INTEL_DOMAIN_GTT
= 0x00000040,
58 /* this is compatible with i915_drm.h's definitions */
59 enum intel_tiling_mode
{
60 INTEL_TILING_NONE
= 0,
65 /* this is compatible with intel_bufmgr.h's definitions */
66 enum intel_alloc_flag
{
67 INTEL_ALLOC_FOR_RENDER
= 1 << 0,
75 struct intel_winsys_info
{
78 bool has_gen7_sol_reset
;
79 bool has_address_swizzling
;
83 intel_winsys_create_for_fd(int fd
);
86 intel_winsys_destroy(struct intel_winsys
*winsys
);
88 const struct intel_winsys_info
*
89 intel_winsys_get_info(const struct intel_winsys
*winsys
);
92 * Create a logical context for use with the render ring.
94 struct intel_context
*
95 intel_winsys_create_context(struct intel_winsys
*winsys
);
98 * Destroy a logical context.
101 intel_winsys_destroy_context(struct intel_winsys
*winsys
,
102 struct intel_context
*ctx
);
105 * Read a register. Only registers that are considered safe, such as
112 intel_winsys_read_reg(struct intel_winsys
*winsys
,
113 uint32_t reg
, uint64_t *val
);
116 * Allocate a linear buffer object.
118 * \param name Informative description of the bo.
119 * \param size Size of the bo.
120 * \param flags bitmask of enum intel_alloc_flag.
123 intel_winsys_alloc_buffer(struct intel_winsys
*winsys
,
126 unsigned long flags
);
129 * Allocate a 2-dimentional buffer object.
131 * \param name Informative description of the bo.
132 * \param width Width of the bo.
133 * \param height Height of the bo.
134 * \param cpp Bytes per texel.
135 * \param tiling Tiling mode.
136 * \param flags bitmask of enum intel_alloc_flag.
137 * \param pitch Pitch of the bo.
140 intel_winsys_alloc_texture(struct intel_winsys
*winsys
,
142 int width
, int height
, int cpp
,
143 enum intel_tiling_mode tiling
,
145 unsigned long *pitch
);
148 * Create a bo from a winsys handle.
151 intel_winsys_import_handle(struct intel_winsys
*winsys
,
153 const struct winsys_handle
*handle
,
154 int width
, int height
, int cpp
,
155 enum intel_tiling_mode
*tiling
,
156 unsigned long *pitch
);
159 * Export \p bo as a winsys handle for inter-process sharing.
162 intel_winsys_export_handle(struct intel_winsys
*winsys
,
164 enum intel_tiling_mode tiling
,
166 struct winsys_handle
*handle
);
169 * Check that buffer objects directly specified in \p bo_array, and those
170 * indirectly referenced by them, can fit in the aperture space.
173 intel_winsys_check_aperture_space(struct intel_winsys
*winsys
,
174 struct intel_bo
**bo_array
,
178 * Decode the commands contained in \p bo. For debugging.
180 * \param bo Batch buffer to decode.
181 * \param used Size of the commands in bytes.
184 intel_winsys_decode_commands(struct intel_winsys
*winsys
,
185 struct intel_bo
*bo
, int used
);
188 * Increase the reference count of \p bo.
191 intel_bo_reference(struct intel_bo
*bo
);
194 * Decrease the reference count of \p bo. When the reference count reaches
195 * zero, \p bo is destroyed.
198 intel_bo_unreference(struct intel_bo
*bo
);
201 * Map \p bo for CPU access. Recursive mapping is allowed.
203 * map() maps the backing store into CPU address space, cached. It will block
204 * if the bo is busy. This variant allows fastest random reads and writes,
205 * but the caller needs to handle tiling or swizzling manually if the bo is
206 * tiled or swizzled. If write is enabled and there is no shared last-level
207 * cache (LLC), the CPU cache will be flushed, which is expensive.
209 * map_gtt() maps the bo for MMIO access, uncached but write-combined. It
210 * will block if the bo is busy. This variant promises a reasonable speed for
211 * sequential writes, but reads would be very slow. Callers always have a
212 * linear view of the bo.
214 * map_unsynchronized() is similar to map_gtt(), except that it does not
218 intel_bo_map(struct intel_bo
*bo
, bool write_enable
);
221 intel_bo_map_gtt(struct intel_bo
*bo
);
224 intel_bo_map_unsynchronized(struct intel_bo
*bo
);
230 intel_bo_unmap(struct intel_bo
*bo
);
233 * Write data to \p bo.
236 intel_bo_pwrite(struct intel_bo
*bo
, unsigned long offset
,
237 unsigned long size
, const void *data
);
240 * Read data from the bo.
243 intel_bo_pread(struct intel_bo
*bo
, unsigned long offset
,
244 unsigned long size
, void *data
);
247 * Add \p target_bo to the relocation list.
249 * When \p bo is submitted for execution, and if \p target_bo has moved,
250 * the kernel will patch \p bo at \p offset to \p target_bo->offset plus
254 intel_bo_add_reloc(struct intel_bo
*bo
, uint32_t offset
,
255 struct intel_bo
*target_bo
, uint32_t target_offset
,
256 uint32_t read_domains
, uint32_t write_domain
,
257 uint64_t *presumed_offset
);
260 * Return the current number of relocations.
263 intel_bo_get_reloc_count(struct intel_bo
*bo
);
266 * Truncate all relocations except the first \p start ones.
268 * Combined with \p intel_bo_get_reloc_count(), they can be used to undo the
269 * \p intel_bo_add_reloc() calls that were just made.
272 intel_bo_truncate_relocs(struct intel_bo
*bo
, int start
);
275 * Return true if \p target_bo is on the relocation list of \p bo, or on
276 * the relocation list of some bo that is referenced by \p bo.
279 intel_bo_has_reloc(struct intel_bo
*bo
, struct intel_bo
*target_bo
);
282 * Submit \p bo for execution.
284 * \p bo and all bos referenced by \p bo will be considered busy until all
285 * commands are parsed and executed.
288 intel_bo_exec(struct intel_bo
*bo
, int used
,
289 struct intel_context
*ctx
, unsigned long flags
);
292 * Wait until \bo is idle, or \p timeout nanoseconds have passed. A
293 * negative timeout means to wait indefinitely.
295 * \return 0 only when \p bo is idle
298 intel_bo_wait(struct intel_bo
*bo
, int64_t timeout
);
301 * Return true if \p bo is busy.
304 intel_bo_is_busy(struct intel_bo
*bo
)
306 return (intel_bo_wait(bo
, 0) != 0);
309 #endif /* INTEL_WINSYS_H */