2 * Copyright 2010 Jerome Glisse <glisse@freedesktop.org>
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * on the rights to use, copy, modify, merge, publish, distribute, sub
8 * license, and/or sell copies of the Software, and to permit persons to whom
9 * the Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
33 #include "evergreend.h"
34 #include "radeon_drm.h"
36 #include "pipe/p_compiler.h"
37 #include "util/u_inlines.h"
38 #include "util/u_memory.h"
39 #include "r600_priv.h"
41 #define GROUP_FORCE_NEW_BLOCK 0
43 static const struct r600_reg evergreen_config_reg_list
[] = {
44 {R_008958_VGT_PRIMITIVE_TYPE
, 0, 0, 0},
45 {R_008A14_PA_CL_ENHANCE
, 0, 0, 0},
46 {R_008C00_SQ_CONFIG
, 0, 0, 0},
47 {R_008C04_SQ_GPR_RESOURCE_MGMT_1
, 0, 0, 0},
48 {R_008C08_SQ_GPR_RESOURCE_MGMT_2
, 0, 0, 0},
49 {R_008C0C_SQ_THREAD_RESOURCE_MGMT
, 0, 0, 0},
50 {R_008C18_SQ_THREAD_RESOURCE_MGMT_1
, 0, 0, 0},
51 {R_008C1C_SQ_THREAD_RESOURCE_MGMT_2
, 0, 0, 0},
52 {R_008C20_SQ_STACK_RESOURCE_MGMT_1
, 0, 0, 0},
53 {R_008C24_SQ_STACK_RESOURCE_MGMT_2
, 0, 0, 0},
54 {R_008C28_SQ_STACK_RESOURCE_MGMT_3
, 0, 0, 0},
55 {R_008D8C_SQ_DYN_GPR_CNTL_PS_FLUSH_REQ
, 0, 0, 0},
56 {R_009100_SPI_CONFIG_CNTL
, 0, 0, 0},
57 {R_00913C_SPI_CONFIG_CNTL_1
, 0, 0, 0},
60 static const struct r600_reg evergreen_ctl_const_list
[] = {
61 {R_03CFF0_SQ_VTX_BASE_VTX_LOC
, 0, 0, 0},
62 {R_03CFF4_SQ_VTX_START_INST_LOC
, 0, 0, 0},
65 static const struct r600_reg evergreen_context_reg_list
[] = {
66 {R_028000_DB_RENDER_CONTROL
, 0, 0, 0},
67 {R_028004_DB_COUNT_CONTROL
, 0, 0, 0},
68 {R_028008_DB_DEPTH_VIEW
, 0, 0, 0},
69 {R_02800C_DB_RENDER_OVERRIDE
, 0, 0, 0},
70 {R_028010_DB_RENDER_OVERRIDE2
, 0, 0, 0},
71 {GROUP_FORCE_NEW_BLOCK
, 0, 0, 0},
72 {R_028014_DB_HTILE_DATA_BASE
, REG_FLAG_NEED_BO
, 0, 0},
73 {GROUP_FORCE_NEW_BLOCK
, 0, 0, 0},
74 {R_028028_DB_STENCIL_CLEAR
, 0, 0, 0},
75 {R_02802C_DB_DEPTH_CLEAR
, 0, 0, 0},
76 {R_028030_PA_SC_SCREEN_SCISSOR_TL
, 0, 0, 0},
77 {R_028034_PA_SC_SCREEN_SCISSOR_BR
, 0, 0, 0},
78 {GROUP_FORCE_NEW_BLOCK
, 0, 0, 0},
79 {R_028040_DB_Z_INFO
, REG_FLAG_NEED_BO
, 0, 0xFFFFFFFF},
80 {GROUP_FORCE_NEW_BLOCK
, 0, 0, 0},
81 {R_028044_DB_STENCIL_INFO
, 0, 0, 0},
82 {GROUP_FORCE_NEW_BLOCK
, 0, 0, 0},
83 {R_028048_DB_Z_READ_BASE
, REG_FLAG_NEED_BO
, 0, 0},
84 {GROUP_FORCE_NEW_BLOCK
, 0, 0, 0},
85 {R_02804C_DB_STENCIL_READ_BASE
, REG_FLAG_NEED_BO
, 0, 0},
86 {GROUP_FORCE_NEW_BLOCK
, 0, 0, 0},
87 {R_028050_DB_Z_WRITE_BASE
, REG_FLAG_NEED_BO
, 0, 0},
88 {GROUP_FORCE_NEW_BLOCK
, 0, 0, 0},
89 {R_028054_DB_STENCIL_WRITE_BASE
, REG_FLAG_NEED_BO
, 0, 0},
90 {GROUP_FORCE_NEW_BLOCK
, 0, 0, 0},
91 {R_028058_DB_DEPTH_SIZE
, 0, 0, 0},
92 {R_02805C_DB_DEPTH_SLICE
, 0, 0, 0},
93 {R_028140_ALU_CONST_BUFFER_SIZE_PS_0
, REG_FLAG_DIRTY_ALWAYS
, 0, 0},
94 {R_028180_ALU_CONST_BUFFER_SIZE_VS_0
, REG_FLAG_DIRTY_ALWAYS
, 0, 0},
95 {R_028200_PA_SC_WINDOW_OFFSET
, 0, 0, 0},
96 {R_028204_PA_SC_WINDOW_SCISSOR_TL
, 0, 0, 0},
97 {R_028208_PA_SC_WINDOW_SCISSOR_BR
, 0, 0, 0},
98 {R_02820C_PA_SC_CLIPRECT_RULE
, 0, 0, 0},
99 {R_028210_PA_SC_CLIPRECT_0_TL
, 0, 0, 0},
100 {R_028214_PA_SC_CLIPRECT_0_BR
, 0, 0, 0},
101 {R_028218_PA_SC_CLIPRECT_1_TL
, 0, 0, 0},
102 {R_02821C_PA_SC_CLIPRECT_1_BR
, 0, 0, 0},
103 {R_028220_PA_SC_CLIPRECT_2_TL
, 0, 0, 0},
104 {R_028224_PA_SC_CLIPRECT_2_BR
, 0, 0, 0},
105 {R_028228_PA_SC_CLIPRECT_3_TL
, 0, 0, 0},
106 {R_02822C_PA_SC_CLIPRECT_3_BR
, 0, 0, 0},
107 {R_028230_PA_SC_EDGERULE
, 0, 0, 0},
108 {R_028234_PA_SU_HARDWARE_SCREEN_OFFSET
, 0, 0, 0},
109 {R_028238_CB_TARGET_MASK
, 0, 0, 0},
110 {R_02823C_CB_SHADER_MASK
, 0, 0, 0},
111 {R_028240_PA_SC_GENERIC_SCISSOR_TL
, 0, 0, 0},
112 {R_028244_PA_SC_GENERIC_SCISSOR_BR
, 0, 0, 0},
113 {R_028250_PA_SC_VPORT_SCISSOR_0_TL
, 0, 0, 0},
114 {R_028254_PA_SC_VPORT_SCISSOR_0_BR
, 0, 0, 0},
115 {R_028350_SX_MISC
, 0, 0, 0},
116 {R_028380_SQ_VTX_SEMANTIC_0
, 0, 0, 0},
117 {R_028384_SQ_VTX_SEMANTIC_1
, 0, 0, 0},
118 {R_028388_SQ_VTX_SEMANTIC_2
, 0, 0, 0},
119 {R_02838C_SQ_VTX_SEMANTIC_3
, 0, 0, 0},
120 {R_028390_SQ_VTX_SEMANTIC_4
, 0, 0, 0},
121 {R_028394_SQ_VTX_SEMANTIC_5
, 0, 0, 0},
122 {R_028398_SQ_VTX_SEMANTIC_6
, 0, 0, 0},
123 {R_02839C_SQ_VTX_SEMANTIC_7
, 0, 0, 0},
124 {R_0283A0_SQ_VTX_SEMANTIC_8
, 0, 0, 0},
125 {R_0283A4_SQ_VTX_SEMANTIC_9
, 0, 0, 0},
126 {R_0283A8_SQ_VTX_SEMANTIC_10
, 0, 0, 0},
127 {R_0283AC_SQ_VTX_SEMANTIC_11
, 0, 0, 0},
128 {R_0283B0_SQ_VTX_SEMANTIC_12
, 0, 0, 0},
129 {R_0283B4_SQ_VTX_SEMANTIC_13
, 0, 0, 0},
130 {R_0283B8_SQ_VTX_SEMANTIC_14
, 0, 0, 0},
131 {R_0283BC_SQ_VTX_SEMANTIC_15
, 0, 0, 0},
132 {R_0283C0_SQ_VTX_SEMANTIC_16
, 0, 0, 0},
133 {R_0283C4_SQ_VTX_SEMANTIC_17
, 0, 0, 0},
134 {R_0283C8_SQ_VTX_SEMANTIC_18
, 0, 0, 0},
135 {R_0283CC_SQ_VTX_SEMANTIC_19
, 0, 0, 0},
136 {R_0283D0_SQ_VTX_SEMANTIC_20
, 0, 0, 0},
137 {R_0283D4_SQ_VTX_SEMANTIC_21
, 0, 0, 0},
138 {R_0283D8_SQ_VTX_SEMANTIC_22
, 0, 0, 0},
139 {R_0283DC_SQ_VTX_SEMANTIC_23
, 0, 0, 0},
140 {R_0283E0_SQ_VTX_SEMANTIC_24
, 0, 0, 0},
141 {R_0283E4_SQ_VTX_SEMANTIC_25
, 0, 0, 0},
142 {R_0283E8_SQ_VTX_SEMANTIC_26
, 0, 0, 0},
143 {R_0283EC_SQ_VTX_SEMANTIC_27
, 0, 0, 0},
144 {R_0283F0_SQ_VTX_SEMANTIC_28
, 0, 0, 0},
145 {R_0283F4_SQ_VTX_SEMANTIC_29
, 0, 0, 0},
146 {R_0283F8_SQ_VTX_SEMANTIC_30
, 0, 0, 0},
147 {R_0283FC_SQ_VTX_SEMANTIC_31
, 0, 0, 0},
148 {R_0282D0_PA_SC_VPORT_ZMIN_0
, 0, 0, 0},
149 {R_0282D4_PA_SC_VPORT_ZMAX_0
, 0, 0, 0},
150 {R_028400_VGT_MAX_VTX_INDX
, 0, 0, 0},
151 {R_028404_VGT_MIN_VTX_INDX
, 0, 0, 0},
152 {R_028408_VGT_INDX_OFFSET
, 0, 0, 0},
153 {R_02840C_VGT_MULTI_PRIM_IB_RESET_INDX
, 0, 0, 0},
154 {R_028410_SX_ALPHA_TEST_CONTROL
, 0, 0, 0},
155 {R_028414_CB_BLEND_RED
, 0, 0, 0},
156 {R_028418_CB_BLEND_GREEN
, 0, 0, 0},
157 {R_02841C_CB_BLEND_BLUE
, 0, 0, 0},
158 {R_028420_CB_BLEND_ALPHA
, 0, 0, 0},
159 {R_028430_DB_STENCILREFMASK
, 0, 0, 0},
160 {R_028434_DB_STENCILREFMASK_BF
, 0, 0, 0},
161 {R_028438_SX_ALPHA_REF
, 0, 0, 0},
162 {R_02843C_PA_CL_VPORT_XSCALE_0
, 0, 0, 0},
163 {R_028440_PA_CL_VPORT_XOFFSET_0
, 0, 0, 0},
164 {R_028444_PA_CL_VPORT_YSCALE_0
, 0, 0, 0},
165 {R_028448_PA_CL_VPORT_YOFFSET_0
, 0, 0, 0},
166 {R_02844C_PA_CL_VPORT_ZSCALE_0
, 0, 0, 0},
167 {R_028450_PA_CL_VPORT_ZOFFSET_0
, 0, 0, 0},
168 {R_0285BC_PA_CL_UCP0_X
, 0, 0, 0},
169 {R_0285C0_PA_CL_UCP0_Y
, 0, 0, 0},
170 {R_0285C4_PA_CL_UCP0_Z
, 0, 0, 0},
171 {R_0285C8_PA_CL_UCP0_W
, 0, 0, 0},
172 {R_0285CC_PA_CL_UCP1_X
, 0, 0, 0},
173 {R_0285D0_PA_CL_UCP1_Y
, 0, 0, 0},
174 {R_0285D4_PA_CL_UCP1_Z
, 0, 0, 0},
175 {R_0285D8_PA_CL_UCP1_W
, 0, 0, 0},
176 {R_0285DC_PA_CL_UCP2_X
, 0, 0, 0},
177 {R_0285E0_PA_CL_UCP2_Y
, 0, 0, 0},
178 {R_0285E4_PA_CL_UCP2_Z
, 0, 0, 0},
179 {R_0285E8_PA_CL_UCP2_W
, 0, 0, 0},
180 {R_0285EC_PA_CL_UCP3_X
, 0, 0, 0},
181 {R_0285F0_PA_CL_UCP3_Y
, 0, 0, 0},
182 {R_0285F4_PA_CL_UCP3_Z
, 0, 0, 0},
183 {R_0285F8_PA_CL_UCP3_W
, 0, 0, 0},
184 {R_0285FC_PA_CL_UCP4_X
, 0, 0, 0},
185 {R_028600_PA_CL_UCP4_Y
, 0, 0, 0},
186 {R_028604_PA_CL_UCP4_Z
, 0, 0, 0},
187 {R_028608_PA_CL_UCP4_W
, 0, 0, 0},
188 {R_02860C_PA_CL_UCP5_X
, 0, 0, 0},
189 {R_028610_PA_CL_UCP5_Y
, 0, 0, 0},
190 {R_028614_PA_CL_UCP5_Z
, 0, 0, 0},
191 {R_028618_PA_CL_UCP5_W
, 0, 0, 0},
192 {R_02861C_SPI_VS_OUT_ID_0
, 0, 0, 0},
193 {R_028620_SPI_VS_OUT_ID_1
, 0, 0, 0},
194 {R_028624_SPI_VS_OUT_ID_2
, 0, 0, 0},
195 {R_028628_SPI_VS_OUT_ID_3
, 0, 0, 0},
196 {R_02862C_SPI_VS_OUT_ID_4
, 0, 0, 0},
197 {R_028630_SPI_VS_OUT_ID_5
, 0, 0, 0},
198 {R_028634_SPI_VS_OUT_ID_6
, 0, 0, 0},
199 {R_028638_SPI_VS_OUT_ID_7
, 0, 0, 0},
200 {R_02863C_SPI_VS_OUT_ID_8
, 0, 0, 0},
201 {R_028640_SPI_VS_OUT_ID_9
, 0, 0, 0},
202 {R_028644_SPI_PS_INPUT_CNTL_0
, 0, 0, 0},
203 {R_028648_SPI_PS_INPUT_CNTL_1
, 0, 0, 0},
204 {R_02864C_SPI_PS_INPUT_CNTL_2
, 0, 0, 0},
205 {R_028650_SPI_PS_INPUT_CNTL_3
, 0, 0, 0},
206 {R_028654_SPI_PS_INPUT_CNTL_4
, 0, 0, 0},
207 {R_028658_SPI_PS_INPUT_CNTL_5
, 0, 0, 0},
208 {R_02865C_SPI_PS_INPUT_CNTL_6
, 0, 0, 0},
209 {R_028660_SPI_PS_INPUT_CNTL_7
, 0, 0, 0},
210 {R_028664_SPI_PS_INPUT_CNTL_8
, 0, 0, 0},
211 {R_028668_SPI_PS_INPUT_CNTL_9
, 0, 0, 0},
212 {R_02866C_SPI_PS_INPUT_CNTL_10
, 0, 0, 0},
213 {R_028670_SPI_PS_INPUT_CNTL_11
, 0, 0, 0},
214 {R_028674_SPI_PS_INPUT_CNTL_12
, 0, 0, 0},
215 {R_028678_SPI_PS_INPUT_CNTL_13
, 0, 0, 0},
216 {R_02867C_SPI_PS_INPUT_CNTL_14
, 0, 0, 0},
217 {R_028680_SPI_PS_INPUT_CNTL_15
, 0, 0, 0},
218 {R_028684_SPI_PS_INPUT_CNTL_16
, 0, 0, 0},
219 {R_028688_SPI_PS_INPUT_CNTL_17
, 0, 0, 0},
220 {R_02868C_SPI_PS_INPUT_CNTL_18
, 0, 0, 0},
221 {R_028690_SPI_PS_INPUT_CNTL_19
, 0, 0, 0},
222 {R_028694_SPI_PS_INPUT_CNTL_20
, 0, 0, 0},
223 {R_028698_SPI_PS_INPUT_CNTL_21
, 0, 0, 0},
224 {R_02869C_SPI_PS_INPUT_CNTL_22
, 0, 0, 0},
225 {R_0286A0_SPI_PS_INPUT_CNTL_23
, 0, 0, 0},
226 {R_0286A4_SPI_PS_INPUT_CNTL_24
, 0, 0, 0},
227 {R_0286A8_SPI_PS_INPUT_CNTL_25
, 0, 0, 0},
228 {R_0286AC_SPI_PS_INPUT_CNTL_26
, 0, 0, 0},
229 {R_0286B0_SPI_PS_INPUT_CNTL_27
, 0, 0, 0},
230 {R_0286B4_SPI_PS_INPUT_CNTL_28
, 0, 0, 0},
231 {R_0286B8_SPI_PS_INPUT_CNTL_29
, 0, 0, 0},
232 {R_0286BC_SPI_PS_INPUT_CNTL_30
, 0, 0, 0},
233 {R_0286C0_SPI_PS_INPUT_CNTL_31
, 0, 0, 0},
234 {R_0286C4_SPI_VS_OUT_CONFIG
, 0, 0, 0},
235 {R_0286C8_SPI_THREAD_GROUPING
, 0, 0, 0},
236 {R_0286CC_SPI_PS_IN_CONTROL_0
, 0, 0, 0},
237 {R_0286D0_SPI_PS_IN_CONTROL_1
, 0, 0, 0},
238 {R_0286D4_SPI_INTERP_CONTROL_0
, 0, 0, 0},
239 {R_0286D8_SPI_INPUT_Z
, 0, 0, 0},
240 {R_0286DC_SPI_FOG_CNTL
, 0, 0, 0},
241 {R_0286E0_SPI_BARYC_CNTL
, 0, 0, 0},
242 {R_0286E4_SPI_PS_IN_CONTROL_2
, 0, 0, 0},
243 {R_0286E8_SPI_COMPUTE_INPUT_CNTL
, 0, 0, 0},
244 {R_028780_CB_BLEND0_CONTROL
, 0, 0, 0},
245 {R_028784_CB_BLEND1_CONTROL
, 0, 0, 0},
246 {R_028788_CB_BLEND2_CONTROL
, 0, 0, 0},
247 {R_02878C_CB_BLEND3_CONTROL
, 0, 0, 0},
248 {R_028790_CB_BLEND4_CONTROL
, 0, 0, 0},
249 {R_028794_CB_BLEND5_CONTROL
, 0, 0, 0},
250 {R_028798_CB_BLEND6_CONTROL
, 0, 0, 0},
251 {R_02879C_CB_BLEND7_CONTROL
, 0, 0, 0},
252 {R_028800_DB_DEPTH_CONTROL
, 0, 0, 0},
253 {R_02880C_DB_SHADER_CONTROL
, 0, 0, 0},
254 {R_028808_CB_COLOR_CONTROL
, 0, 0, 0},
255 {R_028810_PA_CL_CLIP_CNTL
, 0, 0, 0},
256 {R_028814_PA_SU_SC_MODE_CNTL
, 0, 0, 0},
257 {R_028818_PA_CL_VTE_CNTL
, 0, 0, 0},
258 {R_02881C_PA_CL_VS_OUT_CNTL
, 0, 0, 0},
259 {R_028820_PA_CL_NANINF_CNTL
, 0, 0, 0},
260 {R_028838_SQ_DYN_GPR_RESOURCE_LIMIT_1
, 0, 0, 0},
261 {R_028840_SQ_PGM_START_PS
, REG_FLAG_NEED_BO
, S_0085F0_SH_ACTION_ENA(1), 0xFFFFFFFF},
262 {R_028844_SQ_PGM_RESOURCES_PS
, 0, 0, 0},
263 {R_028848_SQ_PGM_RESOURCES_2_PS
, 0, 0, 0},
264 {R_02884C_SQ_PGM_EXPORTS_PS
, 0, 0, 0},
265 {R_02885C_SQ_PGM_START_VS
, REG_FLAG_NEED_BO
, S_0085F0_SH_ACTION_ENA(1), 0xFFFFFFFF},
266 {R_028860_SQ_PGM_RESOURCES_VS
, 0, 0, 0},
267 {R_028864_SQ_PGM_RESOURCES_2_VS
, 0, 0, 0},
268 {R_0288A4_SQ_PGM_START_FS
, REG_FLAG_NEED_BO
, S_0085F0_SH_ACTION_ENA(1), 0xFFFFFFFF},
269 {R_0288A8_SQ_PGM_RESOURCES_FS
, 0, 0, 0},
270 {R_0288EC_SQ_LDS_ALLOC_PS
, 0, 0, 0},
271 {R_028900_SQ_ESGS_RING_ITEMSIZE
, 0, 0, 0},
272 {R_028904_SQ_GSVS_RING_ITEMSIZE
, 0, 0, 0},
273 {R_028908_SQ_ESTMP_RING_ITEMSIZE
, 0, 0, 0},
274 {R_02890C_SQ_GSTMP_RING_ITEMSIZE
, 0, 0, 0},
275 {R_028910_SQ_VSTMP_RING_ITEMSIZE
, 0, 0, 0},
276 {R_028914_SQ_PSTMP_RING_ITEMSIZE
, 0, 0, 0},
277 {R_02891C_SQ_GS_VERT_ITEMSIZE
, 0, 0, 0},
278 {R_028920_SQ_GS_VERT_ITEMSIZE_1
, 0, 0, 0},
279 {R_028924_SQ_GS_VERT_ITEMSIZE_2
, 0, 0, 0},
280 {R_028928_SQ_GS_VERT_ITEMSIZE_3
, 0, 0, 0},
281 {R_028940_ALU_CONST_CACHE_PS_0
, REG_FLAG_NEED_BO
, S_0085F0_SH_ACTION_ENA(1), 0xFFFFFFFF},
282 {R_028980_ALU_CONST_CACHE_VS_0
, REG_FLAG_NEED_BO
, S_0085F0_SH_ACTION_ENA(1), 0xFFFFFFFF},
283 {R_028A00_PA_SU_POINT_SIZE
, 0, 0, 0},
284 {R_028A04_PA_SU_POINT_MINMAX
, 0, 0, 0},
285 {R_028A08_PA_SU_LINE_CNTL
, 0, 0, 0},
286 {R_028A10_VGT_OUTPUT_PATH_CNTL
, 0, 0, 0},
287 {R_028A14_VGT_HOS_CNTL
, 0, 0, 0},
288 {R_028A18_VGT_HOS_MAX_TESS_LEVEL
, 0, 0, 0},
289 {R_028A1C_VGT_HOS_MIN_TESS_LEVEL
, 0, 0, 0},
290 {R_028A20_VGT_HOS_REUSE_DEPTH
, 0, 0, 0},
291 {R_028A24_VGT_GROUP_PRIM_TYPE
, 0, 0, 0},
292 {R_028A28_VGT_GROUP_FIRST_DECR
, 0, 0, 0},
293 {R_028A2C_VGT_GROUP_DECR
, 0, 0, 0},
294 {R_028A30_VGT_GROUP_VECT_0_CNTL
, 0, 0, 0},
295 {R_028A34_VGT_GROUP_VECT_1_CNTL
, 0, 0, 0},
296 {R_028A38_VGT_GROUP_VECT_0_FMT_CNTL
, 0, 0, 0},
297 {R_028A3C_VGT_GROUP_VECT_1_FMT_CNTL
, 0, 0, 0},
298 {R_028A40_VGT_GS_MODE
, 0, 0, 0},
299 {R_028A48_PA_SC_MODE_CNTL_0
, 0, 0, 0},
300 {R_028A4C_PA_SC_MODE_CNTL_1
, 0, 0, 0},
301 {R_028AB4_VGT_REUSE_OFF
, 0, 0, 0},
302 {R_028AB8_VGT_VTX_CNT_EN
, 0, 0, 0},
303 {R_028ABC_DB_HTILE_SURFACE
, 0, 0, 0},
304 {R_028AC0_DB_SRESULTS_COMPARE_STATE0
, 0, 0, 0},
305 {R_028AC4_DB_SRESULTS_COMPARE_STATE1
, 0, 0, 0},
306 {R_028AC8_DB_PRELOAD_CONTROL
, 0, 0, 0},
307 {R_028B54_VGT_SHADER_STAGES_EN
, 0, 0, 0},
308 {R_028B70_DB_ALPHA_TO_MASK
, 0, 0, 0},
309 {R_028B78_PA_SU_POLY_OFFSET_DB_FMT_CNTL
, 0, 0, 0},
310 {R_028B7C_PA_SU_POLY_OFFSET_CLAMP
, 0, 0, 0},
311 {R_028B80_PA_SU_POLY_OFFSET_FRONT_SCALE
, 0, 0, 0},
312 {R_028B84_PA_SU_POLY_OFFSET_FRONT_OFFSET
, 0, 0, 0},
313 {R_028B88_PA_SU_POLY_OFFSET_BACK_SCALE
, 0, 0, 0},
314 {R_028B8C_PA_SU_POLY_OFFSET_BACK_OFFSET
, 0, 0, 0},
315 {R_028B94_VGT_STRMOUT_CONFIG
, 0, 0, 0},
316 {R_028B98_VGT_STRMOUT_BUFFER_CONFIG
, 0, 0, 0},
317 {R_028C00_PA_SC_LINE_CNTL
, 0, 0, 0},
318 {R_028C04_PA_SC_AA_CONFIG
, 0, 0, 0},
319 {R_028C08_PA_SU_VTX_CNTL
, 0, 0, 0},
320 {R_028C0C_PA_CL_GB_VERT_CLIP_ADJ
, 0, 0, 0},
321 {R_028C10_PA_CL_GB_VERT_DISC_ADJ
, 0, 0, 0},
322 {R_028C14_PA_CL_GB_HORZ_CLIP_ADJ
, 0, 0, 0},
323 {R_028C18_PA_CL_GB_HORZ_DISC_ADJ
, 0, 0, 0},
324 {R_028C1C_PA_SC_AA_SAMPLE_LOCS_MCTX
, 0, 0, 0},
325 {R_028C3C_PA_SC_AA_MASK
, 0, 0, 0},
326 {GROUP_FORCE_NEW_BLOCK
, 0, 0, 0},
327 {R_028C60_CB_COLOR0_BASE
, REG_FLAG_NEED_BO
, 0, 0},
328 {R_028C64_CB_COLOR0_PITCH
, 0, 0, 0},
329 {R_028C68_CB_COLOR0_SLICE
, 0, 0, 0},
330 {R_028C6C_CB_COLOR0_VIEW
, 0, 0, 0},
331 {R_028C70_CB_COLOR0_INFO
, REG_FLAG_NEED_BO
, 0, 0xFFFFFFFF},
332 {R_028C74_CB_COLOR0_ATTRIB
, REG_FLAG_NEED_BO
, 0, 0},
333 {R_028C78_CB_COLOR0_DIM
, 0, 0, 0},
334 {GROUP_FORCE_NEW_BLOCK
, 0, 0, 0},
335 {R_028C9C_CB_COLOR1_BASE
, REG_FLAG_NEED_BO
, 0, 0},
336 {R_028CA0_CB_COLOR1_PITCH
, 0, 0, 0},
337 {R_028CA4_CB_COLOR1_SLICE
, 0, 0, 0},
338 {R_028CA8_CB_COLOR1_VIEW
, 0, 0, 0},
339 {R_028CAC_CB_COLOR1_INFO
, REG_FLAG_NEED_BO
, 0, 0xFFFFFFFF},
340 {R_028CB0_CB_COLOR1_ATTRIB
, REG_FLAG_NEED_BO
, 0, 0},
341 {R_028CB4_CB_COLOR1_DIM
, 0, 0, 0},
342 {GROUP_FORCE_NEW_BLOCK
, 0, 0, 0},
343 {R_028CD8_CB_COLOR2_BASE
, REG_FLAG_NEED_BO
, 0, 0},
344 {R_028CDC_CB_COLOR2_PITCH
, 0, 0, 0},
345 {R_028CE0_CB_COLOR2_SLICE
, 0, 0, 0},
346 {R_028CE4_CB_COLOR2_VIEW
, 0, 0, 0},
347 {R_028CE8_CB_COLOR2_INFO
, REG_FLAG_NEED_BO
, 0, 0xFFFFFFFF},
348 {R_028CEC_CB_COLOR2_ATTRIB
, REG_FLAG_NEED_BO
, 0, 0},
349 {R_028CF0_CB_COLOR2_DIM
, 0, 0, 0},
350 {GROUP_FORCE_NEW_BLOCK
, 0, 0, 0},
351 {R_028D14_CB_COLOR3_BASE
, REG_FLAG_NEED_BO
, 0, 0},
352 {R_028D18_CB_COLOR3_PITCH
, 0, 0, 0},
353 {R_028D1C_CB_COLOR3_SLICE
, 0, 0, 0},
354 {R_028D20_CB_COLOR3_VIEW
, 0, 0, 0},
355 {R_028D24_CB_COLOR3_INFO
, REG_FLAG_NEED_BO
, 0, 0xFFFFFFFF},
356 {R_028D28_CB_COLOR3_ATTRIB
, REG_FLAG_NEED_BO
, 0, 0},
357 {R_028D2C_CB_COLOR3_DIM
, 0, 0, 0},
358 {GROUP_FORCE_NEW_BLOCK
, 0, 0, 0},
359 {R_028D50_CB_COLOR4_BASE
, REG_FLAG_NEED_BO
, 0, 0},
360 {R_028D54_CB_COLOR4_PITCH
, 0, 0, 0},
361 {R_028D58_CB_COLOR4_SLICE
, 0, 0, 0},
362 {R_028D5C_CB_COLOR4_VIEW
, 0, 0, 0},
363 {R_028D60_CB_COLOR4_INFO
, REG_FLAG_NEED_BO
, 0, 0xFFFFFFFF},
364 {R_028D64_CB_COLOR4_ATTRIB
, REG_FLAG_NEED_BO
, 0, 0},
365 {R_028D68_CB_COLOR4_DIM
, 0, 0, 0},
366 {GROUP_FORCE_NEW_BLOCK
, 0, 0, 0},
367 {R_028D8C_CB_COLOR5_BASE
, REG_FLAG_NEED_BO
, 0, 0},
368 {R_028D90_CB_COLOR5_PITCH
, 0, 0, 0},
369 {R_028D94_CB_COLOR5_SLICE
, 0, 0, 0},
370 {R_028D98_CB_COLOR5_VIEW
, 0, 0, 0},
371 {R_028D9C_CB_COLOR5_INFO
, REG_FLAG_NEED_BO
, 0, 0xFFFFFFFF},
372 {R_028DA0_CB_COLOR5_ATTRIB
, REG_FLAG_NEED_BO
, 0, 0},
373 {R_028DA4_CB_COLOR5_DIM
, 0, 0, 0},
374 {GROUP_FORCE_NEW_BLOCK
, 0, 0, 0},
375 {R_028DC8_CB_COLOR6_BASE
, REG_FLAG_NEED_BO
, 0, 0},
376 {R_028DCC_CB_COLOR6_PITCH
, 0, 0, 0},
377 {R_028DD0_CB_COLOR6_SLICE
, 0, 0, 0},
378 {R_028DD4_CB_COLOR6_VIEW
, 0, 0, 0},
379 {R_028DD8_CB_COLOR6_INFO
, REG_FLAG_NEED_BO
, 0, 0xFFFFFFFF},
380 {R_028DDC_CB_COLOR6_ATTRIB
, REG_FLAG_NEED_BO
, 0, 0},
381 {R_028DE0_CB_COLOR6_DIM
, 0, 0, 0},
382 {GROUP_FORCE_NEW_BLOCK
, 0, 0, 0},
383 {R_028E04_CB_COLOR7_BASE
, REG_FLAG_NEED_BO
, 0, 0},
384 {R_028E08_CB_COLOR7_PITCH
, 0, 0, 0},
385 {R_028E0C_CB_COLOR7_SLICE
, 0, 0, 0},
386 {R_028E10_CB_COLOR7_VIEW
, 0, 0, 0},
387 {R_028E14_CB_COLOR7_INFO
, REG_FLAG_NEED_BO
, 0, 0xFFFFFFFF},
388 {R_028E18_CB_COLOR7_ATTRIB
, REG_FLAG_NEED_BO
, 0, 0},
389 {R_028E1C_CB_COLOR7_DIM
, 0, 0, 0},
390 {GROUP_FORCE_NEW_BLOCK
, 0, 0, 0},
391 {R_028E40_CB_COLOR8_BASE
, REG_FLAG_NEED_BO
, 0, 0},
392 {R_028E44_CB_COLOR8_PITCH
, 0, 0, 0},
393 {R_028E48_CB_COLOR8_SLICE
, 0, 0, 0},
394 {R_028E4C_CB_COLOR8_VIEW
, 0, 0, 0},
395 {R_028E50_CB_COLOR8_INFO
, REG_FLAG_NEED_BO
, 0, 0xFFFFFFFF},
396 {R_028E54_CB_COLOR8_ATTRIB
, REG_FLAG_NEED_BO
, 0, 0},
397 {R_028E58_CB_COLOR8_DIM
, 0, 0, 0},
398 {GROUP_FORCE_NEW_BLOCK
, 0, 0, 0},
399 {R_028E5C_CB_COLOR9_BASE
, REG_FLAG_NEED_BO
, 0, 0},
400 {R_028E60_CB_COLOR9_PITCH
, 0, 0, 0},
401 {R_028E64_CB_COLOR9_SLICE
, 0, 0, 0},
402 {R_028E68_CB_COLOR9_VIEW
, 0, 0, 0},
403 {R_028E6C_CB_COLOR9_INFO
, REG_FLAG_NEED_BO
, 0, 0xFFFFFFFF},
404 {R_028E70_CB_COLOR9_ATTRIB
, REG_FLAG_NEED_BO
, 0, 0},
405 {R_028E74_CB_COLOR9_DIM
, 0, 0, 0},
406 {GROUP_FORCE_NEW_BLOCK
, 0, 0, 0},
407 {R_028E78_CB_COLOR10_BASE
, REG_FLAG_NEED_BO
, 0, 0},
408 {R_028E7C_CB_COLOR10_PITCH
, 0, 0, 0},
409 {R_028E80_CB_COLOR10_SLICE
, 0, 0, 0},
410 {R_028E84_CB_COLOR10_VIEW
, 0, 0, 0},
411 {R_028E88_CB_COLOR10_INFO
, REG_FLAG_NEED_BO
, 0, 0xFFFFFFFF},
412 {R_028E8C_CB_COLOR10_ATTRIB
, REG_FLAG_NEED_BO
, 0, 0},
413 {R_028E90_CB_COLOR10_DIM
, 0, 0, 0},
414 {GROUP_FORCE_NEW_BLOCK
, 0, 0, 0},
415 {R_028E94_CB_COLOR11_BASE
, REG_FLAG_NEED_BO
, 0, 0},
416 {R_028E98_CB_COLOR11_PITCH
, 0, 0, 0},
417 {R_028E9C_CB_COLOR11_SLICE
, 0, 0, 0},
418 {R_028EA0_CB_COLOR11_VIEW
, 0, 0, 0},
419 {R_028EA4_CB_COLOR11_INFO
, REG_FLAG_NEED_BO
, 0, 0xFFFFFFFF},
420 {R_028EA8_CB_COLOR11_ATTRIB
, REG_FLAG_NEED_BO
, 0, 0},
421 {R_028EAC_CB_COLOR11_DIM
, 0, 0, 0},
424 /* SHADER RESOURCE R600/R700 */
425 static int evergreen_state_resource_init(struct r600_context
*ctx
, u32 offset
)
427 struct r600_reg r600_shader_resource
[] = {
428 {R_030000_RESOURCE0_WORD0
, 0, 0, 0},
429 {R_030004_RESOURCE0_WORD1
, 0, 0, 0},
430 {R_030008_RESOURCE0_WORD2
, REG_FLAG_NEED_BO
, S_0085F0_TC_ACTION_ENA(1) | S_0085F0_VC_ACTION_ENA(1), 0xFFFFFFFF},
431 {R_03000C_RESOURCE0_WORD3
, REG_FLAG_NEED_BO
, S_0085F0_TC_ACTION_ENA(1) | S_0085F0_VC_ACTION_ENA(1), 0xFFFFFFFF},
432 {R_030010_RESOURCE0_WORD4
, 0, 0, 0},
433 {R_030014_RESOURCE0_WORD5
, 0, 0, 0},
434 {R_030018_RESOURCE0_WORD6
, 0, 0, 0},
435 {R_03001C_RESOURCE0_WORD7
, 0, 0, 0},
437 unsigned nreg
= Elements(r600_shader_resource
);
439 for (int i
= 0; i
< nreg
; i
++) {
440 r600_shader_resource
[i
].offset
+= offset
;
442 return r600_context_add_block(ctx
, r600_shader_resource
, nreg
, PKT3_SET_RESOURCE
, EVERGREEN_RESOURCE_OFFSET
);
445 /* SHADER SAMPLER R600/R700 */
446 static int r600_state_sampler_init(struct r600_context
*ctx
, u32 offset
)
448 struct r600_reg r600_shader_sampler
[] = {
449 {R_03C000_SQ_TEX_SAMPLER_WORD0_0
, 0, 0, 0},
450 {R_03C004_SQ_TEX_SAMPLER_WORD1_0
, 0, 0, 0},
451 {R_03C008_SQ_TEX_SAMPLER_WORD2_0
, 0, 0, 0},
453 unsigned nreg
= Elements(r600_shader_sampler
);
455 for (int i
= 0; i
< nreg
; i
++) {
456 r600_shader_sampler
[i
].offset
+= offset
;
458 return r600_context_add_block(ctx
, r600_shader_sampler
, nreg
, PKT3_SET_SAMPLER
, EVERGREEN_SAMPLER_OFFSET
);
461 /* SHADER SAMPLER BORDER R600/R700 */
462 static int evergreen_state_sampler_border_init(struct r600_context
*ctx
, u32 offset
, unsigned id
)
464 struct r600_reg r600_shader_sampler_border
[] = {
465 {R_00A400_TD_PS_SAMPLER0_BORDER_INDEX
, 0, 0, 0},
466 {R_00A404_TD_PS_SAMPLER0_BORDER_RED
, 0, 0, 0},
467 {R_00A408_TD_PS_SAMPLER0_BORDER_GREEN
, 0, 0, 0},
468 {R_00A40C_TD_PS_SAMPLER0_BORDER_BLUE
, 0, 0, 0},
469 {R_00A410_TD_PS_SAMPLER0_BORDER_ALPHA
, 0, 0, 0},
471 unsigned nreg
= Elements(r600_shader_sampler_border
);
472 unsigned fake_offset
= (offset
- R_00A400_TD_PS_SAMPLER0_BORDER_INDEX
) * 0x100 + 0x40000 + id
* 0x1C;
473 struct r600_range
*range
;
474 struct r600_block
*block
;
477 for (int i
= 0; i
< nreg
; i
++) {
478 r600_shader_sampler_border
[i
].offset
-= R_00A400_TD_PS_SAMPLER0_BORDER_INDEX
;
479 r600_shader_sampler_border
[i
].offset
+= fake_offset
;
481 r
= r600_context_add_block(ctx
, r600_shader_sampler_border
, nreg
, PKT3_SET_CONFIG_REG
, 0);
485 /* set proper offset */
486 range
= &ctx
->range
[CTX_RANGE_ID(ctx
, r600_shader_sampler_border
[0].offset
)];
487 block
= range
->blocks
[CTX_BLOCK_ID(ctx
, r600_shader_sampler_border
[0].offset
)];
488 block
->pm4
[1] = (offset
- EVERGREEN_CONFIG_REG_OFFSET
) >> 2;
492 static int evergreen_loop_const_init(struct r600_context
*ctx
, u32 offset
)
495 struct r600_reg r600_loop_consts
[32];
498 for (i
= 0; i
< nreg
; i
++) {
499 r600_loop_consts
[i
].offset
= EVERGREEN_LOOP_CONST_OFFSET
+ ((offset
+ i
) * 4);
500 r600_loop_consts
[i
].flags
= REG_FLAG_DIRTY_ALWAYS
;
501 r600_loop_consts
[i
].flush_flags
= 0;
502 r600_loop_consts
[i
].flush_mask
= 0;
504 return r600_context_add_block(ctx
, r600_loop_consts
, nreg
, PKT3_SET_LOOP_CONST
, EVERGREEN_LOOP_CONST_OFFSET
);
507 int evergreen_context_init(struct r600_context
*ctx
, struct radeon
*radeon
)
511 memset(ctx
, 0, sizeof(struct r600_context
));
512 ctx
->radeon
= radeon
;
513 LIST_INITHEAD(&ctx
->query_list
);
515 ctx
->range
= calloc(NUM_RANGES
, sizeof(struct r600_range
));
521 /* initialize hash */
522 for (int i
= 0; i
< NUM_RANGES
; i
++) {
523 ctx
->range
[i
].blocks
= calloc(1 << HASH_SHIFT
, sizeof(void*));
524 if (ctx
->range
[i
].blocks
== NULL
) {
531 r
= r600_context_add_block(ctx
, evergreen_config_reg_list
,
532 Elements(evergreen_config_reg_list
), PKT3_SET_CONFIG_REG
, EVERGREEN_CONFIG_REG_OFFSET
);
535 r
= r600_context_add_block(ctx
, evergreen_context_reg_list
,
536 Elements(evergreen_context_reg_list
), PKT3_SET_CONTEXT_REG
, EVERGREEN_CONTEXT_REG_OFFSET
);
539 r
= r600_context_add_block(ctx
, evergreen_ctl_const_list
,
540 Elements(evergreen_ctl_const_list
), PKT3_SET_CTL_CONST
, EVERGREEN_CTL_CONST_OFFSET
);
546 for (int j
= 0, offset
= 0; j
< 18; j
++, offset
+= 0xC) {
547 r
= r600_state_sampler_init(ctx
, offset
);
552 for (int j
= 0, offset
= 0xD8; j
< 18; j
++, offset
+= 0xC) {
553 r
= r600_state_sampler_init(ctx
, offset
);
557 /* PS SAMPLER BORDER */
558 for (int j
= 0; j
< 18; j
++) {
559 r
= evergreen_state_sampler_border_init(ctx
, R_00A400_TD_PS_SAMPLER0_BORDER_INDEX
, j
);
563 /* VS SAMPLER BORDER */
564 for (int j
= 0; j
< 18; j
++) {
565 r
= evergreen_state_sampler_border_init(ctx
, R_00A414_TD_VS_SAMPLER0_BORDER_INDEX
, j
);
570 for (int j
= 0, offset
= 0; j
< 176; j
++, offset
+= 0x20) {
571 r
= evergreen_state_resource_init(ctx
, offset
);
576 for (int j
= 0, offset
= 0x1600; j
< 160; j
++, offset
+= 0x20) {
577 r
= evergreen_state_resource_init(ctx
, offset
);
582 for (int j
= 0, offset
= 0x7C00; j
< 16; j
++, offset
+= 0x20) {
583 r
= evergreen_state_resource_init(ctx
, offset
);
589 evergreen_loop_const_init(ctx
, 0);
591 evergreen_loop_const_init(ctx
, 32);
593 /* setup block table */
594 ctx
->blocks
= calloc(ctx
->nblocks
, sizeof(void*));
595 for (int i
= 0, c
= 0; i
< NUM_RANGES
; i
++) {
596 for (int j
= 0; j
< (1 << HASH_SHIFT
); j
++) {
597 if (ctx
->range
[i
].blocks
[j
]) {
598 assert(c
< ctx
->nblocks
);
599 ctx
->blocks
[c
++] = ctx
->range
[i
].blocks
[j
];
600 j
+= (ctx
->range
[i
].blocks
[j
]->nreg
) - 1;
605 /* allocate cs variables */
606 ctx
->nreloc
= RADEON_CTX_MAX_PM4
;
607 ctx
->reloc
= calloc(ctx
->nreloc
, sizeof(struct r600_reloc
));
608 if (ctx
->reloc
== NULL
) {
612 ctx
->bo
= calloc(ctx
->nreloc
, sizeof(void *));
613 if (ctx
->bo
== NULL
) {
617 ctx
->pm4_ndwords
= RADEON_CTX_MAX_PM4
;
618 ctx
->pm4
= calloc(ctx
->pm4_ndwords
, 4);
619 if (ctx
->pm4
== NULL
) {
623 /* save 16dwords space for fence mecanism */
624 ctx
->pm4_ndwords
-= 16;
628 LIST_INITHEAD(&ctx
->fenced_bo
);
630 /* init dirty list */
631 LIST_INITHEAD(&ctx
->dirty
);
634 r600_context_fini(ctx
);
638 void evergreen_context_pipe_state_set_ps_resource(struct r600_context
*ctx
, struct r600_pipe_state
*state
, unsigned rid
)
640 unsigned offset
= R_030000_SQ_TEX_RESOURCE_WORD0_0
+ 0x20 * rid
;
642 r600_context_pipe_state_set_resource(ctx
, state
, offset
);
645 void evergreen_context_pipe_state_set_vs_resource(struct r600_context
*ctx
, struct r600_pipe_state
*state
, unsigned rid
)
647 unsigned offset
= R_030000_SQ_TEX_RESOURCE_WORD0_0
+ 0x1600 + 0x20 * rid
;
649 r600_context_pipe_state_set_resource(ctx
, state
, offset
);
652 void evergreen_context_pipe_state_set_fs_resource(struct r600_context
*ctx
, struct r600_pipe_state
*state
, unsigned rid
)
654 unsigned offset
= R_030000_SQ_TEX_RESOURCE_WORD0_0
+ 0x7C00 + 0x20 * rid
;
656 r600_context_pipe_state_set_resource(ctx
, state
, offset
);
659 static inline void evergreen_context_pipe_state_set_sampler(struct r600_context
*ctx
, struct r600_pipe_state
*state
, unsigned offset
)
661 struct r600_range
*range
;
662 struct r600_block
*block
;
666 range
= &ctx
->range
[CTX_RANGE_ID(ctx
, offset
)];
667 block
= range
->blocks
[CTX_BLOCK_ID(ctx
, offset
)];
669 block
->status
&= ~(R600_BLOCK_STATUS_ENABLED
| R600_BLOCK_STATUS_DIRTY
);
670 LIST_DELINIT(&block
->list
);
673 dirty
= block
->status
& R600_BLOCK_STATUS_DIRTY
;
675 for (i
= 0; i
< 3; i
++) {
676 if (block
->reg
[i
] != state
->regs
[i
].value
) {
677 dirty
|= R600_BLOCK_STATUS_DIRTY
;
678 block
->reg
[i
] = state
->regs
[i
].value
;
682 r600_context_dirty_block(ctx
, block
, dirty
, 2);
685 static inline void evergreen_context_ps_partial_flush(struct r600_context
*ctx
)
687 if (!(ctx
->flags
& R600_CONTEXT_DRAW_PENDING
))
690 ctx
->pm4
[ctx
->pm4_cdwords
++] = PKT3(PKT3_EVENT_WRITE
, 0, 0);
691 ctx
->pm4
[ctx
->pm4_cdwords
++] = EVENT_TYPE(EVENT_TYPE_PS_PARTIAL_FLUSH
) | EVENT_INDEX(4);
693 ctx
->flags
&= ~R600_CONTEXT_DRAW_PENDING
;
696 static inline void evergreen_context_pipe_state_set_sampler_border(struct r600_context
*ctx
, struct r600_pipe_state
*state
, unsigned offset
, unsigned id
)
698 unsigned fake_offset
= (offset
- R_00A400_TD_PS_SAMPLER0_BORDER_INDEX
) * 0x100 + 0x40000 + id
* 0x1C;
699 struct r600_range
*range
;
700 struct r600_block
*block
;
704 range
= &ctx
->range
[CTX_RANGE_ID(ctx
, fake_offset
)];
705 block
= range
->blocks
[CTX_BLOCK_ID(ctx
, fake_offset
)];
707 block
->status
&= ~(R600_BLOCK_STATUS_ENABLED
| R600_BLOCK_STATUS_DIRTY
);
708 LIST_DELINIT(&block
->list
);
711 if (state
->nregs
<= 3) {
715 dirty
= block
->status
& R600_BLOCK_STATUS_DIRTY
;
716 if (block
->reg
[0] != id
) {
718 dirty
|= R600_BLOCK_STATUS_DIRTY
;
721 for (i
= 1; i
< 5; i
++) {
722 if (block
->reg
[i
] != state
->regs
[i
+ 2].value
) {
723 block
->reg
[i
] = state
->regs
[i
+ 2].value
;
724 dirty
|= R600_BLOCK_STATUS_DIRTY
;
728 /* We have to flush the shaders before we change the border color
729 * registers, or previous draw commands that haven't completed yet
730 * will end up using the new border color. */
731 if (dirty
& R600_BLOCK_STATUS_DIRTY
)
732 evergreen_context_ps_partial_flush(ctx
);
734 r600_context_dirty_block(ctx
, block
, dirty
, 4);
737 void evergreen_context_pipe_state_set_ps_sampler(struct r600_context
*ctx
, struct r600_pipe_state
*state
, unsigned id
)
741 offset
= 0x0003C000 + id
* 0xc;
742 evergreen_context_pipe_state_set_sampler(ctx
, state
, offset
);
743 evergreen_context_pipe_state_set_sampler_border(ctx
, state
, R_00A400_TD_PS_SAMPLER0_BORDER_INDEX
, id
);
746 void evergreen_context_pipe_state_set_vs_sampler(struct r600_context
*ctx
, struct r600_pipe_state
*state
, unsigned id
)
750 offset
= 0x0003C0D8 + id
* 0xc;
751 evergreen_context_pipe_state_set_sampler(ctx
, state
, offset
);
752 evergreen_context_pipe_state_set_sampler_border(ctx
, state
, R_00A414_TD_VS_SAMPLER0_BORDER_INDEX
, id
);
756 void evergreen_context_draw(struct r600_context
*ctx
, const struct r600_draw
*draw
)
758 unsigned ndwords
= 7;
759 struct r600_block
*dirty_block
= NULL
;
760 struct r600_block
*next_block
;
764 /* make sure there is enough relocation space before scheduling draw */
765 if (ctx
->creloc
>= (ctx
->nreloc
- 1)) {
766 r600_context_flush(ctx
);
770 /* queries need some special values */
771 if (ctx
->num_query_running
) {
772 r600_context_reg(ctx
,
773 R_028004_DB_COUNT_CONTROL
,
774 S_028004_PERFECT_ZPASS_COUNTS(1),
775 S_028004_PERFECT_ZPASS_COUNTS(1));
776 r600_context_reg(ctx
,
777 R_02800C_DB_RENDER_OVERRIDE
,
778 S_02800C_NOOP_CULL_DISABLE(1),
779 S_02800C_NOOP_CULL_DISABLE(1));
782 /* update the max dword count to make sure we have enough space
783 * reserved for flushing the destination caches */
784 ctx
->pm4_ndwords
= RADEON_CTX_MAX_PM4
- ctx
->num_dest_buffers
* 7 - 16;
786 if ((ctx
->pm4_dirty_cdwords
+ ndwords
+ ctx
->pm4_cdwords
) > ctx
->pm4_ndwords
) {
788 r600_context_flush(ctx
);
790 /* at that point everythings is flushed and ctx->pm4_cdwords = 0 */
791 if ((ctx
->pm4_dirty_cdwords
+ ndwords
) > ctx
->pm4_ndwords
) {
792 R600_ERR("context is too big to be scheduled\n");
796 /* enough room to copy packet */
797 LIST_FOR_EACH_ENTRY_SAFE(dirty_block
, next_block
, &ctx
->dirty
,list
) {
798 r600_context_block_emit_dirty(ctx
, dirty_block
);
802 ctx
->pm4
[ctx
->pm4_cdwords
++] = PKT3(PKT3_INDEX_TYPE
, 0, ctx
->predicate_drawing
);
803 ctx
->pm4
[ctx
->pm4_cdwords
++] = draw
->vgt_index_type
;
804 ctx
->pm4
[ctx
->pm4_cdwords
++] = PKT3(PKT3_NUM_INSTANCES
, 0, ctx
->predicate_drawing
);
805 ctx
->pm4
[ctx
->pm4_cdwords
++] = draw
->vgt_num_instances
;
807 ctx
->pm4
[ctx
->pm4_cdwords
++] = PKT3(PKT3_DRAW_INDEX
, 3, ctx
->predicate_drawing
);
808 ctx
->pm4
[ctx
->pm4_cdwords
++] = draw
->indices_bo_offset
+ r600_bo_offset(draw
->indices
);
809 ctx
->pm4
[ctx
->pm4_cdwords
++] = 0;
810 ctx
->pm4
[ctx
->pm4_cdwords
++] = draw
->vgt_num_indices
;
811 ctx
->pm4
[ctx
->pm4_cdwords
++] = draw
->vgt_draw_initiator
;
812 ctx
->pm4
[ctx
->pm4_cdwords
++] = PKT3(PKT3_NOP
, 0, ctx
->predicate_drawing
);
813 ctx
->pm4
[ctx
->pm4_cdwords
++] = 0;
814 r600_context_bo_reloc(ctx
, &ctx
->pm4
[ctx
->pm4_cdwords
- 1], draw
->indices
);
816 ctx
->pm4
[ctx
->pm4_cdwords
++] = PKT3(PKT3_DRAW_INDEX_AUTO
, 1, ctx
->predicate_drawing
);
817 ctx
->pm4
[ctx
->pm4_cdwords
++] = draw
->vgt_num_indices
;
818 ctx
->pm4
[ctx
->pm4_cdwords
++] = draw
->vgt_draw_initiator
;
821 ctx
->flags
|= (R600_CONTEXT_DRAW_PENDING
| R600_CONTEXT_DST_CACHES_DIRTY
);
823 /* all dirty state have been scheduled in current cs */
824 ctx
->pm4_dirty_cdwords
= 0;
827 void evergreen_context_flush_dest_caches(struct r600_context
*ctx
)
829 struct r600_bo
*cb
[12];
832 if (!(ctx
->flags
& R600_CONTEXT_DST_CACHES_DIRTY
))
835 /* find number of color buffer */
836 db
= r600_context_reg_bo(ctx
, R_028048_DB_Z_READ_BASE
);
837 cb
[0] = r600_context_reg_bo(ctx
, R_028C60_CB_COLOR0_BASE
);
838 cb
[1] = r600_context_reg_bo(ctx
, R_028C9C_CB_COLOR1_BASE
);
839 cb
[2] = r600_context_reg_bo(ctx
, R_028CD8_CB_COLOR2_BASE
);
840 cb
[3] = r600_context_reg_bo(ctx
, R_028D14_CB_COLOR3_BASE
);
841 cb
[4] = r600_context_reg_bo(ctx
, R_028D50_CB_COLOR4_BASE
);
842 cb
[5] = r600_context_reg_bo(ctx
, R_028D8C_CB_COLOR5_BASE
);
843 cb
[6] = r600_context_reg_bo(ctx
, R_028DC8_CB_COLOR6_BASE
);
844 cb
[7] = r600_context_reg_bo(ctx
, R_028E04_CB_COLOR7_BASE
);
845 cb
[8] = r600_context_reg_bo(ctx
, R_028E40_CB_COLOR8_BASE
);
846 cb
[9] = r600_context_reg_bo(ctx
, R_028E5C_CB_COLOR9_BASE
);
847 cb
[10] = r600_context_reg_bo(ctx
, R_028E78_CB_COLOR10_BASE
);
848 cb
[11] = r600_context_reg_bo(ctx
, R_028E94_CB_COLOR11_BASE
);
850 /* flush color buffer */
851 for (int i
= 0; i
< 12; i
++) {
856 flush
= (S_0085F0_CB8_DEST_BASE_ENA(1) << (i
- 8)) |
857 S_0085F0_CB_ACTION_ENA(1);
859 flush
= (S_0085F0_CB0_DEST_BASE_ENA(1) << i
) |
860 S_0085F0_CB_ACTION_ENA(1);
862 r600_context_bo_flush(ctx
, flush
, 0, cb
[i
]);
866 r600_context_bo_flush(ctx
,
867 S_0085F0_DB_ACTION_ENA(1) |
868 S_0085F0_DB_DEST_BASE_ENA(1),
872 ctx
->flags
&= ~R600_CONTEXT_DST_CACHES_DIRTY
;