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r600g: fix evergreen new path
[mesa.git] / src / gallium / winsys / r600 / drm / evergreen_state.c
1 /*
2 * Copyright 2010 Jerome Glisse <glisse@freedesktop.org>
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * on the rights to use, copy, modify, merge, publish, distribute, sub
8 * license, and/or sell copies of the Software, and to permit persons to whom
9 * the Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
22 *
23 * Authors:
24 * Jerome Glisse
25 */
26 #include <errno.h>
27 #include <stdint.h>
28 #include <string.h>
29 #include <stdlib.h>
30 #include <assert.h>
31 #include "xf86drm.h"
32 #include "r600.h"
33 #include "evergreend.h"
34 #include "r600_priv.h"
35 #include "radeon_drm.h"
36 #include "bof.h"
37 #include "pipe/p_compiler.h"
38 #include "util/u_inlines.h"
39 #include <pipebuffer/pb_bufmgr.h>
40
41 struct radeon_bo {
42 struct pipe_reference reference;
43 unsigned handle;
44 unsigned size;
45 unsigned alignment;
46 unsigned map_count;
47 void *data;
48 };
49 struct radeon_ws_bo {
50 struct pipe_reference reference;
51 struct pb_buffer *pb;
52 };
53 struct radeon_bo *radeon_bo_pb_get_bo(struct pb_buffer *_buf);
54
55 struct radeon_bo *r600_context_reg_bo(struct r600_context *ctx, unsigned group_id, unsigned offset);
56 void r600_context_group_emit_dirty(struct r600_context *ctx, struct r600_group *group, unsigned opcode);
57 void r600_context_bo_reloc(struct r600_context *ctx, u32 *pm4, struct radeon_bo *bo);
58 int r600_context_add_block(struct r600_context *ctx, const struct r600_reg *reg, unsigned nreg);
59 int r600_group_init(struct r600_group *group, unsigned start_offset, unsigned end_offset);
60
61 #define GROUP_FORCE_NEW_BLOCK 0
62 static const struct r600_reg evergreen_reg_list[] = {
63 {0, 0, R_008958_VGT_PRIMITIVE_TYPE},
64 {0, 0, R_008A14_PA_CL_ENHANCE},
65 {0, 0, R_008C00_SQ_CONFIG},
66 {0, 0, R_008C04_SQ_GPR_RESOURCE_MGMT_1},
67 {0, 0, R_008C08_SQ_GPR_RESOURCE_MGMT_2},
68 {0, 0, R_008C0C_SQ_THREAD_RESOURCE_MGMT},
69 {0, 0, R_008C18_SQ_THREAD_RESOURCE_MGMT_1},
70 {0, 0, R_008C1C_SQ_THREAD_RESOURCE_MGMT_2},
71 {0, 0, R_008C20_SQ_STACK_RESOURCE_MGMT_1},
72 {0, 0, R_008C24_SQ_STACK_RESOURCE_MGMT_2},
73 {0, 0, R_008C28_SQ_STACK_RESOURCE_MGMT_3},
74 {0, 0, R_008D8C_SQ_DYN_GPR_CNTL_PS_FLUSH_REQ},
75 {0, 0, R_009100_SPI_CONFIG_CNTL},
76 {0, 0, R_00913C_SPI_CONFIG_CNTL_1},
77 {0, 0, R_028000_DB_RENDER_CONTROL},
78 {0, 0, R_028008_DB_DEPTH_VIEW},
79 {0, 0, R_02800C_DB_RENDER_OVERRIDE},
80 {0, 0, R_028010_DB_RENDER_OVERRIDE2},
81 {0, 0, GROUP_FORCE_NEW_BLOCK},
82 {1, 0, R_028014_DB_HTILE_DATA_BASE},
83 {0, 0, GROUP_FORCE_NEW_BLOCK},
84 {0, 0, R_028028_DB_STENCIL_CLEAR},
85 {0, 0, R_02802C_DB_DEPTH_CLEAR},
86 {0, 0, R_028030_PA_SC_SCREEN_SCISSOR_TL},
87 {0, 0, R_028034_PA_SC_SCREEN_SCISSOR_BR},
88 {1, 0, R_028040_DB_Z_INFO},
89 {0, 0, R_028044_DB_STENCIL_INFO},
90 {1, 0, R_028048_DB_Z_READ_BASE},
91 {1, 0, R_02804C_DB_STENCIL_READ_BASE},
92 {1, 0, R_028050_DB_Z_WRITE_BASE},
93 {1, 0, R_028054_DB_STENCIL_WRITE_BASE},
94 {0, 0, R_028058_DB_DEPTH_SIZE},
95 {0, 0, R_02805C_DB_DEPTH_SLICE},
96 {0, 0, R_028140_ALU_CONST_BUFFER_SIZE_PS_0},
97 {0, 0, R_028180_ALU_CONST_BUFFER_SIZE_VS_0},
98 {0, 0, R_028200_PA_SC_WINDOW_OFFSET},
99 {0, 0, R_028204_PA_SC_WINDOW_SCISSOR_TL},
100 {0, 0, R_028208_PA_SC_WINDOW_SCISSOR_BR},
101 {0, 0, R_02820C_PA_SC_CLIPRECT_RULE},
102 {0, 0, R_028210_PA_SC_CLIPRECT_0_TL},
103 {0, 0, R_028214_PA_SC_CLIPRECT_0_BR},
104 {0, 0, R_028218_PA_SC_CLIPRECT_1_TL},
105 {0, 0, R_02821C_PA_SC_CLIPRECT_1_BR},
106 {0, 0, R_028220_PA_SC_CLIPRECT_2_TL},
107 {0, 0, R_028224_PA_SC_CLIPRECT_2_BR},
108 {0, 0, R_028228_PA_SC_CLIPRECT_3_TL},
109 {0, 0, R_02822C_PA_SC_CLIPRECT_3_BR},
110 {0, 0, R_028230_PA_SC_EDGERULE},
111 {0, 0, R_028234_PA_SU_HARDWARE_SCREEN_OFFSET},
112 {0, 0, R_028238_CB_TARGET_MASK},
113 {0, 0, R_02823C_CB_SHADER_MASK},
114 {0, 0, R_028240_PA_SC_GENERIC_SCISSOR_TL},
115 {0, 0, R_028244_PA_SC_GENERIC_SCISSOR_BR},
116 {0, 0, R_028250_PA_SC_VPORT_SCISSOR_0_TL},
117 {0, 0, R_028254_PA_SC_VPORT_SCISSOR_0_BR},
118 {0, 0, R_028350_SX_MISC},
119 {0, 0, R_028380_SQ_VTX_SEMANTIC_0},
120 {0, 0, R_028384_SQ_VTX_SEMANTIC_1},
121 {0, 0, R_028388_SQ_VTX_SEMANTIC_2},
122 {0, 0, R_02838C_SQ_VTX_SEMANTIC_3},
123 {0, 0, R_028390_SQ_VTX_SEMANTIC_4},
124 {0, 0, R_028394_SQ_VTX_SEMANTIC_5},
125 {0, 0, R_028398_SQ_VTX_SEMANTIC_6},
126 {0, 0, R_02839C_SQ_VTX_SEMANTIC_7},
127 {0, 0, R_0283A0_SQ_VTX_SEMANTIC_8},
128 {0, 0, R_0283A4_SQ_VTX_SEMANTIC_9},
129 {0, 0, R_0283A8_SQ_VTX_SEMANTIC_10},
130 {0, 0, R_0283AC_SQ_VTX_SEMANTIC_11},
131 {0, 0, R_0283B0_SQ_VTX_SEMANTIC_12},
132 {0, 0, R_0283B4_SQ_VTX_SEMANTIC_13},
133 {0, 0, R_0283B8_SQ_VTX_SEMANTIC_14},
134 {0, 0, R_0283BC_SQ_VTX_SEMANTIC_15},
135 {0, 0, R_0283C0_SQ_VTX_SEMANTIC_16},
136 {0, 0, R_0283C4_SQ_VTX_SEMANTIC_17},
137 {0, 0, R_0283C8_SQ_VTX_SEMANTIC_18},
138 {0, 0, R_0283CC_SQ_VTX_SEMANTIC_19},
139 {0, 0, R_0283D0_SQ_VTX_SEMANTIC_20},
140 {0, 0, R_0283D4_SQ_VTX_SEMANTIC_21},
141 {0, 0, R_0283D8_SQ_VTX_SEMANTIC_22},
142 {0, 0, R_0283DC_SQ_VTX_SEMANTIC_23},
143 {0, 0, R_0283E0_SQ_VTX_SEMANTIC_24},
144 {0, 0, R_0283E4_SQ_VTX_SEMANTIC_25},
145 {0, 0, R_0283E8_SQ_VTX_SEMANTIC_26},
146 {0, 0, R_0283EC_SQ_VTX_SEMANTIC_27},
147 {0, 0, R_0283F0_SQ_VTX_SEMANTIC_28},
148 {0, 0, R_0283F4_SQ_VTX_SEMANTIC_29},
149 {0, 0, R_0283F8_SQ_VTX_SEMANTIC_30},
150 {0, 0, R_0283FC_SQ_VTX_SEMANTIC_31},
151 {0, 0, R_0282D0_PA_SC_VPORT_ZMIN_0},
152 {0, 0, R_0282D4_PA_SC_VPORT_ZMAX_0},
153 {0, 0, R_028400_VGT_MAX_VTX_INDX},
154 {0, 0, R_028404_VGT_MIN_VTX_INDX},
155 {0, 0, R_028408_VGT_INDX_OFFSET},
156 {0, 0, R_02840C_VGT_MULTI_PRIM_IB_RESET_INDX},
157 {0, 0, R_028410_SX_ALPHA_TEST_CONTROL},
158 {0, 0, R_028414_CB_BLEND_RED},
159 {0, 0, R_028418_CB_BLEND_GREEN},
160 {0, 0, R_02841C_CB_BLEND_BLUE},
161 {0, 0, R_028420_CB_BLEND_ALPHA},
162 {0, 0, R_028430_DB_STENCILREFMASK},
163 {0, 0, R_028434_DB_STENCILREFMASK_BF},
164 {0, 0, R_028438_SX_ALPHA_REF},
165 {0, 0, R_02843C_PA_CL_VPORT_XSCALE_0},
166 {0, 0, R_028440_PA_CL_VPORT_XOFFSET_0},
167 {0, 0, R_028444_PA_CL_VPORT_YSCALE_0},
168 {0, 0, R_028448_PA_CL_VPORT_YOFFSET_0},
169 {0, 0, R_02844C_PA_CL_VPORT_ZSCALE_0},
170 {0, 0, R_028450_PA_CL_VPORT_ZOFFSET_0},
171 {0, 0, R_0285BC_PA_CL_UCP0_X},
172 {0, 0, R_0285C0_PA_CL_UCP0_Y},
173 {0, 0, R_0285C4_PA_CL_UCP0_Z},
174 {0, 0, R_0285C8_PA_CL_UCP0_W},
175 {0, 0, R_0285CC_PA_CL_UCP1_X},
176 {0, 0, R_0285D0_PA_CL_UCP1_Y},
177 {0, 0, R_0285D4_PA_CL_UCP1_Z},
178 {0, 0, R_0285D8_PA_CL_UCP1_W},
179 {0, 0, R_0285DC_PA_CL_UCP2_X},
180 {0, 0, R_0285E0_PA_CL_UCP2_Y},
181 {0, 0, R_0285E4_PA_CL_UCP2_Z},
182 {0, 0, R_0285E8_PA_CL_UCP2_W},
183 {0, 0, R_0285EC_PA_CL_UCP3_X},
184 {0, 0, R_0285F0_PA_CL_UCP3_Y},
185 {0, 0, R_0285F4_PA_CL_UCP3_Z},
186 {0, 0, R_0285F8_PA_CL_UCP3_W},
187 {0, 0, R_0285FC_PA_CL_UCP4_X},
188 {0, 0, R_028600_PA_CL_UCP4_Y},
189 {0, 0, R_028604_PA_CL_UCP4_Z},
190 {0, 0, R_028608_PA_CL_UCP4_W},
191 {0, 0, R_02860C_PA_CL_UCP5_X},
192 {0, 0, R_028610_PA_CL_UCP5_Y},
193 {0, 0, R_028614_PA_CL_UCP5_Z},
194 {0, 0, R_028618_PA_CL_UCP5_W},
195 {0, 0, R_02861C_SPI_VS_OUT_ID_0},
196 {0, 0, R_028620_SPI_VS_OUT_ID_1},
197 {0, 0, R_028624_SPI_VS_OUT_ID_2},
198 {0, 0, R_028628_SPI_VS_OUT_ID_3},
199 {0, 0, R_02862C_SPI_VS_OUT_ID_4},
200 {0, 0, R_028630_SPI_VS_OUT_ID_5},
201 {0, 0, R_028634_SPI_VS_OUT_ID_6},
202 {0, 0, R_028638_SPI_VS_OUT_ID_7},
203 {0, 0, R_02863C_SPI_VS_OUT_ID_8},
204 {0, 0, R_028640_SPI_VS_OUT_ID_9},
205 {0, 0, R_028644_SPI_PS_INPUT_CNTL_0},
206 {0, 0, R_028648_SPI_PS_INPUT_CNTL_1},
207 {0, 0, R_02864C_SPI_PS_INPUT_CNTL_2},
208 {0, 0, R_028650_SPI_PS_INPUT_CNTL_3},
209 {0, 0, R_028654_SPI_PS_INPUT_CNTL_4},
210 {0, 0, R_028658_SPI_PS_INPUT_CNTL_5},
211 {0, 0, R_02865C_SPI_PS_INPUT_CNTL_6},
212 {0, 0, R_028660_SPI_PS_INPUT_CNTL_7},
213 {0, 0, R_028664_SPI_PS_INPUT_CNTL_8},
214 {0, 0, R_028668_SPI_PS_INPUT_CNTL_9},
215 {0, 0, R_02866C_SPI_PS_INPUT_CNTL_10},
216 {0, 0, R_028670_SPI_PS_INPUT_CNTL_11},
217 {0, 0, R_028674_SPI_PS_INPUT_CNTL_12},
218 {0, 0, R_028678_SPI_PS_INPUT_CNTL_13},
219 {0, 0, R_02867C_SPI_PS_INPUT_CNTL_14},
220 {0, 0, R_028680_SPI_PS_INPUT_CNTL_15},
221 {0, 0, R_028684_SPI_PS_INPUT_CNTL_16},
222 {0, 0, R_028688_SPI_PS_INPUT_CNTL_17},
223 {0, 0, R_02868C_SPI_PS_INPUT_CNTL_18},
224 {0, 0, R_028690_SPI_PS_INPUT_CNTL_19},
225 {0, 0, R_028694_SPI_PS_INPUT_CNTL_20},
226 {0, 0, R_028698_SPI_PS_INPUT_CNTL_21},
227 {0, 0, R_02869C_SPI_PS_INPUT_CNTL_22},
228 {0, 0, R_0286A0_SPI_PS_INPUT_CNTL_23},
229 {0, 0, R_0286A4_SPI_PS_INPUT_CNTL_24},
230 {0, 0, R_0286A8_SPI_PS_INPUT_CNTL_25},
231 {0, 0, R_0286AC_SPI_PS_INPUT_CNTL_26},
232 {0, 0, R_0286B0_SPI_PS_INPUT_CNTL_27},
233 {0, 0, R_0286B4_SPI_PS_INPUT_CNTL_28},
234 {0, 0, R_0286B8_SPI_PS_INPUT_CNTL_29},
235 {0, 0, R_0286BC_SPI_PS_INPUT_CNTL_30},
236 {0, 0, R_0286C0_SPI_PS_INPUT_CNTL_31},
237 {0, 0, R_0286C4_SPI_VS_OUT_CONFIG},
238 {0, 0, R_0286C8_SPI_THREAD_GROUPING},
239 {0, 0, R_0286CC_SPI_PS_IN_CONTROL_0},
240 {0, 0, R_0286D0_SPI_PS_IN_CONTROL_1},
241 {0, 0, R_0286D4_SPI_INTERP_CONTROL_0},
242 {0, 0, R_0286D8_SPI_INPUT_Z},
243 {0, 0, R_0286DC_SPI_FOG_CNTL},
244 {0, 0, R_0286E0_SPI_BARYC_CNTL},
245 {0, 0, R_0286E4_SPI_PS_IN_CONTROL_2},
246 {0, 0, R_0286E8_SPI_COMPUTE_INPUT_CNTL},
247 {0, 0, R_028780_CB_BLEND0_CONTROL},
248 {0, 0, R_028784_CB_BLEND1_CONTROL},
249 {0, 0, R_028788_CB_BLEND2_CONTROL},
250 {0, 0, R_02878C_CB_BLEND3_CONTROL},
251 {0, 0, R_028790_CB_BLEND4_CONTROL},
252 {0, 0, R_028794_CB_BLEND5_CONTROL},
253 {0, 0, R_028798_CB_BLEND6_CONTROL},
254 {0, 0, R_02879C_CB_BLEND7_CONTROL},
255 {0, 0, R_028800_DB_DEPTH_CONTROL},
256 {0, 0, R_02880C_DB_SHADER_CONTROL},
257 {0, 0, R_028808_CB_COLOR_CONTROL},
258 {0, 0, R_028810_PA_CL_CLIP_CNTL},
259 {0, 0, R_028814_PA_SU_SC_MODE_CNTL},
260 {0, 0, R_028818_PA_CL_VTE_CNTL},
261 {0, 0, R_02881C_PA_CL_VS_OUT_CNTL},
262 {0, 0, R_028820_PA_CL_NANINF_CNTL},
263 {0, 0, R_028838_SQ_DYN_GPR_RESOURCE_LIMIT_1},
264 {1, 0, R_028840_SQ_PGM_START_PS},
265 {0, 0, R_028844_SQ_PGM_RESOURCES_PS},
266 {0, 0, R_028848_SQ_PGM_RESOURCES_2_PS},
267 {0, 0, R_02884C_SQ_PGM_EXPORTS_PS},
268 {1, 0, R_02885C_SQ_PGM_START_VS},
269 {0, 0, R_028860_SQ_PGM_RESOURCES_VS},
270 {0, 0, R_028864_SQ_PGM_RESOURCES_2_VS},
271 {1, 0, R_0288A4_SQ_PGM_START_FS},
272 {0, 0, R_0288A8_SQ_PGM_RESOURCES_FS},
273 {0, 0, R_0288EC_SQ_LDS_ALLOC_PS},
274 {0, 0, R_028900_SQ_ESGS_RING_ITEMSIZE},
275 {0, 0, R_028904_SQ_GSVS_RING_ITEMSIZE},
276 {0, 0, R_028908_SQ_ESTMP_RING_ITEMSIZE},
277 {0, 0, R_02890C_SQ_GSTMP_RING_ITEMSIZE},
278 {0, 0, R_028910_SQ_VSTMP_RING_ITEMSIZE},
279 {0, 0, R_028914_SQ_PSTMP_RING_ITEMSIZE},
280 {0, 0, R_02891C_SQ_GS_VERT_ITEMSIZE},
281 {0, 0, R_028920_SQ_GS_VERT_ITEMSIZE_1},
282 {0, 0, R_028924_SQ_GS_VERT_ITEMSIZE_2},
283 {0, 0, R_028928_SQ_GS_VERT_ITEMSIZE_3},
284 {1, 0, R_028940_ALU_CONST_CACHE_PS_0},
285 {1, 0, R_028980_ALU_CONST_CACHE_VS_0},
286 {0, 0, R_028A00_PA_SU_POINT_SIZE},
287 {0, 0, R_028A04_PA_SU_POINT_MINMAX},
288 {0, 0, R_028A08_PA_SU_LINE_CNTL},
289 {0, 0, R_028A10_VGT_OUTPUT_PATH_CNTL},
290 {0, 0, R_028A14_VGT_HOS_CNTL},
291 {0, 0, R_028A18_VGT_HOS_MAX_TESS_LEVEL},
292 {0, 0, R_028A1C_VGT_HOS_MIN_TESS_LEVEL},
293 {0, 0, R_028A20_VGT_HOS_REUSE_DEPTH},
294 {0, 0, R_028A24_VGT_GROUP_PRIM_TYPE},
295 {0, 0, R_028A28_VGT_GROUP_FIRST_DECR},
296 {0, 0, R_028A2C_VGT_GROUP_DECR},
297 {0, 0, R_028A30_VGT_GROUP_VECT_0_CNTL},
298 {0, 0, R_028A34_VGT_GROUP_VECT_1_CNTL},
299 {0, 0, R_028A38_VGT_GROUP_VECT_0_FMT_CNTL},
300 {0, 0, R_028A3C_VGT_GROUP_VECT_1_FMT_CNTL},
301 {0, 0, R_028A40_VGT_GS_MODE},
302 {0, 0, R_028A48_PA_SC_MODE_CNTL_0},
303 {0, 0, R_028A4C_PA_SC_MODE_CNTL_1},
304 {0, 0, R_028AB4_VGT_REUSE_OFF},
305 {0, 0, R_028AB8_VGT_VTX_CNT_EN},
306 {0, 0, R_028ABC_DB_HTILE_SURFACE},
307 {0, 0, R_028AC0_DB_SRESULTS_COMPARE_STATE0},
308 {0, 0, R_028AC4_DB_SRESULTS_COMPARE_STATE1},
309 {0, 0, R_028AC8_DB_PRELOAD_CONTROL},
310 {0, 0, R_028B54_VGT_SHADER_STAGES_EN},
311 {0, 0, R_028B70_DB_ALPHA_TO_MASK},
312 {0, 0, R_028B78_PA_SU_POLY_OFFSET_DB_FMT_CNTL},
313 {0, 0, R_028B7C_PA_SU_POLY_OFFSET_CLAMP},
314 {0, 0, R_028B80_PA_SU_POLY_OFFSET_FRONT_SCALE},
315 {0, 0, R_028B84_PA_SU_POLY_OFFSET_FRONT_OFFSET},
316 {0, 0, R_028B88_PA_SU_POLY_OFFSET_BACK_SCALE},
317 {0, 0, R_028B8C_PA_SU_POLY_OFFSET_BACK_OFFSET},
318 {0, 0, R_028B94_VGT_STRMOUT_CONFIG},
319 {0, 0, R_028B98_VGT_STRMOUT_BUFFER_CONFIG},
320 {0, 0, R_028C00_PA_SC_LINE_CNTL},
321 {0, 0, R_028C04_PA_SC_AA_CONFIG},
322 {0, 0, R_028C08_PA_SU_VTX_CNTL},
323 {0, 0, R_028C0C_PA_CL_GB_VERT_CLIP_ADJ},
324 {0, 0, R_028C10_PA_CL_GB_VERT_DISC_ADJ},
325 {0, 0, R_028C14_PA_CL_GB_HORZ_CLIP_ADJ},
326 {0, 0, R_028C18_PA_CL_GB_HORZ_DISC_ADJ},
327 {0, 0, R_028C1C_PA_SC_AA_SAMPLE_LOCS_MCTX},
328 {0, 0, R_028C3C_PA_SC_AA_MASK},
329 {0, 0, GROUP_FORCE_NEW_BLOCK},
330 {1, 0, R_028C60_CB_COLOR0_BASE},
331 {0, 0, R_028C64_CB_COLOR0_PITCH},
332 {0, 0, R_028C68_CB_COLOR0_SLICE},
333 {0, 0, R_028C6C_CB_COLOR0_VIEW},
334 {1, 0, R_028C70_CB_COLOR0_INFO},
335 {0, 0, R_028C74_CB_COLOR0_ATTRIB},
336 {0, 0, R_028C78_CB_COLOR0_DIM},
337 {0, 0, GROUP_FORCE_NEW_BLOCK},
338 {1, 0, R_028C9C_CB_COLOR1_BASE},
339 {0, 0, R_028CA0_CB_COLOR1_PITCH},
340 {0, 0, R_028CA4_CB_COLOR1_SLICE},
341 {0, 0, R_028CA8_CB_COLOR1_VIEW},
342 {1, 0, R_028CAC_CB_COLOR1_INFO},
343 {0, 0, R_028CB0_CB_COLOR1_ATTRIB},
344 {0, 0, R_028CB8_CB_COLOR1_DIM},
345 {0, 0, GROUP_FORCE_NEW_BLOCK},
346 {1, 0, R_028CD8_CB_COLOR2_BASE},
347 {0, 0, R_028CDC_CB_COLOR2_PITCH},
348 {0, 0, R_028CE0_CB_COLOR2_SLICE},
349 {0, 0, R_028CE4_CB_COLOR2_VIEW},
350 {1, 0, R_028CE8_CB_COLOR2_INFO},
351 {0, 0, R_028CEC_CB_COLOR2_ATTRIB},
352 {0, 0, R_028CF0_CB_COLOR2_DIM},
353 {0, 0, GROUP_FORCE_NEW_BLOCK},
354 {1, 0, R_028D14_CB_COLOR3_BASE},
355 {0, 0, R_028D18_CB_COLOR3_PITCH},
356 {0, 0, R_028D1C_CB_COLOR3_SLICE},
357 {0, 0, R_028D20_CB_COLOR3_VIEW},
358 {1, 0, R_028D24_CB_COLOR3_INFO},
359 {0, 0, R_028D28_CB_COLOR3_ATTRIB},
360 {0, 0, R_028D2C_CB_COLOR3_DIM},
361 {0, 0, GROUP_FORCE_NEW_BLOCK},
362 {1, 0, R_028D50_CB_COLOR4_BASE},
363 {0, 0, R_028D54_CB_COLOR4_PITCH},
364 {0, 0, R_028D58_CB_COLOR4_SLICE},
365 {0, 0, R_028D5C_CB_COLOR4_VIEW},
366 {1, 0, R_028D60_CB_COLOR4_INFO},
367 {0, 0, R_028D64_CB_COLOR4_ATTRIB},
368 {0, 0, R_028D68_CB_COLOR4_DIM},
369 {0, 0, GROUP_FORCE_NEW_BLOCK},
370 {1, 0, R_028D8C_CB_COLOR5_BASE},
371 {0, 0, R_028D90_CB_COLOR5_PITCH},
372 {0, 0, R_028D94_CB_COLOR5_SLICE},
373 {0, 0, R_028D98_CB_COLOR5_VIEW},
374 {1, 0, R_028D9C_CB_COLOR5_INFO},
375 {0, 0, R_028DA0_CB_COLOR5_ATTRIB},
376 {0, 0, R_028DA4_CB_COLOR5_DIM},
377 {0, 0, GROUP_FORCE_NEW_BLOCK},
378 {1, 0, R_028DC8_CB_COLOR6_BASE},
379 {0, 0, R_028DCC_CB_COLOR6_PITCH},
380 {0, 0, R_028DD0_CB_COLOR6_SLICE},
381 {0, 0, R_028DD4_CB_COLOR6_VIEW},
382 {1, 0, R_028DD8_CB_COLOR6_INFO},
383 {0, 0, R_028DDC_CB_COLOR6_ATTRIB},
384 {0, 0, R_028DE0_CB_COLOR6_DIM},
385 {0, 0, GROUP_FORCE_NEW_BLOCK},
386 {1, 0, R_028E04_CB_COLOR7_BASE},
387 {0, 0, R_028E08_CB_COLOR7_PITCH},
388 {0, 0, R_028E0C_CB_COLOR7_SLICE},
389 {0, 0, R_028E10_CB_COLOR7_VIEW},
390 {1, 0, R_028E14_CB_COLOR7_INFO},
391 {0, 0, R_028E18_CB_COLOR7_ATTRIB},
392 {0, 0, R_028E1C_CB_COLOR7_DIM},
393 {0, 0, GROUP_FORCE_NEW_BLOCK},
394 {1, 0, R_028E40_CB_COLOR8_BASE},
395 {0, 0, R_028E44_CB_COLOR8_PITCH},
396 {0, 0, R_028E48_CB_COLOR8_SLICE},
397 {0, 0, R_028E4C_CB_COLOR8_VIEW},
398 {1, 0, R_028E50_CB_COLOR8_INFO},
399 {0, 0, R_028E54_CB_COLOR8_ATTRIB},
400 {0, 0, R_028E58_CB_COLOR8_DIM},
401 {0, 0, GROUP_FORCE_NEW_BLOCK},
402 {1, 0, R_028E5C_CB_COLOR9_BASE},
403 {0, 0, R_028E60_CB_COLOR9_PITCH},
404 {0, 0, R_028E64_CB_COLOR9_SLICE},
405 {0, 0, R_028E68_CB_COLOR9_VIEW},
406 {1, 0, R_028E6C_CB_COLOR9_INFO},
407 {0, 0, R_028E70_CB_COLOR9_ATTRIB},
408 {0, 0, R_028E74_CB_COLOR9_DIM},
409 {0, 0, GROUP_FORCE_NEW_BLOCK},
410 {1, 0, R_028E78_CB_COLOR10_BASE},
411 {0, 0, R_028E7C_CB_COLOR10_PITCH},
412 {0, 0, R_028E80_CB_COLOR10_SLICE},
413 {0, 0, R_028E84_CB_COLOR10_VIEW},
414 {1, 0, R_028E88_CB_COLOR10_INFO},
415 {0, 0, R_028E8C_CB_COLOR10_ATTRIB},
416 {0, 0, R_028E90_CB_COLOR10_DIM},
417 {0, 0, GROUP_FORCE_NEW_BLOCK},
418 {1, 0, R_028E94_CB_COLOR11_BASE},
419 {0, 0, R_028E98_CB_COLOR11_PITCH},
420 {0, 0, R_028E9C_CB_COLOR11_SLICE},
421 {0, 0, R_028EA0_CB_COLOR11_VIEW},
422 {1, 0, R_028EA4_CB_COLOR11_INFO},
423 {0, 0, R_028EA8_CB_COLOR11_ATTRIB},
424 {0, 0, R_028EAC_CB_COLOR11_DIM},
425 };
426
427 /* SHADER RESOURCE R600/R700 */
428 static int evergreen_state_resource_init(struct r600_context *ctx, u32 offset)
429 {
430 struct r600_reg r600_shader_resource[] = {
431 {0, 0, R_030000_RESOURCE0_WORD0},
432 {0, 0, R_030004_RESOURCE0_WORD1},
433 {1, 0, R_030008_RESOURCE0_WORD2},
434 {1, 0, R_03000C_RESOURCE0_WORD3},
435 {0, 0, R_030010_RESOURCE0_WORD4},
436 {0, 0, R_030014_RESOURCE0_WORD5},
437 {0, 0, R_030018_RESOURCE0_WORD6},
438 {0, 0, R_03001C_RESOURCE0_WORD7},
439 };
440 unsigned nreg = sizeof(r600_shader_resource)/sizeof(struct r600_reg);
441
442 for (int i = 0; i < nreg; i++) {
443 r600_shader_resource[i].offset += offset;
444 }
445 return r600_context_add_block(ctx, r600_shader_resource, nreg);
446 }
447
448 /* SHADER SAMPLER R600/R700 */
449 static int r600_state_sampler_init(struct r600_context *ctx, u32 offset)
450 {
451 struct r600_reg r600_shader_sampler[] = {
452 {0, 0, R_03C000_SQ_TEX_SAMPLER_WORD0_0},
453 {0, 0, R_03C004_SQ_TEX_SAMPLER_WORD1_0},
454 {0, 0, R_03C008_SQ_TEX_SAMPLER_WORD2_0},
455 };
456 unsigned nreg = sizeof(r600_shader_sampler)/sizeof(struct r600_reg);
457
458 for (int i = 0; i < nreg; i++) {
459 r600_shader_sampler[i].offset += offset;
460 }
461 return r600_context_add_block(ctx, r600_shader_sampler, nreg);
462 }
463
464 int evergreen_context_init(struct r600_context *ctx, struct radeon *radeon)
465 {
466 int r;
467
468 memset(ctx, 0, sizeof(struct r600_context));
469 radeon->use_mem_constant = TRUE;
470 ctx->radeon = radeon;
471 LIST_INITHEAD(&ctx->query_list);
472 /* initialize groups */
473 r = r600_group_init(&ctx->groups[EVERGREEN_GROUP_CONFIG], EVERGREEN_CONFIG_REG_OFFSET, EVERGREEN_CONFIG_REG_END);
474 if (r) {
475 goto out_err;
476 }
477 r = r600_group_init(&ctx->groups[EVERGREEN_GROUP_LOOP_CONST], EVERGREEN_LOOP_CONST_OFFSET, EVERGREEN_LOOP_CONST_END);
478 if (r) {
479 goto out_err;
480 }
481 r = r600_group_init(&ctx->groups[EVERGREEN_GROUP_BOOL_CONST], EVERGREEN_BOOL_CONST_OFFSET, EVERGREEN_BOOL_CONST_END);
482 if (r) {
483 goto out_err;
484 }
485 r = r600_group_init(&ctx->groups[EVERGREEN_GROUP_SAMPLER], EVERGREEN_SAMPLER_OFFSET, EVERGREEN_SAMPLER_END);
486 if (r) {
487 goto out_err;
488 }
489 r = r600_group_init(&ctx->groups[EVERGREEN_GROUP_RESOURCE], EVERGREEN_RESOURCE_OFFSET, EVERGREEN_RESOURCE_END);
490 if (r) {
491 goto out_err;
492 }
493 r = r600_group_init(&ctx->groups[EVERGREEN_GROUP_CONTEXT], EVERGREEN_CONTEXT_REG_OFFSET, EVERGREEN_CONTEXT_REG_END);
494 if (r) {
495 goto out_err;
496 }
497 ctx->ngroups = EVERGREEN_NGROUPS;
498
499 /* add blocks */
500 r = r600_context_add_block(ctx, evergreen_reg_list, sizeof(evergreen_reg_list)/sizeof(struct r600_reg));
501 if (r)
502 goto out_err;
503
504 /* PS SAMPLER */
505 for (int j = 0, offset = 0; j < 18; j++, offset += 0xC) {
506 r = r600_state_sampler_init(ctx, offset);
507 if (r)
508 goto out_err;
509 }
510 /* VS SAMPLER */
511 for (int j = 0, offset = 0xD8; j < 18; j++, offset += 0xC) {
512 r = r600_state_sampler_init(ctx, offset);
513 if (r)
514 goto out_err;
515 }
516 /* PS RESOURCE */
517 for (int j = 0, offset = 0; j < 176; j++, offset += 0x20) {
518 r = evergreen_state_resource_init(ctx, offset);
519 if (r)
520 goto out_err;
521 }
522 /* VS RESOURCE */
523 for (int j = 0, offset = 0x1600; j < 176; j++, offset += 0x20) {
524 r = evergreen_state_resource_init(ctx, offset);
525 if (r)
526 goto out_err;
527 }
528
529 /* allocate cs variables */
530 ctx->nreloc = RADEON_CTX_MAX_PM4;
531 ctx->reloc = calloc(ctx->nreloc, sizeof(struct r600_reloc));
532 if (ctx->reloc == NULL) {
533 r = -ENOMEM;
534 goto out_err;
535 }
536 ctx->bo = calloc(ctx->nreloc, sizeof(void *));
537 if (ctx->bo == NULL) {
538 r = -ENOMEM;
539 goto out_err;
540 }
541 ctx->pm4_ndwords = RADEON_CTX_MAX_PM4;
542 ctx->pm4 = calloc(ctx->pm4_ndwords, 4);
543 if (ctx->pm4 == NULL) {
544 r = -ENOMEM;
545 goto out_err;
546 }
547 return 0;
548 out_err:
549 r600_context_fini(ctx);
550 return r;
551 }
552
553 void evergreen_context_draw(struct r600_context *ctx, const struct r600_draw *draw)
554 {
555 struct radeon_bo *cb[12];
556 unsigned ndwords = 9;
557
558 if (draw->indices) {
559 ndwords = 13;
560 /* make sure there is enough relocation space before scheduling draw */
561 if (ctx->creloc >= (ctx->nreloc - 1)) {
562 r600_context_flush(ctx);
563 }
564 }
565
566 /* find number of color buffer */
567 cb[0] = r600_context_reg_bo(ctx, EVERGREEN_GROUP_CONTEXT, R_028C60_CB_COLOR0_BASE);
568 cb[1] = r600_context_reg_bo(ctx, EVERGREEN_GROUP_CONTEXT, R_028C9C_CB_COLOR1_BASE);
569 cb[2] = r600_context_reg_bo(ctx, EVERGREEN_GROUP_CONTEXT, R_028CD8_CB_COLOR2_BASE);
570 cb[3] = r600_context_reg_bo(ctx, EVERGREEN_GROUP_CONTEXT, R_028D14_CB_COLOR3_BASE);
571 cb[4] = r600_context_reg_bo(ctx, EVERGREEN_GROUP_CONTEXT, R_028D50_CB_COLOR4_BASE);
572 cb[5] = r600_context_reg_bo(ctx, EVERGREEN_GROUP_CONTEXT, R_028D8C_CB_COLOR5_BASE);
573 cb[6] = r600_context_reg_bo(ctx, EVERGREEN_GROUP_CONTEXT, R_028DC8_CB_COLOR6_BASE);
574 cb[7] = r600_context_reg_bo(ctx, EVERGREEN_GROUP_CONTEXT, R_028E04_CB_COLOR7_BASE);
575 cb[8] = r600_context_reg_bo(ctx, EVERGREEN_GROUP_CONTEXT, R_028E40_CB_COLOR8_BASE);
576 cb[9] = r600_context_reg_bo(ctx, EVERGREEN_GROUP_CONTEXT, R_028E5C_CB_COLOR9_BASE);
577 cb[10] = r600_context_reg_bo(ctx, EVERGREEN_GROUP_CONTEXT, R_028E78_CB_COLOR10_BASE);
578 cb[11] = r600_context_reg_bo(ctx, EVERGREEN_GROUP_CONTEXT, R_028E94_CB_COLOR11_BASE);
579 for (int i = 0; i < 12; i++) {
580 if (cb[i]) {
581 ndwords += 7;
582 }
583 }
584
585 if ((ctx->pm4_dirty_cdwords + ndwords + ctx->pm4_cdwords) > ctx->pm4_ndwords) {
586 /* need to flush */
587 r600_context_flush(ctx);
588 }
589 /* at that point everythings is flushed and ctx->pm4_cdwords = 0 */
590 if ((ctx->pm4_dirty_cdwords + ndwords) > ctx->pm4_ndwords) {
591 R600_ERR("context is too big to be scheduled\n");
592 return;
593 }
594
595 /* enough room to copy packet */
596 r600_context_group_emit_dirty(ctx, &ctx->groups[EVERGREEN_GROUP_CONFIG], PKT3_SET_CONFIG_REG);
597 r600_context_group_emit_dirty(ctx, &ctx->groups[EVERGREEN_GROUP_CONTEXT], PKT3_SET_CONTEXT_REG);
598 r600_context_group_emit_dirty(ctx, &ctx->groups[EVERGREEN_GROUP_RESOURCE], PKT3_SET_RESOURCE);
599 r600_context_group_emit_dirty(ctx, &ctx->groups[EVERGREEN_GROUP_SAMPLER], PKT3_SET_SAMPLER);
600
601 /* draw packet */
602 ctx->pm4[ctx->pm4_cdwords++] = PKT3(PKT3_INDEX_TYPE, 0);
603 ctx->pm4[ctx->pm4_cdwords++] = draw->vgt_index_type;
604 ctx->pm4[ctx->pm4_cdwords++] = PKT3(PKT3_NUM_INSTANCES, 0);
605 ctx->pm4[ctx->pm4_cdwords++] = draw->vgt_num_instances;
606 if (draw->indices) {
607 ctx->pm4[ctx->pm4_cdwords++] = PKT3(PKT3_DRAW_INDEX, 3);
608 ctx->pm4[ctx->pm4_cdwords++] = draw->indices_bo_offset;
609 ctx->pm4[ctx->pm4_cdwords++] = 0;
610 ctx->pm4[ctx->pm4_cdwords++] = draw->vgt_num_indices;
611 ctx->pm4[ctx->pm4_cdwords++] = draw->vgt_draw_initiator;
612 ctx->pm4[ctx->pm4_cdwords++] = PKT3(PKT3_NOP, 0);
613 ctx->pm4[ctx->pm4_cdwords++] = 0;
614 r600_context_bo_reloc(ctx, &ctx->pm4[ctx->pm4_cdwords - 1], radeon_bo_pb_get_bo(draw->indices->pb));
615 } else {
616 ctx->pm4[ctx->pm4_cdwords++] = PKT3(PKT3_DRAW_INDEX_AUTO, 1);
617 ctx->pm4[ctx->pm4_cdwords++] = draw->vgt_num_indices;
618 ctx->pm4[ctx->pm4_cdwords++] = draw->vgt_draw_initiator;
619 }
620 ctx->pm4[ctx->pm4_cdwords++] = PKT3(PKT3_EVENT_WRITE, 0);
621 ctx->pm4[ctx->pm4_cdwords++] = EVENT_TYPE_CACHE_FLUSH_AND_INV_EVENT;
622
623 /* flush color buffer */
624 for (int i = 0; i < 8; i++) {
625 if (cb[i]) {
626 ctx->pm4[ctx->pm4_cdwords++] = PKT3(PKT3_SURFACE_SYNC, 3);
627 ctx->pm4[ctx->pm4_cdwords++] = (S_0085F0_CB0_DEST_BASE_ENA(1) << i) |
628 S_0085F0_CB_ACTION_ENA(1);
629 ctx->pm4[ctx->pm4_cdwords++] = (cb[i]->size + 255) >> 8;
630 ctx->pm4[ctx->pm4_cdwords++] = 0x00000000;
631 ctx->pm4[ctx->pm4_cdwords++] = 0x0000000A;
632 ctx->pm4[ctx->pm4_cdwords++] = PKT3(PKT3_NOP, 0);
633 ctx->pm4[ctx->pm4_cdwords++] = 0;
634 r600_context_bo_reloc(ctx, &ctx->pm4[ctx->pm4_cdwords - 1], cb[i]);
635 }
636 }
637
638 /* all dirty state have been scheduled in current cs */
639 ctx->pm4_dirty_cdwords = 0;
640 }
641
642 static inline void evergreen_resource_set(struct r600_context *ctx, struct r600_pipe_state *state, unsigned offset)
643 {
644 struct r600_group_block *block;
645 unsigned id;
646
647 offset -= ctx->groups[EVERGREEN_GROUP_RESOURCE].start_offset;
648 id = ctx->groups[EVERGREEN_GROUP_RESOURCE].offset_block_id[offset >> 2];
649 block = &ctx->groups[EVERGREEN_GROUP_RESOURCE].blocks[id];
650 block->pm4[0] = state->regs[0].value;
651 block->pm4[1] = state->regs[1].value;
652 block->pm4[2] = state->regs[2].value;
653 block->pm4[3] = state->regs[3].value;
654 block->pm4[4] = state->regs[4].value;
655 block->pm4[5] = state->regs[5].value;
656 block->pm4[6] = state->regs[6].value;
657 block->pm4[7] = state->regs[7].value;
658 radeon_ws_bo_reference(ctx->radeon, &block->reloc[1].bo, NULL);
659 radeon_ws_bo_reference(ctx->radeon , &block->reloc[2].bo, NULL);
660 if (state->regs[0].bo) {
661 /* VERTEX RESOURCE, we preted there is 2 bo to relocate so
662 * we have single case btw VERTEX & TEXTURE resource
663 */
664 radeon_ws_bo_reference(ctx->radeon, &block->reloc[1].bo, state->regs[0].bo);
665 radeon_ws_bo_reference(ctx->radeon, &block->reloc[2].bo, state->regs[0].bo);
666 } else {
667 /* TEXTURE RESOURCE */
668 radeon_ws_bo_reference(ctx->radeon, &block->reloc[1].bo, state->regs[2].bo);
669 radeon_ws_bo_reference(ctx->radeon, &block->reloc[2].bo, state->regs[3].bo);
670 }
671 block->status |= R600_BLOCK_STATUS_ENABLED;
672 block->status |= R600_BLOCK_STATUS_DIRTY;
673 ctx->pm4_dirty_cdwords += 2 + block->pm4_ndwords;
674 }
675
676 void evergreen_ps_resource_set(struct r600_context *ctx, struct r600_pipe_state *state, unsigned rid)
677 {
678 unsigned offset = R_030000_RESOURCE0_WORD0 + 0x20 * rid;
679
680 evergreen_resource_set(ctx, state, offset);
681 }
682
683 void evergreen_vs_resource_set(struct r600_context *ctx, struct r600_pipe_state *state, unsigned rid)
684 {
685 unsigned offset = R_030000_RESOURCE0_WORD0 + 0x1600 + 0x20 * rid;
686
687 evergreen_resource_set(ctx, state, offset);
688 }