r600g: remove the cache buffer manager from winsys/r600
[mesa.git] / src / gallium / winsys / r600 / drm / r600_bo.c
1 /*
2 * Copyright 2010 Dave Airlie
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * on the rights to use, copy, modify, merge, publish, distribute, sub
8 * license, and/or sell copies of the Software, and to permit persons to whom
9 * the Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
22 *
23 * Authors:
24 * Dave Airlie
25 */
26 #include "r600_priv.h"
27 #include "r600d.h"
28 #include "state_tracker/drm_driver.h"
29 #include "radeon_drm.h"
30
31 struct r600_bo *r600_bo(struct radeon *radeon,
32 unsigned size, unsigned alignment,
33 unsigned binding, unsigned usage)
34 {
35 struct r600_bo *bo;
36 struct radeon_bo *rbo;
37 uint32_t initial_domain, domains;
38
39 /* Staging resources particpate in transfers and blits only
40 * and are used for uploads and downloads from regular
41 * resources. We generate them internally for some transfers.
42 */
43 if (usage == PIPE_USAGE_STAGING)
44 domains = RADEON_GEM_DOMAIN_CPU | RADEON_GEM_DOMAIN_GTT;
45 else
46 domains = (RADEON_GEM_DOMAIN_CPU |
47 RADEON_GEM_DOMAIN_GTT |
48 RADEON_GEM_DOMAIN_VRAM);
49
50 switch(usage) {
51 case PIPE_USAGE_DYNAMIC:
52 case PIPE_USAGE_STREAM:
53 case PIPE_USAGE_STAGING:
54 initial_domain = RADEON_GEM_DOMAIN_GTT;
55 break;
56 case PIPE_USAGE_DEFAULT:
57 case PIPE_USAGE_STATIC:
58 case PIPE_USAGE_IMMUTABLE:
59 default:
60 initial_domain = RADEON_GEM_DOMAIN_VRAM;
61 break;
62 }
63 rbo = radeon_bo(radeon, 0, size, alignment, binding, initial_domain);
64 if (rbo == NULL) {
65 return NULL;
66 }
67
68 bo = calloc(1, sizeof(struct r600_bo));
69 bo->size = size;
70 bo->domains = domains;
71 bo->bo = rbo;
72
73 pipe_reference_init(&bo->reference, 1);
74 return bo;
75 }
76
77 struct r600_bo *r600_bo_handle(struct radeon *radeon, struct winsys_handle *whandle,
78 unsigned *stride, unsigned *array_mode)
79 {
80 struct r600_bo *bo = calloc(1, sizeof(struct r600_bo));
81 struct radeon_bo *rbo;
82 unsigned tiling_flags;
83
84 rbo = bo->bo = radeon_bo(radeon, whandle->handle, 0, 0, 0, 0);
85 if (rbo == NULL) {
86 free(bo);
87 return NULL;
88 }
89
90 pipe_reference_init(&bo->reference, 1);
91 bo->size = rbo->size;
92 bo->domains = (RADEON_GEM_DOMAIN_CPU |
93 RADEON_GEM_DOMAIN_GTT |
94 RADEON_GEM_DOMAIN_VRAM);
95
96 if (stride)
97 *stride = whandle->stride;
98
99 radeon_bo_get_tiling_flags(radeon, rbo, &tiling_flags);
100 if (array_mode) {
101 if (tiling_flags) {
102 if (tiling_flags & RADEON_TILING_MACRO)
103 *array_mode = V_0280A0_ARRAY_2D_TILED_THIN1;
104 else if (tiling_flags & RADEON_TILING_MICRO)
105 *array_mode = V_0280A0_ARRAY_1D_TILED_THIN1;
106 } else {
107 *array_mode = 0;
108 }
109 }
110 return bo;
111 }
112
113 void *r600_bo_map(struct radeon *radeon, struct r600_bo *bo, unsigned usage, void *ctx)
114 {
115 struct pipe_context *pctx = ctx;
116
117 if (usage & PIPE_TRANSFER_UNSYNCHRONIZED) {
118 radeon_bo_map(radeon, bo->bo);
119 return (uint8_t *) bo->bo->data;
120 }
121
122 if (p_atomic_read(&bo->bo->reference.count) > 1) {
123 if (usage & PIPE_TRANSFER_DONTBLOCK) {
124 return NULL;
125 }
126 if (ctx) {
127 pctx->flush(pctx, NULL);
128 }
129 }
130
131 if (usage & PIPE_TRANSFER_DONTBLOCK) {
132 uint32_t domain;
133
134 if (radeon_bo_busy(radeon, bo->bo, &domain))
135 return NULL;
136 if (radeon_bo_map(radeon, bo->bo)) {
137 return NULL;
138 }
139 goto out;
140 }
141
142 radeon_bo_map(radeon, bo->bo);
143 if (radeon_bo_wait(radeon, bo->bo)) {
144 radeon_bo_unmap(radeon, bo->bo);
145 return NULL;
146 }
147
148 out:
149 return (uint8_t *) bo->bo->data;
150 }
151
152 void r600_bo_unmap(struct radeon *radeon, struct r600_bo *bo)
153 {
154 radeon_bo_unmap(radeon, bo->bo);
155 }
156
157 void r600_bo_destroy(struct radeon *radeon, struct r600_bo *bo)
158 {
159 radeon_bo_reference(radeon, &bo->bo, NULL);
160 free(bo);
161 }
162
163 boolean r600_bo_get_winsys_handle(struct radeon *radeon, struct r600_bo *bo,
164 unsigned stride, struct winsys_handle *whandle)
165 {
166 whandle->stride = stride;
167 switch(whandle->type) {
168 case DRM_API_HANDLE_TYPE_KMS:
169 whandle->handle = bo->bo->handle;
170 break;
171 case DRM_API_HANDLE_TYPE_SHARED:
172 if (radeon_bo_get_name(radeon, bo->bo, &whandle->handle))
173 return FALSE;
174 break;
175 default:
176 return FALSE;
177 }
178
179 return TRUE;
180 }