2 * Copyright 2010 Jerome Glisse <glisse@freedesktop.org>
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * on the rights to use, copy, modify, merge, publish, distribute, sub
8 * license, and/or sell copies of the Software, and to permit persons to whom
9 * the Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
25 * Corbin Simpson <MostAwesomeDude@gmail.com>
26 * Joakim Sindholt <opensource@zhasha.com>
30 #include <sys/ioctl.h>
31 #include "util/u_inlines.h"
32 #include "util/u_debug.h"
33 #include "util/u_hash_table.h"
34 #include <pipebuffer/pb_bufmgr.h>
36 #include "r600_priv.h"
37 #include "r600_drm_public.h"
39 #include "radeon_drm.h"
41 #ifndef RADEON_INFO_TILING_CONFIG
42 #define RADEON_INFO_TILING_CONFIG 0x6
45 #ifndef RADEON_INFO_CLOCK_CRYSTAL_FREQ
46 #define RADEON_INFO_CLOCK_CRYSTAL_FREQ 0x9
49 #ifndef RADEON_INFO_NUM_BACKENDS
50 #define RADEON_INFO_NUM_BACKENDS 0xa
53 enum radeon_family
r600_get_family(struct radeon
*r600
)
58 enum chip_class
r600_get_family_class(struct radeon
*radeon
)
60 return radeon
->chip_class
;
63 struct r600_tiling_info
*r600_get_tiling_info(struct radeon
*radeon
)
65 return &radeon
->tiling_info
;
68 unsigned r600_get_clock_crystal_freq(struct radeon
*radeon
)
70 return radeon
->clock_crystal_freq
;
73 unsigned r600_get_num_backends(struct radeon
*radeon
)
75 return radeon
->num_backends
;
78 unsigned r600_get_minor_version(struct radeon
*radeon
)
80 return radeon
->minor_version
;
84 static int radeon_get_device(struct radeon
*radeon
)
86 struct drm_radeon_info info
= {};
90 info
.request
= RADEON_INFO_DEVICE_ID
;
91 info
.value
= (uintptr_t)&radeon
->device
;
92 r
= drmCommandWriteRead(radeon
->fd
, DRM_RADEON_INFO
, &info
,
93 sizeof(struct drm_radeon_info
));
97 static int r600_interpret_tiling(struct radeon
*radeon
, uint32_t tiling_config
)
99 switch ((tiling_config
& 0xe) >> 1) {
101 radeon
->tiling_info
.num_channels
= 1;
104 radeon
->tiling_info
.num_channels
= 2;
107 radeon
->tiling_info
.num_channels
= 4;
110 radeon
->tiling_info
.num_channels
= 8;
116 switch ((tiling_config
& 0x30) >> 4) {
118 radeon
->tiling_info
.num_banks
= 4;
121 radeon
->tiling_info
.num_banks
= 8;
127 switch ((tiling_config
& 0xc0) >> 6) {
129 radeon
->tiling_info
.group_bytes
= 256;
132 radeon
->tiling_info
.group_bytes
= 512;
140 static int eg_interpret_tiling(struct radeon
*radeon
, uint32_t tiling_config
)
142 switch (tiling_config
& 0xf) {
144 radeon
->tiling_info
.num_channels
= 1;
147 radeon
->tiling_info
.num_channels
= 2;
150 radeon
->tiling_info
.num_channels
= 4;
153 radeon
->tiling_info
.num_channels
= 8;
159 radeon
->tiling_info
.num_banks
= (tiling_config
& 0xf0) >> 4;
161 switch ((tiling_config
& 0xf00) >> 8) {
163 radeon
->tiling_info
.group_bytes
= 256;
166 radeon
->tiling_info
.group_bytes
= 512;
174 static int radeon_drm_get_tiling(struct radeon
*radeon
)
176 struct drm_radeon_info info
;
178 uint32_t tiling_config
= 0;
180 info
.request
= RADEON_INFO_TILING_CONFIG
;
181 info
.value
= (uintptr_t)&tiling_config
;
182 r
= drmCommandWriteRead(radeon
->fd
, DRM_RADEON_INFO
, &info
,
183 sizeof(struct drm_radeon_info
));
188 if (radeon
->chip_class
== R600
|| radeon
->chip_class
== R700
) {
189 r
= r600_interpret_tiling(radeon
, tiling_config
);
191 r
= eg_interpret_tiling(radeon
, tiling_config
);
196 static int radeon_get_clock_crystal_freq(struct radeon
*radeon
)
198 struct drm_radeon_info info
;
199 uint32_t clock_crystal_freq
;
202 info
.request
= RADEON_INFO_CLOCK_CRYSTAL_FREQ
;
203 info
.value
= (uintptr_t)&clock_crystal_freq
;
204 r
= drmCommandWriteRead(radeon
->fd
, DRM_RADEON_INFO
, &info
,
205 sizeof(struct drm_radeon_info
));
209 radeon
->clock_crystal_freq
= clock_crystal_freq
;
214 static int radeon_get_num_backends(struct radeon
*radeon
)
216 struct drm_radeon_info info
;
217 uint32_t num_backends
;
220 info
.request
= RADEON_INFO_NUM_BACKENDS
;
221 info
.value
= (uintptr_t)&num_backends
;
222 r
= drmCommandWriteRead(radeon
->fd
, DRM_RADEON_INFO
, &info
,
223 sizeof(struct drm_radeon_info
));
227 radeon
->num_backends
= num_backends
;
232 static int radeon_init_fence(struct radeon
*radeon
)
235 radeon
->fence_bo
= r600_bo(radeon
, 4096, 0, 0, 0);
236 if (radeon
->fence_bo
== NULL
) {
239 radeon
->cfence
= r600_bo_map(radeon
, radeon
->fence_bo
, PB_USAGE_UNSYNCHRONIZED
, NULL
);
244 #define PTR_TO_UINT(x) ((unsigned)((intptr_t)(x)))
246 static unsigned handle_hash(void *key
)
248 return PTR_TO_UINT(key
);
251 static int handle_compare(void *key1
, void *key2
)
253 return PTR_TO_UINT(key1
) != PTR_TO_UINT(key2
);
256 static struct radeon
*radeon_new(int fd
, unsigned device
)
258 struct radeon
*radeon
;
260 drmVersionPtr version
;
262 radeon
= calloc(1, sizeof(*radeon
));
263 if (radeon
== NULL
) {
267 radeon
->device
= device
;
268 radeon
->refcount
= 1;
270 version
= drmGetVersion(radeon
->fd
);
271 if (version
->version_major
!= 2) {
272 fprintf(stderr
, "%s: DRM version is %d.%d.%d but this driver is "
273 "only compatible with 2.x.x\n", __FUNCTION__
,
274 version
->version_major
, version
->version_minor
,
275 version
->version_patchlevel
);
276 drmFreeVersion(version
);
280 radeon
->minor_version
= version
->version_minor
;
282 drmFreeVersion(version
);
284 r
= radeon_get_device(radeon
);
286 fprintf(stderr
, "Failed to get device id\n");
287 return radeon_decref(radeon
);
290 radeon
->family
= radeon_family_from_device(radeon
->device
);
291 if (radeon
->family
== CHIP_UNKNOWN
) {
292 fprintf(stderr
, "Unknown chipset 0x%04X\n", radeon
->device
);
293 return radeon_decref(radeon
);
296 switch (radeon
->family
) {
305 radeon
->chip_class
= R600
;
306 /* set default group bytes, overridden by tiling info ioctl */
307 radeon
->tiling_info
.group_bytes
= 256;
313 radeon
->chip_class
= R700
;
314 /* set default group bytes, overridden by tiling info ioctl */
315 radeon
->tiling_info
.group_bytes
= 256;
326 radeon
->chip_class
= EVERGREEN
;
327 /* set default group bytes, overridden by tiling info ioctl */
328 radeon
->tiling_info
.group_bytes
= 512;
331 fprintf(stderr
, "%s unknown or unsupported chipset 0x%04X\n",
332 __func__
, radeon
->device
);
336 if (radeon_drm_get_tiling(radeon
))
339 /* get the GPU counter frequency, failure is non fatal */
340 radeon_get_clock_crystal_freq(radeon
);
342 if (radeon
->minor_version
>= 9)
343 radeon_get_num_backends(radeon
);
345 radeon
->bomgr
= r600_bomgr_create(radeon
, 1000000);
346 if (radeon
->bomgr
== NULL
) {
349 r
= radeon_init_fence(radeon
);
351 radeon_decref(radeon
);
355 radeon
->bo_handles
= util_hash_table_create(handle_hash
, handle_compare
);
356 pipe_mutex_init(radeon
->bo_handles_mutex
);
360 struct radeon
*r600_drm_winsys_create(int drmfd
)
362 return radeon_new(drmfd
, 0);
365 struct radeon
*radeon_decref(struct radeon
*radeon
)
369 if (--radeon
->refcount
> 0) {
373 util_hash_table_destroy(radeon
->bo_handles
);
374 pipe_mutex_destroy(radeon
->bo_handles_mutex
);
375 if (radeon
->fence_bo
) {
376 r600_bo_reference(radeon
, &radeon
->fence_bo
, NULL
);
380 r600_bomgr_destroy(radeon
->bomgr
);