2 * Copyright 2010 Jerome Glisse <glisse@freedesktop.org>
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * on the rights to use, copy, modify, merge, publish, distribute, sub
8 * license, and/or sell copies of the Software, and to permit persons to whom
9 * the Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
26 #include "r600_priv.h"
28 #include "util/u_memory.h"
31 #define GROUP_FORCE_NEW_BLOCK 0
33 /* Get backends mask */
34 void r600_get_backend_mask(struct r600_context
*ctx
)
36 struct r600_bo
* buffer
;
38 unsigned num_backends
= r600_get_num_backends(ctx
->radeon
);
41 /* if backend_map query is supported by the kernel */
42 if (ctx
->radeon
->info
.r600_backend_map_valid
) {
43 unsigned num_tile_pipes
= r600_get_num_tile_pipes(ctx
->radeon
);
44 unsigned backend_map
= r600_get_backend_map(ctx
->radeon
);
45 unsigned item_width
, item_mask
;
47 if (ctx
->radeon
->chip_class
>= EVERGREEN
) {
55 while(num_tile_pipes
--) {
56 i
= backend_map
& item_mask
;
58 backend_map
>>= item_width
;
61 ctx
->backend_mask
= mask
;
66 /* otherwise backup path for older kernels */
68 /* create buffer for event data */
69 buffer
= r600_bo(ctx
->radeon
, ctx
->max_db
*16, 1, 0,
74 /* initialize buffer with zeroes */
75 results
= r600_bo_map(ctx
->radeon
, buffer
, ctx
->cs
, PIPE_TRANSFER_WRITE
);
77 memset(results
, 0, ctx
->max_db
* 4 * 4);
78 r600_bo_unmap(ctx
->radeon
, buffer
);
80 /* emit EVENT_WRITE for ZPASS_DONE */
81 ctx
->pm4
[ctx
->pm4_cdwords
++] = PKT3(PKT3_EVENT_WRITE
, 2, 0);
82 ctx
->pm4
[ctx
->pm4_cdwords
++] = EVENT_TYPE(EVENT_TYPE_ZPASS_DONE
) | EVENT_INDEX(1);
83 ctx
->pm4
[ctx
->pm4_cdwords
++] = 0;
84 ctx
->pm4
[ctx
->pm4_cdwords
++] = 0;
86 ctx
->pm4
[ctx
->pm4_cdwords
++] = PKT3(PKT3_NOP
, 0, 0);
87 ctx
->pm4
[ctx
->pm4_cdwords
++] = r600_context_bo_reloc(ctx
, buffer
, RADEON_USAGE_WRITE
);
90 r600_context_flush(ctx
, 0);
93 results
= r600_bo_map(ctx
->radeon
, buffer
, ctx
->cs
, PIPE_TRANSFER_READ
);
95 for(i
= 0; i
< ctx
->max_db
; i
++) {
96 /* at least highest bit will be set if backend is used */
100 r600_bo_unmap(ctx
->radeon
, buffer
);
104 r600_bo_reference(&buffer
, NULL
);
107 ctx
->backend_mask
= mask
;
112 /* fallback to old method - set num_backends lower bits to 1 */
113 ctx
->backend_mask
= (~((u32
)0))>>(32-num_backends
);
117 static inline void r600_context_ps_partial_flush(struct r600_context
*ctx
)
119 if (!(ctx
->flags
& R600_CONTEXT_DRAW_PENDING
))
122 ctx
->pm4
[ctx
->pm4_cdwords
++] = PKT3(PKT3_EVENT_WRITE
, 0, 0);
123 ctx
->pm4
[ctx
->pm4_cdwords
++] = EVENT_TYPE(EVENT_TYPE_PS_PARTIAL_FLUSH
) | EVENT_INDEX(4);
125 ctx
->flags
&= ~R600_CONTEXT_DRAW_PENDING
;
128 void r600_init_cs(struct r600_context
*ctx
)
130 /* R6xx requires this packet at the start of each command buffer */
131 if (ctx
->radeon
->family
< CHIP_RV770
) {
132 ctx
->pm4
[ctx
->pm4_cdwords
++] = PKT3(PKT3_START_3D_CMDBUF
, 0, 0);
133 ctx
->pm4
[ctx
->pm4_cdwords
++] = 0x00000000;
135 /* All asics require this one */
136 ctx
->pm4
[ctx
->pm4_cdwords
++] = PKT3(PKT3_CONTEXT_CONTROL
, 1, 0);
137 ctx
->pm4
[ctx
->pm4_cdwords
++] = 0x80000000;
138 ctx
->pm4
[ctx
->pm4_cdwords
++] = 0x80000000;
140 ctx
->init_dwords
= ctx
->pm4_cdwords
;
143 static void r600_init_block(struct r600_context
*ctx
,
144 struct r600_block
*block
,
145 const struct r600_reg
*reg
, int index
, int nreg
,
146 unsigned opcode
, unsigned offset_base
)
151 /* initialize block */
152 if (opcode
== PKT3_SET_RESOURCE
) {
153 block
->flags
= BLOCK_FLAG_RESOURCE
;
154 block
->status
|= R600_BLOCK_STATUS_RESOURCE_DIRTY
; /* dirty all blocks at start */
157 block
->status
|= R600_BLOCK_STATUS_DIRTY
; /* dirty all blocks at start */
159 block
->start_offset
= reg
[i
].offset
;
160 block
->pm4
[block
->pm4_ndwords
++] = PKT3(opcode
, n
, 0);
161 block
->pm4
[block
->pm4_ndwords
++] = (block
->start_offset
- offset_base
) >> 2;
162 block
->reg
= &block
->pm4
[block
->pm4_ndwords
];
163 block
->pm4_ndwords
+= n
;
165 block
->nreg_dirty
= n
;
166 LIST_INITHEAD(&block
->list
);
167 LIST_INITHEAD(&block
->enable_list
);
169 for (j
= 0; j
< n
; j
++) {
170 if (reg
[i
+j
].flags
& REG_FLAG_DIRTY_ALWAYS
) {
171 block
->flags
|= REG_FLAG_DIRTY_ALWAYS
;
173 if (reg
[i
+j
].flags
& REG_FLAG_ENABLE_ALWAYS
) {
174 if (!(block
->status
& R600_BLOCK_STATUS_ENABLED
)) {
175 block
->status
|= R600_BLOCK_STATUS_ENABLED
;
176 LIST_ADDTAIL(&block
->enable_list
, &ctx
->enable_list
);
177 LIST_ADDTAIL(&block
->list
,&ctx
->dirty
);
180 if (reg
[i
+j
].flags
& REG_FLAG_FLUSH_CHANGE
) {
181 block
->flags
|= REG_FLAG_FLUSH_CHANGE
;
184 if (reg
[i
+j
].flags
& REG_FLAG_NEED_BO
) {
186 assert(block
->nbo
< R600_BLOCK_MAX_BO
);
187 block
->pm4_bo_index
[j
] = block
->nbo
;
188 block
->pm4
[block
->pm4_ndwords
++] = PKT3(PKT3_NOP
, 0, 0);
189 block
->pm4
[block
->pm4_ndwords
++] = 0x00000000;
190 if (reg
[i
+j
].flags
& REG_FLAG_RV6XX_SBU
) {
191 block
->reloc
[block
->nbo
].flush_flags
= 0;
192 block
->reloc
[block
->nbo
].flush_mask
= 0;
194 block
->reloc
[block
->nbo
].flush_flags
= reg
[i
+j
].flush_flags
;
195 block
->reloc
[block
->nbo
].flush_mask
= reg
[i
+j
].flush_mask
;
197 block
->reloc
[block
->nbo
].bo_pm4_index
= block
->pm4_ndwords
- 1;
199 if ((ctx
->radeon
->family
> CHIP_R600
) &&
200 (ctx
->radeon
->family
< CHIP_RV770
) && reg
[i
+j
].flags
& REG_FLAG_RV6XX_SBU
) {
201 block
->pm4
[block
->pm4_ndwords
++] = PKT3(PKT3_SURFACE_BASE_UPDATE
, 0, 0);
202 block
->pm4
[block
->pm4_ndwords
++] = reg
[i
+j
].flush_flags
;
205 for (j
= 0; j
< n
; j
++) {
206 if (reg
[i
+j
].flush_flags
) {
207 block
->pm4_flush_ndwords
+= 7;
210 /* check that we stay in limit */
211 assert(block
->pm4_ndwords
< R600_BLOCK_MAX_REG
);
214 int r600_context_add_block(struct r600_context
*ctx
, const struct r600_reg
*reg
, unsigned nreg
,
215 unsigned opcode
, unsigned offset_base
)
217 struct r600_block
*block
;
218 struct r600_range
*range
;
221 for (unsigned i
= 0, n
= 0; i
< nreg
; i
+= n
) {
222 /* ignore new block balise */
223 if (reg
[i
].offset
== GROUP_FORCE_NEW_BLOCK
) {
228 /* ignore regs not on R600 on R600 */
229 if ((reg
[i
].flags
& REG_FLAG_NOT_R600
) && ctx
->radeon
->family
== CHIP_R600
) {
234 /* register that need relocation are in their own group */
235 /* find number of consecutive registers */
237 offset
= reg
[i
].offset
;
238 while (reg
[i
+ n
].offset
== offset
) {
243 if (n
>= (R600_BLOCK_MAX_REG
- 2))
247 /* allocate new block */
248 block
= calloc(1, sizeof(struct r600_block
));
253 for (int j
= 0; j
< n
; j
++) {
254 range
= &ctx
->range
[CTX_RANGE_ID(reg
[i
+ j
].offset
)];
255 /* create block table if it doesn't exist */
257 range
->blocks
= calloc(1 << HASH_SHIFT
, sizeof(void *));
261 range
->blocks
[CTX_BLOCK_ID(reg
[i
+ j
].offset
)] = block
;
264 r600_init_block(ctx
, block
, reg
, i
, n
, opcode
, offset_base
);
270 /* R600/R700 configuration */
271 static const struct r600_reg r600_config_reg_list
[] = {
272 {R_008958_VGT_PRIMITIVE_TYPE
, 0, 0, 0},
273 {R_008C00_SQ_CONFIG
, REG_FLAG_ENABLE_ALWAYS
| REG_FLAG_FLUSH_CHANGE
, 0, 0},
274 {R_008C04_SQ_GPR_RESOURCE_MGMT_1
, REG_FLAG_ENABLE_ALWAYS
| REG_FLAG_FLUSH_CHANGE
, 0, 0},
275 {R_008C08_SQ_GPR_RESOURCE_MGMT_2
, REG_FLAG_ENABLE_ALWAYS
| REG_FLAG_FLUSH_CHANGE
, 0, 0},
276 {R_008C0C_SQ_THREAD_RESOURCE_MGMT
, REG_FLAG_ENABLE_ALWAYS
| REG_FLAG_FLUSH_CHANGE
, 0, 0},
277 {R_008C10_SQ_STACK_RESOURCE_MGMT_1
, REG_FLAG_ENABLE_ALWAYS
| REG_FLAG_FLUSH_CHANGE
, 0, 0},
278 {R_008C14_SQ_STACK_RESOURCE_MGMT_2
, REG_FLAG_ENABLE_ALWAYS
| REG_FLAG_FLUSH_CHANGE
, 0, 0},
279 {R_008D8C_SQ_DYN_GPR_CNTL_PS_FLUSH_REQ
, REG_FLAG_ENABLE_ALWAYS
| REG_FLAG_FLUSH_CHANGE
, 0, 0},
280 {R_009508_TA_CNTL_AUX
, REG_FLAG_ENABLE_ALWAYS
| REG_FLAG_FLUSH_CHANGE
, 0, 0},
281 {R_009714_VC_ENHANCE
, REG_FLAG_ENABLE_ALWAYS
| REG_FLAG_FLUSH_CHANGE
, 0, 0},
282 {R_009830_DB_DEBUG
, REG_FLAG_ENABLE_ALWAYS
| REG_FLAG_FLUSH_CHANGE
, 0, 0},
283 {R_009838_DB_WATERMARKS
, REG_FLAG_ENABLE_ALWAYS
| REG_FLAG_FLUSH_CHANGE
, 0, 0},
286 static const struct r600_reg r600_ctl_const_list
[] = {
287 {R_03CFF0_SQ_VTX_BASE_VTX_LOC
, 0, 0, 0},
288 {R_03CFF4_SQ_VTX_START_INST_LOC
, 0, 0, 0},
291 static const struct r600_reg r600_context_reg_list
[] = {
292 {R_028350_SX_MISC
, 0, 0, 0},
293 {R_0286C8_SPI_THREAD_GROUPING
, 0, 0, 0},
294 {R_0288A8_SQ_ESGS_RING_ITEMSIZE
, 0, 0, 0},
295 {R_0288AC_SQ_GSVS_RING_ITEMSIZE
, 0, 0, 0},
296 {R_0288B0_SQ_ESTMP_RING_ITEMSIZE
, 0, 0, 0},
297 {R_0288B4_SQ_GSTMP_RING_ITEMSIZE
, 0, 0, 0},
298 {R_0288B8_SQ_VSTMP_RING_ITEMSIZE
, 0, 0, 0},
299 {R_0288BC_SQ_PSTMP_RING_ITEMSIZE
, 0, 0, 0},
300 {R_0288C0_SQ_FBUF_RING_ITEMSIZE
, 0, 0, 0},
301 {R_0288C4_SQ_REDUC_RING_ITEMSIZE
, 0, 0, 0},
302 {R_0288C8_SQ_GS_VERT_ITEMSIZE
, 0, 0, 0},
303 {R_028A10_VGT_OUTPUT_PATH_CNTL
, 0, 0, 0},
304 {R_028A14_VGT_HOS_CNTL
, 0, 0, 0},
305 {R_028A18_VGT_HOS_MAX_TESS_LEVEL
, 0, 0, 0},
306 {R_028A1C_VGT_HOS_MIN_TESS_LEVEL
, 0, 0, 0},
307 {R_028A20_VGT_HOS_REUSE_DEPTH
, 0, 0, 0},
308 {R_028A24_VGT_GROUP_PRIM_TYPE
, 0, 0, 0},
309 {R_028A28_VGT_GROUP_FIRST_DECR
, 0, 0, 0},
310 {R_028A2C_VGT_GROUP_DECR
, 0, 0, 0},
311 {R_028A30_VGT_GROUP_VECT_0_CNTL
, 0, 0, 0},
312 {R_028A34_VGT_GROUP_VECT_1_CNTL
, 0, 0, 0},
313 {R_028A38_VGT_GROUP_VECT_0_FMT_CNTL
, 0, 0, 0},
314 {R_028A3C_VGT_GROUP_VECT_1_FMT_CNTL
, 0, 0, 0},
315 {R_028A40_VGT_GS_MODE
, 0, 0, 0},
316 {R_028A4C_PA_SC_MODE_CNTL
, 0, 0, 0},
317 {R_028AB0_VGT_STRMOUT_EN
, 0, 0, 0},
318 {R_028AB4_VGT_REUSE_OFF
, 0, 0, 0},
319 {R_028AB8_VGT_VTX_CNT_EN
, 0, 0, 0},
320 {R_028B20_VGT_STRMOUT_BUFFER_EN
, 0, 0, 0},
321 {R_028028_DB_STENCIL_CLEAR
, 0, 0, 0},
322 {R_02802C_DB_DEPTH_CLEAR
, 0, 0, 0},
323 {GROUP_FORCE_NEW_BLOCK
, 0, 0, 0},
324 {R_028040_CB_COLOR0_BASE
, REG_FLAG_NEED_BO
|REG_FLAG_RV6XX_SBU
, SURFACE_BASE_UPDATE_COLOR(0), 0},
325 {GROUP_FORCE_NEW_BLOCK
, 0, 0, 0},
326 {R_0280A0_CB_COLOR0_INFO
, REG_FLAG_NEED_BO
, 0, 0xFFFFFFFF},
327 {R_028060_CB_COLOR0_SIZE
, 0, 0, 0},
328 {R_028080_CB_COLOR0_VIEW
, 0, 0, 0},
329 {GROUP_FORCE_NEW_BLOCK
, 0, 0, 0},
330 {R_0280E0_CB_COLOR0_FRAG
, REG_FLAG_NEED_BO
, 0, 0},
331 {GROUP_FORCE_NEW_BLOCK
, 0, 0, 0},
332 {R_0280C0_CB_COLOR0_TILE
, REG_FLAG_NEED_BO
, 0, 0},
333 {R_028100_CB_COLOR0_MASK
, 0, 0, 0},
334 {GROUP_FORCE_NEW_BLOCK
, 0, 0, 0},
335 {R_028044_CB_COLOR1_BASE
, REG_FLAG_NEED_BO
|REG_FLAG_RV6XX_SBU
, SURFACE_BASE_UPDATE_COLOR(1), 0},
336 {GROUP_FORCE_NEW_BLOCK
, 0, 0, 0},
337 {R_0280A4_CB_COLOR1_INFO
, REG_FLAG_NEED_BO
, 0, 0xFFFFFFFF},
338 {R_028064_CB_COLOR1_SIZE
, 0, 0, 0},
339 {R_028084_CB_COLOR1_VIEW
, 0, 0, 0},
340 {GROUP_FORCE_NEW_BLOCK
, 0, 0, 0},
341 {R_0280E4_CB_COLOR1_FRAG
, REG_FLAG_NEED_BO
, 0, 0},
342 {GROUP_FORCE_NEW_BLOCK
, 0, 0, 0},
343 {R_0280C4_CB_COLOR1_TILE
, REG_FLAG_NEED_BO
, 0, 0},
344 {R_028104_CB_COLOR1_MASK
, 0, 0, 0},
345 {GROUP_FORCE_NEW_BLOCK
, 0, 0, 0},
346 {R_028048_CB_COLOR2_BASE
, REG_FLAG_NEED_BO
|REG_FLAG_RV6XX_SBU
, SURFACE_BASE_UPDATE_COLOR(2), 0},
347 {GROUP_FORCE_NEW_BLOCK
, 0, 0, 0},
348 {R_0280A8_CB_COLOR2_INFO
, REG_FLAG_NEED_BO
, 0, 0xFFFFFFFF},
349 {R_028068_CB_COLOR2_SIZE
, 0, 0, 0},
350 {R_028088_CB_COLOR2_VIEW
, 0, 0, 0},
351 {GROUP_FORCE_NEW_BLOCK
, 0, 0, 0},
352 {R_0280E8_CB_COLOR2_FRAG
, REG_FLAG_NEED_BO
, 0, 0},
353 {GROUP_FORCE_NEW_BLOCK
, 0, 0, 0},
354 {R_0280C8_CB_COLOR2_TILE
, REG_FLAG_NEED_BO
, 0, 0},
355 {R_028108_CB_COLOR2_MASK
, 0, 0, 0},
356 {GROUP_FORCE_NEW_BLOCK
, 0, 0, 0},
357 {R_02804C_CB_COLOR3_BASE
, REG_FLAG_NEED_BO
|REG_FLAG_RV6XX_SBU
, SURFACE_BASE_UPDATE_COLOR(3), 0},
358 {GROUP_FORCE_NEW_BLOCK
, 0, 0, 0},
359 {R_0280AC_CB_COLOR3_INFO
, REG_FLAG_NEED_BO
, 0, 0xFFFFFFFF},
360 {R_02806C_CB_COLOR3_SIZE
, 0, 0, 0},
361 {R_02808C_CB_COLOR3_VIEW
, 0, 0, 0},
362 {GROUP_FORCE_NEW_BLOCK
, 0, 0, 0},
363 {R_0280EC_CB_COLOR3_FRAG
, REG_FLAG_NEED_BO
, 0, 0},
364 {GROUP_FORCE_NEW_BLOCK
, 0, 0, 0},
365 {R_0280CC_CB_COLOR3_TILE
, REG_FLAG_NEED_BO
, 0, 0},
366 {R_02810C_CB_COLOR3_MASK
, 0, 0, 0},
367 {GROUP_FORCE_NEW_BLOCK
, 0, 0, 0},
368 {R_028050_CB_COLOR4_BASE
, REG_FLAG_NEED_BO
|REG_FLAG_RV6XX_SBU
, SURFACE_BASE_UPDATE_COLOR(4), 0},
369 {GROUP_FORCE_NEW_BLOCK
, 0, 0, 0},
370 {R_0280B0_CB_COLOR4_INFO
, REG_FLAG_NEED_BO
, 0, 0xFFFFFFFF},
371 {R_028070_CB_COLOR4_SIZE
, 0, 0, 0},
372 {R_028090_CB_COLOR4_VIEW
, 0, 0, 0},
373 {GROUP_FORCE_NEW_BLOCK
, 0, 0, 0},
374 {R_0280F0_CB_COLOR4_FRAG
, REG_FLAG_NEED_BO
, 0, 0},
375 {GROUP_FORCE_NEW_BLOCK
, 0, 0, 0},
376 {R_0280D0_CB_COLOR4_TILE
, REG_FLAG_NEED_BO
, 0, 0},
377 {R_028110_CB_COLOR4_MASK
, 0, 0, 0},
378 {GROUP_FORCE_NEW_BLOCK
, 0, 0, 0},
379 {R_028054_CB_COLOR5_BASE
, REG_FLAG_NEED_BO
|REG_FLAG_RV6XX_SBU
, SURFACE_BASE_UPDATE_COLOR(5), 0},
380 {GROUP_FORCE_NEW_BLOCK
, 0, 0, 0},
381 {R_0280B4_CB_COLOR5_INFO
, REG_FLAG_NEED_BO
, 0, 0xFFFFFFFF},
382 {R_028074_CB_COLOR5_SIZE
, 0, 0, 0},
383 {R_028094_CB_COLOR5_VIEW
, 0, 0, 0},
384 {GROUP_FORCE_NEW_BLOCK
, 0, 0, 0},
385 {R_0280F4_CB_COLOR5_FRAG
, REG_FLAG_NEED_BO
, 0, 0},
386 {GROUP_FORCE_NEW_BLOCK
, 0, 0, 0},
387 {R_0280D4_CB_COLOR5_TILE
, REG_FLAG_NEED_BO
, 0, 0},
388 {R_028114_CB_COLOR5_MASK
, 0, 0, 0},
389 {R_028058_CB_COLOR6_BASE
, REG_FLAG_NEED_BO
|REG_FLAG_RV6XX_SBU
, SURFACE_BASE_UPDATE_COLOR(6), 0},
390 {R_0280B8_CB_COLOR6_INFO
, REG_FLAG_NEED_BO
, 0, 0xFFFFFFFF},
391 {R_028078_CB_COLOR6_SIZE
, 0, 0, 0},
392 {R_028098_CB_COLOR6_VIEW
, 0, 0, 0},
393 {GROUP_FORCE_NEW_BLOCK
, 0, 0, 0},
394 {R_0280F8_CB_COLOR6_FRAG
, REG_FLAG_NEED_BO
, 0, 0},
395 {GROUP_FORCE_NEW_BLOCK
, 0, 0, 0},
396 {R_0280D8_CB_COLOR6_TILE
, REG_FLAG_NEED_BO
, 0, 0},
397 {R_028118_CB_COLOR6_MASK
, 0, 0, 0},
398 {GROUP_FORCE_NEW_BLOCK
, 0, 0, 0},
399 {R_02805C_CB_COLOR7_BASE
, REG_FLAG_NEED_BO
|REG_FLAG_RV6XX_SBU
, SURFACE_BASE_UPDATE_COLOR(7), 0},
400 {GROUP_FORCE_NEW_BLOCK
, 0, 0, 0},
401 {R_0280BC_CB_COLOR7_INFO
, REG_FLAG_NEED_BO
, 0, 0xFFFFFFFF},
402 {R_02807C_CB_COLOR7_SIZE
, 0, 0, 0},
403 {R_02809C_CB_COLOR7_VIEW
, 0, 0, 0},
404 {R_0280FC_CB_COLOR7_FRAG
, REG_FLAG_NEED_BO
, 0, 0},
405 {R_0280DC_CB_COLOR7_TILE
, REG_FLAG_NEED_BO
, 0, 0},
406 {R_02811C_CB_COLOR7_MASK
, 0, 0, 0},
407 {R_028120_CB_CLEAR_RED
, 0, 0, 0},
408 {R_028124_CB_CLEAR_GREEN
, 0, 0, 0},
409 {R_028128_CB_CLEAR_BLUE
, 0, 0, 0},
410 {R_02812C_CB_CLEAR_ALPHA
, 0, 0, 0},
411 {R_028140_ALU_CONST_BUFFER_SIZE_PS_0
, REG_FLAG_DIRTY_ALWAYS
, 0, 0},
412 {R_028180_ALU_CONST_BUFFER_SIZE_VS_0
, REG_FLAG_DIRTY_ALWAYS
, 0, 0},
413 {R_028940_ALU_CONST_CACHE_PS_0
, REG_FLAG_NEED_BO
, S_0085F0_SH_ACTION_ENA(1), 0xFFFFFFFF},
414 {R_028980_ALU_CONST_CACHE_VS_0
, REG_FLAG_NEED_BO
, S_0085F0_SH_ACTION_ENA(1), 0xFFFFFFFF},
415 {R_02823C_CB_SHADER_MASK
, 0, 0, 0},
416 {R_028238_CB_TARGET_MASK
, 0, 0, 0},
417 {R_028410_SX_ALPHA_TEST_CONTROL
, 0, 0, 0},
418 {R_028414_CB_BLEND_RED
, 0, 0, 0},
419 {R_028418_CB_BLEND_GREEN
, 0, 0, 0},
420 {R_02841C_CB_BLEND_BLUE
, 0, 0, 0},
421 {R_028420_CB_BLEND_ALPHA
, 0, 0, 0},
422 {R_028424_CB_FOG_RED
, 0, 0, 0},
423 {R_028428_CB_FOG_GREEN
, 0, 0, 0},
424 {R_02842C_CB_FOG_BLUE
, 0, 0, 0},
425 {R_028430_DB_STENCILREFMASK
, 0, 0, 0},
426 {R_028434_DB_STENCILREFMASK_BF
, 0, 0, 0},
427 {R_028438_SX_ALPHA_REF
, 0, 0, 0},
428 {R_0286DC_SPI_FOG_CNTL
, 0, 0, 0},
429 {R_0286E0_SPI_FOG_FUNC_SCALE
, 0, 0, 0},
430 {R_0286E4_SPI_FOG_FUNC_BIAS
, 0, 0, 0},
431 {R_028780_CB_BLEND0_CONTROL
, REG_FLAG_NOT_R600
, 0, 0},
432 {R_028784_CB_BLEND1_CONTROL
, REG_FLAG_NOT_R600
, 0, 0},
433 {R_028788_CB_BLEND2_CONTROL
, REG_FLAG_NOT_R600
, 0, 0},
434 {R_02878C_CB_BLEND3_CONTROL
, REG_FLAG_NOT_R600
, 0, 0},
435 {R_028790_CB_BLEND4_CONTROL
, REG_FLAG_NOT_R600
, 0, 0},
436 {R_028794_CB_BLEND5_CONTROL
, REG_FLAG_NOT_R600
, 0, 0},
437 {R_028798_CB_BLEND6_CONTROL
, REG_FLAG_NOT_R600
, 0, 0},
438 {R_02879C_CB_BLEND7_CONTROL
, REG_FLAG_NOT_R600
, 0, 0},
439 {R_0287A0_CB_SHADER_CONTROL
, 0, 0, 0},
440 {R_028800_DB_DEPTH_CONTROL
, 0, 0, 0},
441 {R_028804_CB_BLEND_CONTROL
, 0, 0, 0},
442 {R_028808_CB_COLOR_CONTROL
, 0, 0, 0},
443 {R_02880C_DB_SHADER_CONTROL
, 0, 0, 0},
444 {R_028C04_PA_SC_AA_CONFIG
, 0, 0, 0},
445 {R_028C1C_PA_SC_AA_SAMPLE_LOCS_MCTX
, 0, 0, 0},
446 {R_028C20_PA_SC_AA_SAMPLE_LOCS_8S_WD1_MCTX
, 0, 0, 0},
447 {R_028C30_CB_CLRCMP_CONTROL
, 0, 0, 0},
448 {R_028C34_CB_CLRCMP_SRC
, 0, 0, 0},
449 {R_028C38_CB_CLRCMP_DST
, 0, 0, 0},
450 {R_028C3C_CB_CLRCMP_MSK
, 0, 0, 0},
451 {R_028C48_PA_SC_AA_MASK
, 0, 0, 0},
452 {R_028D2C_DB_SRESULTS_COMPARE_STATE1
, 0, 0, 0},
453 {R_028D44_DB_ALPHA_TO_MASK
, 0, 0, 0},
454 {R_02800C_DB_DEPTH_BASE
, REG_FLAG_NEED_BO
|REG_FLAG_RV6XX_SBU
, SURFACE_BASE_UPDATE_DEPTH
, 0},
455 {R_028000_DB_DEPTH_SIZE
, 0, 0, 0},
456 {R_028004_DB_DEPTH_VIEW
, 0, 0, 0},
457 {GROUP_FORCE_NEW_BLOCK
, 0, 0, 0},
458 {R_028010_DB_DEPTH_INFO
, REG_FLAG_NEED_BO
, 0, 0},
459 {R_028D0C_DB_RENDER_CONTROL
, 0, 0, 0},
460 {R_028D10_DB_RENDER_OVERRIDE
, 0, 0, 0},
461 {R_028D24_DB_HTILE_SURFACE
, 0, 0, 0},
462 {R_028D30_DB_PRELOAD_CONTROL
, 0, 0, 0},
463 {R_028D34_DB_PREFETCH_LIMIT
, 0, 0, 0},
464 {R_028030_PA_SC_SCREEN_SCISSOR_TL
, 0, 0, 0},
465 {R_028034_PA_SC_SCREEN_SCISSOR_BR
, 0, 0, 0},
466 {R_028200_PA_SC_WINDOW_OFFSET
, 0, 0, 0},
467 {R_028204_PA_SC_WINDOW_SCISSOR_TL
, 0, 0, 0},
468 {R_028208_PA_SC_WINDOW_SCISSOR_BR
, 0, 0, 0},
469 {R_02820C_PA_SC_CLIPRECT_RULE
, 0, 0, 0},
470 {R_028210_PA_SC_CLIPRECT_0_TL
, 0, 0, 0},
471 {R_028214_PA_SC_CLIPRECT_0_BR
, 0, 0, 0},
472 {R_028218_PA_SC_CLIPRECT_1_TL
, 0, 0, 0},
473 {R_02821C_PA_SC_CLIPRECT_1_BR
, 0, 0, 0},
474 {R_028220_PA_SC_CLIPRECT_2_TL
, 0, 0, 0},
475 {R_028224_PA_SC_CLIPRECT_2_BR
, 0, 0, 0},
476 {R_028228_PA_SC_CLIPRECT_3_TL
, 0, 0, 0},
477 {R_02822C_PA_SC_CLIPRECT_3_BR
, 0, 0, 0},
478 {R_028230_PA_SC_EDGERULE
, 0, 0, 0},
479 {R_028240_PA_SC_GENERIC_SCISSOR_TL
, 0, 0, 0},
480 {R_028244_PA_SC_GENERIC_SCISSOR_BR
, 0, 0, 0},
481 {R_028250_PA_SC_VPORT_SCISSOR_0_TL
, 0, 0, 0},
482 {R_028254_PA_SC_VPORT_SCISSOR_0_BR
, 0, 0, 0},
483 {R_0282D0_PA_SC_VPORT_ZMIN_0
, 0, 0, 0},
484 {R_0282D4_PA_SC_VPORT_ZMAX_0
, 0, 0, 0},
485 {R_02843C_PA_CL_VPORT_XSCALE_0
, 0, 0, 0},
486 {R_028440_PA_CL_VPORT_XOFFSET_0
, 0, 0, 0},
487 {R_028444_PA_CL_VPORT_YSCALE_0
, 0, 0, 0},
488 {R_028448_PA_CL_VPORT_YOFFSET_0
, 0, 0, 0},
489 {R_02844C_PA_CL_VPORT_ZSCALE_0
, 0, 0, 0},
490 {R_028450_PA_CL_VPORT_ZOFFSET_0
, 0, 0, 0},
491 {R_0286D4_SPI_INTERP_CONTROL_0
, 0, 0, 0},
492 {R_028810_PA_CL_CLIP_CNTL
, 0, 0, 0},
493 {R_028814_PA_SU_SC_MODE_CNTL
, 0, 0, 0},
494 {R_028818_PA_CL_VTE_CNTL
, 0, 0, 0},
495 {R_02881C_PA_CL_VS_OUT_CNTL
, 0, 0, 0},
496 {R_028820_PA_CL_NANINF_CNTL
, 0, 0, 0},
497 {R_028A00_PA_SU_POINT_SIZE
, 0, 0, 0},
498 {R_028A04_PA_SU_POINT_MINMAX
, 0, 0, 0},
499 {R_028A08_PA_SU_LINE_CNTL
, 0, 0, 0},
500 {R_028A0C_PA_SC_LINE_STIPPLE
, 0, 0, 0},
501 {R_028A48_PA_SC_MPASS_PS_CNTL
, 0, 0, 0},
502 {R_028C00_PA_SC_LINE_CNTL
, 0, 0, 0},
503 {R_028C08_PA_SU_VTX_CNTL
, 0, 0, 0},
504 {R_028C0C_PA_CL_GB_VERT_CLIP_ADJ
, 0, 0, 0},
505 {R_028C10_PA_CL_GB_VERT_DISC_ADJ
, 0, 0, 0},
506 {R_028C14_PA_CL_GB_HORZ_CLIP_ADJ
, 0, 0, 0},
507 {R_028C18_PA_CL_GB_HORZ_DISC_ADJ
, 0, 0, 0},
508 {R_028DF8_PA_SU_POLY_OFFSET_DB_FMT_CNTL
, 0, 0, 0},
509 {R_028DFC_PA_SU_POLY_OFFSET_CLAMP
, 0, 0, 0},
510 {R_028E00_PA_SU_POLY_OFFSET_FRONT_SCALE
, 0, 0, 0},
511 {R_028E04_PA_SU_POLY_OFFSET_FRONT_OFFSET
, 0, 0, 0},
512 {R_028E08_PA_SU_POLY_OFFSET_BACK_SCALE
, 0, 0, 0},
513 {R_028E0C_PA_SU_POLY_OFFSET_BACK_OFFSET
, 0, 0, 0},
514 {R_028E20_PA_CL_UCP0_X
, 0, 0, 0},
515 {R_028E24_PA_CL_UCP0_Y
, 0, 0, 0},
516 {R_028E28_PA_CL_UCP0_Z
, 0, 0, 0},
517 {R_028E2C_PA_CL_UCP0_W
, 0, 0, 0},
518 {R_028E30_PA_CL_UCP1_X
, 0, 0, 0},
519 {R_028E34_PA_CL_UCP1_Y
, 0, 0, 0},
520 {R_028E38_PA_CL_UCP1_Z
, 0, 0, 0},
521 {R_028E3C_PA_CL_UCP1_W
, 0, 0, 0},
522 {R_028E40_PA_CL_UCP2_X
, 0, 0, 0},
523 {R_028E44_PA_CL_UCP2_Y
, 0, 0, 0},
524 {R_028E48_PA_CL_UCP2_Z
, 0, 0, 0},
525 {R_028E4C_PA_CL_UCP2_W
, 0, 0, 0},
526 {R_028E50_PA_CL_UCP3_X
, 0, 0, 0},
527 {R_028E54_PA_CL_UCP3_Y
, 0, 0, 0},
528 {R_028E58_PA_CL_UCP3_Z
, 0, 0, 0},
529 {R_028E5C_PA_CL_UCP3_W
, 0, 0, 0},
530 {R_028E60_PA_CL_UCP4_X
, 0, 0, 0},
531 {R_028E64_PA_CL_UCP4_Y
, 0, 0, 0},
532 {R_028E68_PA_CL_UCP4_Z
, 0, 0, 0},
533 {R_028E6C_PA_CL_UCP4_W
, 0, 0, 0},
534 {R_028E70_PA_CL_UCP5_X
, 0, 0, 0},
535 {R_028E74_PA_CL_UCP5_Y
, 0, 0, 0},
536 {R_028E78_PA_CL_UCP5_Z
, 0, 0, 0},
537 {R_028E7C_PA_CL_UCP5_W
, 0, 0, 0},
538 {R_028380_SQ_VTX_SEMANTIC_0
, 0, 0, 0},
539 {R_028384_SQ_VTX_SEMANTIC_1
, 0, 0, 0},
540 {R_028388_SQ_VTX_SEMANTIC_2
, 0, 0, 0},
541 {R_02838C_SQ_VTX_SEMANTIC_3
, 0, 0, 0},
542 {R_028390_SQ_VTX_SEMANTIC_4
, 0, 0, 0},
543 {R_028394_SQ_VTX_SEMANTIC_5
, 0, 0, 0},
544 {R_028398_SQ_VTX_SEMANTIC_6
, 0, 0, 0},
545 {R_02839C_SQ_VTX_SEMANTIC_7
, 0, 0, 0},
546 {R_0283A0_SQ_VTX_SEMANTIC_8
, 0, 0, 0},
547 {R_0283A4_SQ_VTX_SEMANTIC_9
, 0, 0, 0},
548 {R_0283A8_SQ_VTX_SEMANTIC_10
, 0, 0, 0},
549 {R_0283AC_SQ_VTX_SEMANTIC_11
, 0, 0, 0},
550 {R_0283B0_SQ_VTX_SEMANTIC_12
, 0, 0, 0},
551 {R_0283B4_SQ_VTX_SEMANTIC_13
, 0, 0, 0},
552 {R_0283B8_SQ_VTX_SEMANTIC_14
, 0, 0, 0},
553 {R_0283BC_SQ_VTX_SEMANTIC_15
, 0, 0, 0},
554 {R_0283C0_SQ_VTX_SEMANTIC_16
, 0, 0, 0},
555 {R_0283C4_SQ_VTX_SEMANTIC_17
, 0, 0, 0},
556 {R_0283C8_SQ_VTX_SEMANTIC_18
, 0, 0, 0},
557 {R_0283CC_SQ_VTX_SEMANTIC_19
, 0, 0, 0},
558 {R_0283D0_SQ_VTX_SEMANTIC_20
, 0, 0, 0},
559 {R_0283D4_SQ_VTX_SEMANTIC_21
, 0, 0, 0},
560 {R_0283D8_SQ_VTX_SEMANTIC_22
, 0, 0, 0},
561 {R_0283DC_SQ_VTX_SEMANTIC_23
, 0, 0, 0},
562 {R_0283E0_SQ_VTX_SEMANTIC_24
, 0, 0, 0},
563 {R_0283E4_SQ_VTX_SEMANTIC_25
, 0, 0, 0},
564 {R_0283E8_SQ_VTX_SEMANTIC_26
, 0, 0, 0},
565 {R_0283EC_SQ_VTX_SEMANTIC_27
, 0, 0, 0},
566 {R_0283F0_SQ_VTX_SEMANTIC_28
, 0, 0, 0},
567 {R_0283F4_SQ_VTX_SEMANTIC_29
, 0, 0, 0},
568 {R_0283F8_SQ_VTX_SEMANTIC_30
, 0, 0, 0},
569 {R_0283FC_SQ_VTX_SEMANTIC_31
, 0, 0, 0},
570 {R_028614_SPI_VS_OUT_ID_0
, 0, 0, 0},
571 {R_028618_SPI_VS_OUT_ID_1
, 0, 0, 0},
572 {R_02861C_SPI_VS_OUT_ID_2
, 0, 0, 0},
573 {R_028620_SPI_VS_OUT_ID_3
, 0, 0, 0},
574 {R_028624_SPI_VS_OUT_ID_4
, 0, 0, 0},
575 {R_028628_SPI_VS_OUT_ID_5
, 0, 0, 0},
576 {R_02862C_SPI_VS_OUT_ID_6
, 0, 0, 0},
577 {R_028630_SPI_VS_OUT_ID_7
, 0, 0, 0},
578 {R_028634_SPI_VS_OUT_ID_8
, 0, 0, 0},
579 {R_028638_SPI_VS_OUT_ID_9
, 0, 0, 0},
580 {R_0286C4_SPI_VS_OUT_CONFIG
, 0, 0, 0},
581 {GROUP_FORCE_NEW_BLOCK
, 0, 0, 0},
582 {R_028858_SQ_PGM_START_VS
, REG_FLAG_NEED_BO
, S_0085F0_SH_ACTION_ENA(1), 0xFFFFFFFF},
583 {GROUP_FORCE_NEW_BLOCK
, 0, 0, 0},
584 {R_028868_SQ_PGM_RESOURCES_VS
, 0, 0, 0},
585 {GROUP_FORCE_NEW_BLOCK
, 0, 0, 0},
586 {R_028894_SQ_PGM_START_FS
, REG_FLAG_NEED_BO
, S_0085F0_SH_ACTION_ENA(1), 0xFFFFFFFF},
587 {GROUP_FORCE_NEW_BLOCK
, 0, 0, 0},
588 {R_0288A4_SQ_PGM_RESOURCES_FS
, 0, 0, 0},
589 {R_0288D0_SQ_PGM_CF_OFFSET_VS
, 0, 0, 0},
590 {R_0288DC_SQ_PGM_CF_OFFSET_FS
, 0, 0, 0},
591 {R_028644_SPI_PS_INPUT_CNTL_0
, 0, 0, 0},
592 {R_028648_SPI_PS_INPUT_CNTL_1
, 0, 0, 0},
593 {R_02864C_SPI_PS_INPUT_CNTL_2
, 0, 0, 0},
594 {R_028650_SPI_PS_INPUT_CNTL_3
, 0, 0, 0},
595 {R_028654_SPI_PS_INPUT_CNTL_4
, 0, 0, 0},
596 {R_028658_SPI_PS_INPUT_CNTL_5
, 0, 0, 0},
597 {R_02865C_SPI_PS_INPUT_CNTL_6
, 0, 0, 0},
598 {R_028660_SPI_PS_INPUT_CNTL_7
, 0, 0, 0},
599 {R_028664_SPI_PS_INPUT_CNTL_8
, 0, 0, 0},
600 {R_028668_SPI_PS_INPUT_CNTL_9
, 0, 0, 0},
601 {R_02866C_SPI_PS_INPUT_CNTL_10
, 0, 0, 0},
602 {R_028670_SPI_PS_INPUT_CNTL_11
, 0, 0, 0},
603 {R_028674_SPI_PS_INPUT_CNTL_12
, 0, 0, 0},
604 {R_028678_SPI_PS_INPUT_CNTL_13
, 0, 0, 0},
605 {R_02867C_SPI_PS_INPUT_CNTL_14
, 0, 0, 0},
606 {R_028680_SPI_PS_INPUT_CNTL_15
, 0, 0, 0},
607 {R_028684_SPI_PS_INPUT_CNTL_16
, 0, 0, 0},
608 {R_028688_SPI_PS_INPUT_CNTL_17
, 0, 0, 0},
609 {R_02868C_SPI_PS_INPUT_CNTL_18
, 0, 0, 0},
610 {R_028690_SPI_PS_INPUT_CNTL_19
, 0, 0, 0},
611 {R_028694_SPI_PS_INPUT_CNTL_20
, 0, 0, 0},
612 {R_028698_SPI_PS_INPUT_CNTL_21
, 0, 0, 0},
613 {R_02869C_SPI_PS_INPUT_CNTL_22
, 0, 0, 0},
614 {R_0286A0_SPI_PS_INPUT_CNTL_23
, 0, 0, 0},
615 {R_0286A4_SPI_PS_INPUT_CNTL_24
, 0, 0, 0},
616 {R_0286A8_SPI_PS_INPUT_CNTL_25
, 0, 0, 0},
617 {R_0286AC_SPI_PS_INPUT_CNTL_26
, 0, 0, 0},
618 {R_0286B0_SPI_PS_INPUT_CNTL_27
, 0, 0, 0},
619 {R_0286B4_SPI_PS_INPUT_CNTL_28
, 0, 0, 0},
620 {R_0286B8_SPI_PS_INPUT_CNTL_29
, 0, 0, 0},
621 {R_0286BC_SPI_PS_INPUT_CNTL_30
, 0, 0, 0},
622 {R_0286C0_SPI_PS_INPUT_CNTL_31
, 0, 0, 0},
623 {R_0286CC_SPI_PS_IN_CONTROL_0
, 0, 0, 0},
624 {R_0286D0_SPI_PS_IN_CONTROL_1
, 0, 0, 0},
625 {R_0286D8_SPI_INPUT_Z
, 0, 0, 0},
626 {GROUP_FORCE_NEW_BLOCK
, 0, 0, 0},
627 {R_028840_SQ_PGM_START_PS
, REG_FLAG_NEED_BO
, S_0085F0_SH_ACTION_ENA(1), 0xFFFFFFFF},
628 {GROUP_FORCE_NEW_BLOCK
, 0, 0, 0},
629 {R_028850_SQ_PGM_RESOURCES_PS
, 0, 0, 0},
630 {R_028854_SQ_PGM_EXPORTS_PS
, 0, 0, 0},
631 {R_0288CC_SQ_PGM_CF_OFFSET_PS
, 0, 0, 0},
632 {R_028400_VGT_MAX_VTX_INDX
, 0, 0, 0},
633 {R_028404_VGT_MIN_VTX_INDX
, 0, 0, 0},
634 {R_028408_VGT_INDX_OFFSET
, 0, 0, 0},
635 {R_02840C_VGT_MULTI_PRIM_IB_RESET_INDX
, 0, 0, 0},
636 {R_028A84_VGT_PRIMITIVEID_EN
, 0, 0, 0},
637 {R_028A94_VGT_MULTI_PRIM_IB_RESET_EN
, 0, 0, 0},
638 {R_028AA0_VGT_INSTANCE_STEP_RATE_0
, 0, 0, 0},
639 {R_028AA4_VGT_INSTANCE_STEP_RATE_1
, 0, 0, 0},
642 /* SHADER RESOURCE R600/R700 */
643 int r600_resource_init(struct r600_context
*ctx
, struct r600_range
*range
, unsigned offset
, unsigned nblocks
, unsigned stride
, struct r600_reg
*reg
, int nreg
, unsigned offset_base
)
646 struct r600_block
*block
;
647 range
->blocks
= calloc(nblocks
, sizeof(struct r600_block
*));
648 if (range
->blocks
== NULL
)
651 reg
[0].offset
+= offset
;
652 for (i
= 0; i
< nblocks
; i
++) {
653 block
= calloc(1, sizeof(struct r600_block
));
658 range
->blocks
[i
] = block
;
659 r600_init_block(ctx
, block
, reg
, 0, nreg
, PKT3_SET_RESOURCE
, offset_base
);
661 reg
[0].offset
+= stride
;
667 static int r600_resource_range_init(struct r600_context
*ctx
, struct r600_range
*range
, unsigned offset
, unsigned nblocks
, unsigned stride
)
669 struct r600_reg r600_shader_resource
[] = {
670 {R_038000_RESOURCE0_WORD0
, REG_FLAG_NEED_BO
, S_0085F0_TC_ACTION_ENA(1) | S_0085F0_VC_ACTION_ENA(1), 0xFFFFFFFF},
671 {R_038004_RESOURCE0_WORD1
, REG_FLAG_NEED_BO
, S_0085F0_TC_ACTION_ENA(1) | S_0085F0_VC_ACTION_ENA(1), 0xFFFFFFFF},
672 {R_038008_RESOURCE0_WORD2
, 0, 0, 0},
673 {R_03800C_RESOURCE0_WORD3
, 0, 0, 0},
674 {R_038010_RESOURCE0_WORD4
, 0, 0, 0},
675 {R_038014_RESOURCE0_WORD5
, 0, 0, 0},
676 {R_038018_RESOURCE0_WORD6
, 0, 0, 0},
678 unsigned nreg
= Elements(r600_shader_resource
);
680 return r600_resource_init(ctx
, range
, offset
, nblocks
, stride
, r600_shader_resource
, nreg
, R600_RESOURCE_OFFSET
);
683 /* SHADER SAMPLER R600/R700 */
684 static int r600_state_sampler_init(struct r600_context
*ctx
, u32 offset
)
686 struct r600_reg r600_shader_sampler
[] = {
687 {R_03C000_SQ_TEX_SAMPLER_WORD0_0
, 0, 0, 0},
688 {R_03C004_SQ_TEX_SAMPLER_WORD1_0
, 0, 0, 0},
689 {R_03C008_SQ_TEX_SAMPLER_WORD2_0
, 0, 0, 0},
691 unsigned nreg
= Elements(r600_shader_sampler
);
693 for (int i
= 0; i
< nreg
; i
++) {
694 r600_shader_sampler
[i
].offset
+= offset
;
696 return r600_context_add_block(ctx
, r600_shader_sampler
, nreg
, PKT3_SET_SAMPLER
, R600_SAMPLER_OFFSET
);
699 /* SHADER SAMPLER BORDER R600/R700 */
700 static int r600_state_sampler_border_init(struct r600_context
*ctx
, u32 offset
)
702 struct r600_reg r600_shader_sampler_border
[] = {
703 {R_00A400_TD_PS_SAMPLER0_BORDER_RED
, 0, 0, 0},
704 {R_00A404_TD_PS_SAMPLER0_BORDER_GREEN
, 0, 0, 0},
705 {R_00A408_TD_PS_SAMPLER0_BORDER_BLUE
, 0, 0, 0},
706 {R_00A40C_TD_PS_SAMPLER0_BORDER_ALPHA
, 0, 0, 0},
708 unsigned nreg
= Elements(r600_shader_sampler_border
);
710 for (int i
= 0; i
< nreg
; i
++) {
711 r600_shader_sampler_border
[i
].offset
+= offset
;
713 return r600_context_add_block(ctx
, r600_shader_sampler_border
, nreg
, PKT3_SET_CONFIG_REG
, R600_CONFIG_REG_OFFSET
);
716 static int r600_loop_const_init(struct r600_context
*ctx
, u32 offset
)
719 struct r600_reg r600_loop_consts
[32];
722 for (i
= 0; i
< nreg
; i
++) {
723 r600_loop_consts
[i
].offset
= R600_LOOP_CONST_OFFSET
+ ((offset
+ i
) * 4);
724 r600_loop_consts
[i
].flags
= REG_FLAG_DIRTY_ALWAYS
;
725 r600_loop_consts
[i
].flush_flags
= 0;
726 r600_loop_consts
[i
].flush_mask
= 0;
728 return r600_context_add_block(ctx
, r600_loop_consts
, nreg
, PKT3_SET_LOOP_CONST
, R600_LOOP_CONST_OFFSET
);
731 static void r600_free_resource_range(struct r600_context
*ctx
, struct r600_range
*range
, int nblocks
)
733 struct r600_block
*block
;
735 for (i
= 0; i
< nblocks
; i
++) {
736 block
= range
->blocks
[i
];
738 for (int k
= 1; k
<= block
->nbo
; k
++)
739 r600_bo_reference(&block
->reloc
[k
].bo
, NULL
);
748 void r600_context_fini(struct r600_context
*ctx
)
750 struct r600_block
*block
;
751 struct r600_range
*range
;
753 for (int i
= 0; i
< NUM_RANGES
; i
++) {
754 if (!ctx
->range
[i
].blocks
)
756 for (int j
= 0; j
< (1 << HASH_SHIFT
); j
++) {
757 block
= ctx
->range
[i
].blocks
[j
];
759 for (int k
= 0, offset
= block
->start_offset
; k
< block
->nreg
; k
++, offset
+= 4) {
760 range
= &ctx
->range
[CTX_RANGE_ID(offset
)];
761 range
->blocks
[CTX_BLOCK_ID(offset
)] = NULL
;
763 for (int k
= 1; k
<= block
->nbo
; k
++) {
764 r600_bo_reference(&block
->reloc
[k
].bo
, NULL
);
769 free(ctx
->range
[i
].blocks
);
771 r600_free_resource_range(ctx
, &ctx
->ps_resources
, ctx
->num_ps_resources
);
772 r600_free_resource_range(ctx
, &ctx
->vs_resources
, ctx
->num_vs_resources
);
773 r600_free_resource_range(ctx
, &ctx
->fs_resources
, ctx
->num_fs_resources
);
777 ctx
->radeon
->ws
->cs_destroy(ctx
->cs
);
779 memset(ctx
, 0, sizeof(struct r600_context
));
782 static void r600_add_resource_block(struct r600_context
*ctx
, struct r600_range
*range
, int num_blocks
, int *index
)
785 for (int j
= 0; j
< num_blocks
; j
++) {
786 if (!range
->blocks
[j
])
789 ctx
->blocks
[c
++] = range
->blocks
[j
];
794 int r600_setup_block_table(struct r600_context
*ctx
)
796 /* setup block table */
798 ctx
->blocks
= calloc(ctx
->nblocks
, sizeof(void*));
801 for (int i
= 0; i
< NUM_RANGES
; i
++) {
802 if (!ctx
->range
[i
].blocks
)
804 for (int j
= 0, add
; j
< (1 << HASH_SHIFT
); j
++) {
805 if (!ctx
->range
[i
].blocks
[j
])
809 for (int k
= 0; k
< c
; k
++) {
810 if (ctx
->blocks
[k
] == ctx
->range
[i
].blocks
[j
]) {
816 assert(c
< ctx
->nblocks
);
817 ctx
->blocks
[c
++] = ctx
->range
[i
].blocks
[j
];
818 j
+= (ctx
->range
[i
].blocks
[j
]->nreg
) - 1;
823 r600_add_resource_block(ctx
, &ctx
->ps_resources
, ctx
->num_ps_resources
, &c
);
824 r600_add_resource_block(ctx
, &ctx
->vs_resources
, ctx
->num_vs_resources
, &c
);
825 r600_add_resource_block(ctx
, &ctx
->fs_resources
, ctx
->num_fs_resources
, &c
);
829 int r600_context_init(struct r600_context
*ctx
, struct radeon
*radeon
)
833 memset(ctx
, 0, sizeof(struct r600_context
));
834 ctx
->radeon
= radeon
;
836 LIST_INITHEAD(&ctx
->query_list
);
838 /* init dirty list */
839 LIST_INITHEAD(&ctx
->dirty
);
840 LIST_INITHEAD(&ctx
->resource_dirty
);
841 LIST_INITHEAD(&ctx
->enable_list
);
843 ctx
->range
= calloc(NUM_RANGES
, sizeof(struct r600_range
));
850 r
= r600_context_add_block(ctx
, r600_config_reg_list
,
851 Elements(r600_config_reg_list
), PKT3_SET_CONFIG_REG
, R600_CONFIG_REG_OFFSET
);
854 r
= r600_context_add_block(ctx
, r600_context_reg_list
,
855 Elements(r600_context_reg_list
), PKT3_SET_CONTEXT_REG
, R600_CONTEXT_REG_OFFSET
);
858 r
= r600_context_add_block(ctx
, r600_ctl_const_list
,
859 Elements(r600_ctl_const_list
), PKT3_SET_CTL_CONST
, R600_CTL_CONST_OFFSET
);
863 /* PS SAMPLER BORDER */
864 for (int j
= 0, offset
= 0; j
< 18; j
++, offset
+= 0x10) {
865 r
= r600_state_sampler_border_init(ctx
, offset
);
870 /* VS SAMPLER BORDER */
871 for (int j
= 0, offset
= 0x200; j
< 18; j
++, offset
+= 0x10) {
872 r
= r600_state_sampler_border_init(ctx
, offset
);
877 for (int j
= 0, offset
= 0; j
< 18; j
++, offset
+= 0xC) {
878 r
= r600_state_sampler_init(ctx
, offset
);
883 for (int j
= 0, offset
= 0xD8; j
< 18; j
++, offset
+= 0xC) {
884 r
= r600_state_sampler_init(ctx
, offset
);
889 ctx
->num_ps_resources
= 160;
890 ctx
->num_vs_resources
= 160;
891 ctx
->num_fs_resources
= 16;
892 r
= r600_resource_range_init(ctx
, &ctx
->ps_resources
, 0, 160, 0x1c);
895 r
= r600_resource_range_init(ctx
, &ctx
->vs_resources
, 0x1180, 160, 0x1c);
898 r
= r600_resource_range_init(ctx
, &ctx
->fs_resources
, 0x2300, 16, 0x1c);
903 r600_loop_const_init(ctx
, 0);
905 r600_loop_const_init(ctx
, 32);
907 r
= r600_setup_block_table(ctx
);
911 ctx
->cs
= radeon
->ws
->cs_create(radeon
->ws
);
913 /* allocate cs variables */
914 ctx
->bo
= calloc(RADEON_MAX_CMDBUF_DWORDS
, sizeof(void *));
915 if (ctx
->bo
== NULL
) {
919 ctx
->pm4_ndwords
= RADEON_MAX_CMDBUF_DWORDS
;
920 ctx
->pm4
= ctx
->cs
->buf
;
923 /* save 16dwords space for fence mecanism */
924 ctx
->pm4_ndwords
-= 16;
927 r600_get_backend_mask(ctx
);
930 r600_context_fini(ctx
);
934 /* Flushes all surfaces */
935 void r600_context_flush_all(struct r600_context
*ctx
, unsigned flush_flags
)
937 unsigned ndwords
= 5;
939 if ((ctx
->pm4_dirty_cdwords
+ ndwords
+ ctx
->pm4_cdwords
) > ctx
->pm4_ndwords
) {
941 r600_context_flush(ctx
, RADEON_FLUSH_ASYNC
);
944 ctx
->pm4
[ctx
->pm4_cdwords
++] = PKT3(PKT3_SURFACE_SYNC
, 3, ctx
->predicate_drawing
);
945 ctx
->pm4
[ctx
->pm4_cdwords
++] = flush_flags
; /* CP_COHER_CNTL */
946 ctx
->pm4
[ctx
->pm4_cdwords
++] = 0xffffffff; /* CP_COHER_SIZE */
947 ctx
->pm4
[ctx
->pm4_cdwords
++] = 0; /* CP_COHER_BASE */
948 ctx
->pm4
[ctx
->pm4_cdwords
++] = 0x0000000A; /* POLL_INTERVAL */
951 void r600_context_bo_flush(struct r600_context
*ctx
, unsigned flush_flags
,
952 unsigned flush_mask
, struct r600_bo
*bo
)
954 /* if bo has already been flushed */
955 if (!(~bo
->last_flush
& flush_flags
)) {
956 bo
->last_flush
&= flush_mask
;
960 if ((ctx
->radeon
->family
< CHIP_RV770
) &&
961 (G_0085F0_CB_ACTION_ENA(flush_flags
) ||
962 G_0085F0_DB_ACTION_ENA(flush_flags
))) {
963 if (ctx
->flags
& R600_CONTEXT_CHECK_EVENT_FLUSH
) {
964 /* the rv670 seems to fail fbo-generatemipmap unless we flush the CB1 dest base ena */
965 if ((bo
->binding
& BO_BOUND_TEXTURE
) &&
966 (flush_flags
& S_0085F0_CB_ACTION_ENA(1))) {
967 if ((ctx
->radeon
->family
== CHIP_RV670
) ||
968 (ctx
->radeon
->family
== CHIP_RS780
) ||
969 (ctx
->radeon
->family
== CHIP_RS880
)) {
970 ctx
->pm4
[ctx
->pm4_cdwords
++] = PKT3(PKT3_SURFACE_SYNC
, 3, ctx
->predicate_drawing
);
971 ctx
->pm4
[ctx
->pm4_cdwords
++] = S_0085F0_CB1_DEST_BASE_ENA(1); /* CP_COHER_CNTL */
972 ctx
->pm4
[ctx
->pm4_cdwords
++] = 0xffffffff; /* CP_COHER_SIZE */
973 ctx
->pm4
[ctx
->pm4_cdwords
++] = 0; /* CP_COHER_BASE */
974 ctx
->pm4
[ctx
->pm4_cdwords
++] = 0x0000000A; /* POLL_INTERVAL */
978 ctx
->pm4
[ctx
->pm4_cdwords
++] = PKT3(PKT3_EVENT_WRITE
, 0, ctx
->predicate_drawing
);
979 ctx
->pm4
[ctx
->pm4_cdwords
++] = EVENT_TYPE(EVENT_TYPE_CACHE_FLUSH_AND_INV_EVENT
) | EVENT_INDEX(0);
980 ctx
->flags
&= ~R600_CONTEXT_CHECK_EVENT_FLUSH
;
983 ctx
->pm4
[ctx
->pm4_cdwords
++] = PKT3(PKT3_SURFACE_SYNC
, 3, ctx
->predicate_drawing
);
984 ctx
->pm4
[ctx
->pm4_cdwords
++] = flush_flags
;
985 ctx
->pm4
[ctx
->pm4_cdwords
++] = (bo
->buf
->size
+ 255) >> 8;
986 ctx
->pm4
[ctx
->pm4_cdwords
++] = 0x00000000;
987 ctx
->pm4
[ctx
->pm4_cdwords
++] = 0x0000000A;
988 ctx
->pm4
[ctx
->pm4_cdwords
++] = PKT3(PKT3_NOP
, 0, ctx
->predicate_drawing
);
989 ctx
->pm4
[ctx
->pm4_cdwords
++] = r600_context_bo_reloc(ctx
, bo
, RADEON_USAGE_WRITE
);
991 bo
->last_flush
= (bo
->last_flush
| flush_flags
) & flush_mask
;
994 void r600_context_reg(struct r600_context
*ctx
,
995 unsigned offset
, unsigned value
,
998 struct r600_range
*range
;
999 struct r600_block
*block
;
1004 range
= &ctx
->range
[CTX_RANGE_ID(offset
)];
1005 block
= range
->blocks
[CTX_BLOCK_ID(offset
)];
1006 id
= (offset
- block
->start_offset
) >> 2;
1008 dirty
= block
->status
& R600_BLOCK_STATUS_DIRTY
;
1010 new_val
= block
->reg
[id
];
1013 if (new_val
!= block
->reg
[id
]) {
1014 dirty
|= R600_BLOCK_STATUS_DIRTY
;
1015 block
->reg
[id
] = new_val
;
1018 r600_context_dirty_block(ctx
, block
, dirty
, id
);
1021 void r600_context_dirty_block(struct r600_context
*ctx
,
1022 struct r600_block
*block
,
1023 int dirty
, int index
)
1025 if ((index
+ 1) > block
->nreg_dirty
)
1026 block
->nreg_dirty
= index
+ 1;
1028 if ((dirty
!= (block
->status
& R600_BLOCK_STATUS_DIRTY
)) || !(block
->status
& R600_BLOCK_STATUS_ENABLED
)) {
1029 block
->status
|= R600_BLOCK_STATUS_DIRTY
;
1030 ctx
->pm4_dirty_cdwords
+= block
->pm4_ndwords
+ block
->pm4_flush_ndwords
;
1031 if (!(block
->status
& R600_BLOCK_STATUS_ENABLED
)) {
1032 block
->status
|= R600_BLOCK_STATUS_ENABLED
;
1033 LIST_ADDTAIL(&block
->enable_list
, &ctx
->enable_list
);
1035 LIST_ADDTAIL(&block
->list
,&ctx
->dirty
);
1037 if (block
->flags
& REG_FLAG_FLUSH_CHANGE
) {
1038 r600_context_ps_partial_flush(ctx
);
1043 void r600_context_pipe_state_set(struct r600_context
*ctx
, struct r600_pipe_state
*state
)
1045 struct r600_block
*block
;
1048 for (int i
= 0; i
< state
->nregs
; i
++) {
1049 unsigned id
, reloc_id
;
1050 struct r600_pipe_reg
*reg
= &state
->regs
[i
];
1055 dirty
= block
->status
& R600_BLOCK_STATUS_DIRTY
;
1057 new_val
= block
->reg
[id
];
1058 new_val
&= ~reg
->mask
;
1059 new_val
|= reg
->value
;
1060 if (new_val
!= block
->reg
[id
]) {
1061 block
->reg
[id
] = new_val
;
1062 dirty
|= R600_BLOCK_STATUS_DIRTY
;
1064 if (block
->flags
& REG_FLAG_DIRTY_ALWAYS
)
1065 dirty
|= R600_BLOCK_STATUS_DIRTY
;
1066 if (block
->pm4_bo_index
[id
]) {
1067 /* find relocation */
1068 reloc_id
= block
->pm4_bo_index
[id
];
1069 r600_bo_reference(&block
->reloc
[reloc_id
].bo
, reg
->bo
);
1070 block
->reloc
[reloc_id
].bo_usage
= reg
->bo_usage
;
1071 /* always force dirty for relocs for now */
1072 dirty
|= R600_BLOCK_STATUS_DIRTY
;
1076 r600_context_dirty_block(ctx
, block
, dirty
, id
);
1080 static void r600_context_dirty_resource_block(struct r600_context
*ctx
,
1081 struct r600_block
*block
,
1082 int dirty
, int index
)
1084 block
->nreg_dirty
= index
+ 1;
1086 if ((dirty
!= (block
->status
& R600_BLOCK_STATUS_RESOURCE_DIRTY
)) || !(block
->status
& R600_BLOCK_STATUS_ENABLED
)) {
1087 block
->status
|= R600_BLOCK_STATUS_RESOURCE_DIRTY
;
1088 ctx
->pm4_dirty_cdwords
+= block
->pm4_ndwords
+ block
->pm4_flush_ndwords
;
1089 if (!(block
->status
& R600_BLOCK_STATUS_ENABLED
)) {
1090 block
->status
|= R600_BLOCK_STATUS_ENABLED
;
1091 LIST_ADDTAIL(&block
->enable_list
, &ctx
->enable_list
);
1093 LIST_ADDTAIL(&block
->list
,&ctx
->resource_dirty
);
1097 void r600_context_pipe_state_set_resource(struct r600_context
*ctx
, struct r600_pipe_resource_state
*state
, struct r600_block
*block
)
1100 int num_regs
= ctx
->radeon
->chip_class
>= EVERGREEN
? 8 : 7;
1103 if (state
== NULL
) {
1104 block
->status
&= ~(R600_BLOCK_STATUS_ENABLED
| R600_BLOCK_STATUS_RESOURCE_DIRTY
);
1105 if (block
->reloc
[1].bo
)
1106 block
->reloc
[1].bo
->binding
&= ~BO_BOUND_TEXTURE
;
1108 r600_bo_reference(&block
->reloc
[1].bo
, NULL
);
1109 r600_bo_reference(&block
->reloc
[2].bo
, NULL
);
1110 LIST_DELINIT(&block
->list
);
1111 LIST_DELINIT(&block
->enable_list
);
1115 is_vertex
= ((state
->val
[num_regs
-1] & 0xc0000000) == 0xc0000000);
1116 dirty
= block
->status
& R600_BLOCK_STATUS_RESOURCE_DIRTY
;
1118 if (memcmp(block
->reg
, state
->val
, num_regs
*4)) {
1119 memcpy(block
->reg
, state
->val
, num_regs
* 4);
1120 dirty
|= R600_BLOCK_STATUS_RESOURCE_DIRTY
;
1123 /* if no BOs on block, force dirty */
1124 if (!block
->reloc
[1].bo
|| !block
->reloc
[2].bo
)
1125 dirty
|= R600_BLOCK_STATUS_RESOURCE_DIRTY
;
1129 if (block
->reloc
[1].bo
->buf
!= state
->bo
[0]->buf
)
1130 dirty
|= R600_BLOCK_STATUS_RESOURCE_DIRTY
;
1132 if ((block
->reloc
[1].bo
->buf
!= state
->bo
[0]->buf
) ||
1133 (block
->reloc
[2].bo
->buf
!= state
->bo
[1]->buf
))
1134 dirty
|= R600_BLOCK_STATUS_RESOURCE_DIRTY
;
1140 /* VERTEX RESOURCE, we preted there is 2 bo to relocate so
1141 * we have single case btw VERTEX & TEXTURE resource
1143 r600_bo_reference(&block
->reloc
[1].bo
, state
->bo
[0]);
1144 block
->reloc
[1].bo_usage
= state
->bo_usage
[0];
1145 r600_bo_reference(&block
->reloc
[2].bo
, NULL
);
1147 /* TEXTURE RESOURCE */
1148 r600_bo_reference(&block
->reloc
[1].bo
, state
->bo
[0]);
1149 block
->reloc
[1].bo_usage
= state
->bo_usage
[0];
1150 r600_bo_reference(&block
->reloc
[2].bo
, state
->bo
[1]);
1151 block
->reloc
[2].bo_usage
= state
->bo_usage
[1];
1152 state
->bo
[0]->binding
|= BO_BOUND_TEXTURE
;
1156 block
->status
|= R600_BLOCK_STATUS_RESOURCE_VERTEX
;
1158 block
->status
&= ~R600_BLOCK_STATUS_RESOURCE_VERTEX
;
1160 r600_context_dirty_resource_block(ctx
, block
, dirty
, num_regs
- 1);
1164 void r600_context_pipe_state_set_ps_resource(struct r600_context
*ctx
, struct r600_pipe_resource_state
*state
, unsigned rid
)
1166 struct r600_block
*block
= ctx
->ps_resources
.blocks
[rid
];
1168 r600_context_pipe_state_set_resource(ctx
, state
, block
);
1171 void r600_context_pipe_state_set_vs_resource(struct r600_context
*ctx
, struct r600_pipe_resource_state
*state
, unsigned rid
)
1173 struct r600_block
*block
= ctx
->vs_resources
.blocks
[rid
];
1175 r600_context_pipe_state_set_resource(ctx
, state
, block
);
1178 void r600_context_pipe_state_set_fs_resource(struct r600_context
*ctx
, struct r600_pipe_resource_state
*state
, unsigned rid
)
1180 struct r600_block
*block
= ctx
->fs_resources
.blocks
[rid
];
1182 r600_context_pipe_state_set_resource(ctx
, state
, block
);
1185 static inline void r600_context_pipe_state_set_sampler(struct r600_context
*ctx
, struct r600_pipe_state
*state
, unsigned offset
)
1187 struct r600_range
*range
;
1188 struct r600_block
*block
;
1192 range
= &ctx
->range
[CTX_RANGE_ID(offset
)];
1193 block
= range
->blocks
[CTX_BLOCK_ID(offset
)];
1194 if (state
== NULL
) {
1195 block
->status
&= ~(R600_BLOCK_STATUS_ENABLED
| R600_BLOCK_STATUS_DIRTY
);
1196 LIST_DELINIT(&block
->list
);
1197 LIST_DELINIT(&block
->enable_list
);
1200 dirty
= block
->status
& R600_BLOCK_STATUS_DIRTY
;
1201 for (i
= 0; i
< 3; i
++) {
1202 if (block
->reg
[i
] != state
->regs
[i
].value
) {
1203 block
->reg
[i
] = state
->regs
[i
].value
;
1204 dirty
|= R600_BLOCK_STATUS_DIRTY
;
1209 r600_context_dirty_block(ctx
, block
, dirty
, 2);
1213 static inline void r600_context_pipe_state_set_sampler_border(struct r600_context
*ctx
, struct r600_pipe_state
*state
, unsigned offset
)
1215 struct r600_range
*range
;
1216 struct r600_block
*block
;
1220 range
= &ctx
->range
[CTX_RANGE_ID(offset
)];
1221 block
= range
->blocks
[CTX_BLOCK_ID(offset
)];
1222 if (state
== NULL
) {
1223 block
->status
&= ~(R600_BLOCK_STATUS_ENABLED
| R600_BLOCK_STATUS_DIRTY
);
1224 LIST_DELINIT(&block
->list
);
1225 LIST_DELINIT(&block
->enable_list
);
1228 if (state
->nregs
<= 3) {
1231 dirty
= block
->status
& R600_BLOCK_STATUS_DIRTY
;
1232 for (i
= 0; i
< 4; i
++) {
1233 if (block
->reg
[i
] != state
->regs
[i
+ 3].value
) {
1234 block
->reg
[i
] = state
->regs
[i
+ 3].value
;
1235 dirty
|= R600_BLOCK_STATUS_DIRTY
;
1239 /* We have to flush the shaders before we change the border color
1240 * registers, or previous draw commands that haven't completed yet
1241 * will end up using the new border color. */
1242 if (dirty
& R600_BLOCK_STATUS_DIRTY
)
1243 r600_context_ps_partial_flush(ctx
);
1245 r600_context_dirty_block(ctx
, block
, dirty
, 3);
1248 void r600_context_pipe_state_set_ps_sampler(struct r600_context
*ctx
, struct r600_pipe_state
*state
, unsigned id
)
1252 offset
= 0x0003C000 + id
* 0xc;
1253 r600_context_pipe_state_set_sampler(ctx
, state
, offset
);
1254 offset
= 0x0000A400 + id
* 0x10;
1255 r600_context_pipe_state_set_sampler_border(ctx
, state
, offset
);
1258 void r600_context_pipe_state_set_vs_sampler(struct r600_context
*ctx
, struct r600_pipe_state
*state
, unsigned id
)
1262 offset
= 0x0003C0D8 + id
* 0xc;
1263 r600_context_pipe_state_set_sampler(ctx
, state
, offset
);
1264 offset
= 0x0000A600 + id
* 0x10;
1265 r600_context_pipe_state_set_sampler_border(ctx
, state
, offset
);
1268 struct r600_bo
*r600_context_reg_bo(struct r600_context
*ctx
, unsigned offset
)
1270 struct r600_range
*range
;
1271 struct r600_block
*block
;
1274 range
= &ctx
->range
[CTX_RANGE_ID(offset
)];
1275 block
= range
->blocks
[CTX_BLOCK_ID(offset
)];
1276 offset
-= block
->start_offset
;
1277 id
= block
->pm4_bo_index
[offset
>> 2];
1278 if (block
->reloc
[id
].bo
) {
1279 return block
->reloc
[id
].bo
;
1284 void r600_context_block_emit_dirty(struct r600_context
*ctx
, struct r600_block
*block
)
1286 int optional
= block
->nbo
== 0 && !(block
->flags
& REG_FLAG_DIRTY_ALWAYS
);
1287 int cp_dwords
= block
->pm4_ndwords
, start_dword
= 0;
1289 int nbo
= block
->nbo
;
1291 if (block
->nreg_dirty
== 0 && optional
) {
1296 ctx
->flags
|= R600_CONTEXT_CHECK_EVENT_FLUSH
;
1298 for (int j
= 0; j
< block
->nreg
; j
++) {
1299 if (block
->pm4_bo_index
[j
]) {
1300 /* find relocation */
1301 struct r600_block_reloc
*reloc
= &block
->reloc
[block
->pm4_bo_index
[j
]];
1302 block
->pm4
[reloc
->bo_pm4_index
] =
1303 r600_context_bo_reloc(ctx
, reloc
->bo
, reloc
->bo_usage
);
1304 r600_context_bo_flush(ctx
,
1313 ctx
->flags
&= ~R600_CONTEXT_CHECK_EVENT_FLUSH
;
1316 optional
&= (block
->nreg_dirty
!= block
->nreg
);
1318 new_dwords
= block
->nreg_dirty
;
1319 start_dword
= ctx
->pm4_cdwords
;
1320 cp_dwords
= new_dwords
+ 2;
1322 memcpy(&ctx
->pm4
[ctx
->pm4_cdwords
], block
->pm4
, cp_dwords
* 4);
1323 ctx
->pm4_cdwords
+= cp_dwords
;
1328 newword
= ctx
->pm4
[start_dword
];
1329 newword
&= PKT_COUNT_C
;
1330 newword
|= PKT_COUNT_S(new_dwords
);
1331 ctx
->pm4
[start_dword
] = newword
;
1334 block
->status
^= R600_BLOCK_STATUS_DIRTY
;
1335 block
->nreg_dirty
= 0;
1336 LIST_DELINIT(&block
->list
);
1339 void r600_context_block_resource_emit_dirty(struct r600_context
*ctx
, struct r600_block
*block
)
1341 int cp_dwords
= block
->pm4_ndwords
;
1342 int nbo
= block
->nbo
;
1344 ctx
->flags
|= R600_CONTEXT_CHECK_EVENT_FLUSH
;
1346 if (block
->status
& R600_BLOCK_STATUS_RESOURCE_VERTEX
) {
1348 cp_dwords
-= 2; /* don't copy the second NOP */
1351 for (int j
= 0; j
< nbo
; j
++) {
1352 if (block
->pm4_bo_index
[j
]) {
1353 /* find relocation */
1354 struct r600_block_reloc
*reloc
= &block
->reloc
[block
->pm4_bo_index
[j
]];
1355 block
->pm4
[reloc
->bo_pm4_index
] =
1356 r600_context_bo_reloc(ctx
, reloc
->bo
, reloc
->bo_usage
);
1357 r600_context_bo_flush(ctx
,
1363 ctx
->flags
&= ~R600_CONTEXT_CHECK_EVENT_FLUSH
;
1365 memcpy(&ctx
->pm4
[ctx
->pm4_cdwords
], block
->pm4
, cp_dwords
* 4);
1366 ctx
->pm4_cdwords
+= cp_dwords
;
1368 block
->status
^= R600_BLOCK_STATUS_RESOURCE_DIRTY
;
1369 block
->nreg_dirty
= 0;
1370 LIST_DELINIT(&block
->list
);
1373 void r600_context_flush_dest_caches(struct r600_context
*ctx
)
1375 struct r600_bo
*cb
[8];
1379 if (!(ctx
->flags
& R600_CONTEXT_DST_CACHES_DIRTY
))
1382 db
= r600_context_reg_bo(ctx
, R_02800C_DB_DEPTH_BASE
);
1383 cb
[0] = r600_context_reg_bo(ctx
, R_028040_CB_COLOR0_BASE
);
1384 cb
[1] = r600_context_reg_bo(ctx
, R_028044_CB_COLOR1_BASE
);
1385 cb
[2] = r600_context_reg_bo(ctx
, R_028048_CB_COLOR2_BASE
);
1386 cb
[3] = r600_context_reg_bo(ctx
, R_02804C_CB_COLOR3_BASE
);
1387 cb
[4] = r600_context_reg_bo(ctx
, R_028050_CB_COLOR4_BASE
);
1388 cb
[5] = r600_context_reg_bo(ctx
, R_028054_CB_COLOR5_BASE
);
1389 cb
[6] = r600_context_reg_bo(ctx
, R_028058_CB_COLOR6_BASE
);
1390 cb
[7] = r600_context_reg_bo(ctx
, R_02805C_CB_COLOR7_BASE
);
1392 ctx
->flags
|= R600_CONTEXT_CHECK_EVENT_FLUSH
;
1393 /* flush the color buffers */
1394 for (i
= 0; i
< 8; i
++) {
1398 r600_context_bo_flush(ctx
,
1399 (S_0085F0_CB0_DEST_BASE_ENA(1) << i
) |
1400 S_0085F0_CB_ACTION_ENA(1),
1404 r600_context_bo_flush(ctx
, S_0085F0_DB_ACTION_ENA(1) | S_0085F0_DB_DEST_BASE_ENA(1), 0, db
);
1406 ctx
->flags
&= ~R600_CONTEXT_CHECK_EVENT_FLUSH
;
1407 ctx
->flags
&= ~R600_CONTEXT_DST_CACHES_DIRTY
;
1410 void r600_context_draw(struct r600_context
*ctx
, const struct r600_draw
*draw
)
1412 unsigned ndwords
= 7;
1413 struct r600_block
*dirty_block
= NULL
;
1414 struct r600_block
*next_block
;
1417 if (draw
->indices
) {
1421 /* queries need some special values */
1422 if (ctx
->num_query_running
) {
1423 if (ctx
->radeon
->family
>= CHIP_RV770
) {
1424 r600_context_reg(ctx
,
1425 R_028D0C_DB_RENDER_CONTROL
,
1426 S_028D0C_R700_PERFECT_ZPASS_COUNTS(1),
1427 S_028D0C_R700_PERFECT_ZPASS_COUNTS(1));
1429 r600_context_reg(ctx
,
1430 R_028D10_DB_RENDER_OVERRIDE
,
1431 S_028D10_NOOP_CULL_DISABLE(1),
1432 S_028D10_NOOP_CULL_DISABLE(1));
1435 /* update the max dword count to make sure we have enough space
1436 * reserved for flushing the destination caches */
1437 ctx
->pm4_ndwords
= RADEON_MAX_CMDBUF_DWORDS
- ctx
->num_dest_buffers
* 7 - 16;
1439 if ((ctx
->pm4_dirty_cdwords
+ ndwords
+ ctx
->pm4_cdwords
) > ctx
->pm4_ndwords
) {
1441 r600_context_flush(ctx
, RADEON_FLUSH_ASYNC
);
1443 /* at that point everythings is flushed and ctx->pm4_cdwords = 0 */
1444 if ((ctx
->pm4_dirty_cdwords
+ ndwords
) > ctx
->pm4_ndwords
) {
1445 R600_ERR("context is too big to be scheduled\n");
1448 /* enough room to copy packet */
1449 LIST_FOR_EACH_ENTRY_SAFE(dirty_block
, next_block
, &ctx
->dirty
, list
) {
1450 r600_context_block_emit_dirty(ctx
, dirty_block
);
1453 LIST_FOR_EACH_ENTRY_SAFE(dirty_block
, next_block
, &ctx
->resource_dirty
, list
) {
1454 r600_context_block_resource_emit_dirty(ctx
, dirty_block
);
1458 pm4
= &ctx
->pm4
[ctx
->pm4_cdwords
];
1460 pm4
[0] = PKT3(PKT3_INDEX_TYPE
, 0, ctx
->predicate_drawing
);
1461 pm4
[1] = draw
->vgt_index_type
;
1462 pm4
[2] = PKT3(PKT3_NUM_INSTANCES
, 0, ctx
->predicate_drawing
);
1463 pm4
[3] = draw
->vgt_num_instances
;
1464 if (draw
->indices
) {
1465 pm4
[4] = PKT3(PKT3_DRAW_INDEX
, 3, ctx
->predicate_drawing
);
1466 pm4
[5] = draw
->indices_bo_offset
;
1468 pm4
[7] = draw
->vgt_num_indices
;
1469 pm4
[8] = draw
->vgt_draw_initiator
;
1470 pm4
[9] = PKT3(PKT3_NOP
, 0, ctx
->predicate_drawing
);
1471 pm4
[10] = r600_context_bo_reloc(ctx
, draw
->indices
, RADEON_USAGE_READ
);
1473 pm4
[4] = PKT3(PKT3_DRAW_INDEX_AUTO
, 1, ctx
->predicate_drawing
);
1474 pm4
[5] = draw
->vgt_num_indices
;
1475 pm4
[6] = draw
->vgt_draw_initiator
;
1477 ctx
->pm4_cdwords
+= ndwords
;
1479 ctx
->flags
|= (R600_CONTEXT_DST_CACHES_DIRTY
| R600_CONTEXT_DRAW_PENDING
);
1481 /* all dirty state have been scheduled in current cs */
1482 ctx
->pm4_dirty_cdwords
= 0;
1485 void r600_context_flush(struct r600_context
*ctx
, unsigned flags
)
1487 struct r600_block
*enable_block
= NULL
;
1489 if (ctx
->pm4_cdwords
== ctx
->init_dwords
)
1492 /* suspend queries */
1493 r600_context_queries_suspend(ctx
);
1495 if (ctx
->radeon
->chip_class
>= EVERGREEN
)
1496 evergreen_context_flush_dest_caches(ctx
);
1498 r600_context_flush_dest_caches(ctx
);
1500 /* partial flush is needed to avoid lockups on some chips with user fences */
1501 ctx
->pm4
[ctx
->pm4_cdwords
++] = PKT3(PKT3_EVENT_WRITE
, 0, 0);
1502 ctx
->pm4
[ctx
->pm4_cdwords
++] = EVENT_TYPE(EVENT_TYPE_PS_PARTIAL_FLUSH
) | EVENT_INDEX(4);
1505 ctx
->cs
->cdw
= ctx
->pm4_cdwords
;
1506 ctx
->radeon
->ws
->cs_flush(ctx
->cs
, flags
);
1508 /* We need to get the pointer to the other CS,
1509 * the command streams are double-buffered. */
1510 ctx
->pm4
= ctx
->cs
->buf
;
1513 for (int i
= 0; i
< ctx
->creloc
; i
++) {
1514 ctx
->bo
[i
]->last_flush
= 0;
1515 r600_bo_reference(&ctx
->bo
[i
], NULL
);
1518 ctx
->pm4_dirty_cdwords
= 0;
1519 ctx
->pm4_cdwords
= 0;
1524 /* resume queries */
1525 r600_context_queries_resume(ctx
, TRUE
);
1527 /* set all valid group as dirty so they get reemited on
1530 LIST_FOR_EACH_ENTRY(enable_block
, &ctx
->enable_list
, enable_list
) {
1531 if (!(enable_block
->flags
& BLOCK_FLAG_RESOURCE
)) {
1532 if(!(enable_block
->status
& R600_BLOCK_STATUS_DIRTY
)) {
1533 LIST_ADDTAIL(&enable_block
->list
,&ctx
->dirty
);
1534 enable_block
->status
|= R600_BLOCK_STATUS_DIRTY
;
1537 if(!(enable_block
->status
& R600_BLOCK_STATUS_RESOURCE_DIRTY
)) {
1538 LIST_ADDTAIL(&enable_block
->list
,&ctx
->resource_dirty
);
1539 enable_block
->status
|= R600_BLOCK_STATUS_RESOURCE_DIRTY
;
1542 ctx
->pm4_dirty_cdwords
+= enable_block
->pm4_ndwords
+
1543 enable_block
->pm4_flush_ndwords
;
1544 enable_block
->nreg_dirty
= enable_block
->nreg
;
1548 void r600_context_emit_fence(struct r600_context
*ctx
, struct r600_bo
*fence_bo
, unsigned offset
, unsigned value
)
1550 unsigned ndwords
= 10;
1552 if ((ctx
->pm4_dirty_cdwords
+ ndwords
+ ctx
->pm4_cdwords
) > ctx
->pm4_ndwords
) {
1554 r600_context_flush(ctx
, RADEON_FLUSH_ASYNC
);
1557 ctx
->pm4
[ctx
->pm4_cdwords
++] = PKT3(PKT3_EVENT_WRITE
, 0, 0);
1558 ctx
->pm4
[ctx
->pm4_cdwords
++] = EVENT_TYPE(EVENT_TYPE_PS_PARTIAL_FLUSH
) | EVENT_INDEX(4);
1559 ctx
->pm4
[ctx
->pm4_cdwords
++] = PKT3(PKT3_EVENT_WRITE_EOP
, 4, 0);
1560 ctx
->pm4
[ctx
->pm4_cdwords
++] = EVENT_TYPE(EVENT_TYPE_CACHE_FLUSH_AND_INV_TS_EVENT
) | EVENT_INDEX(5);
1561 ctx
->pm4
[ctx
->pm4_cdwords
++] = offset
<< 2; /* ADDRESS_LO */
1562 ctx
->pm4
[ctx
->pm4_cdwords
++] = (1 << 29) | (0 << 24); /* DATA_SEL | INT_EN | ADDRESS_HI */
1563 ctx
->pm4
[ctx
->pm4_cdwords
++] = value
; /* DATA_LO */
1564 ctx
->pm4
[ctx
->pm4_cdwords
++] = 0; /* DATA_HI */
1565 ctx
->pm4
[ctx
->pm4_cdwords
++] = PKT3(PKT3_NOP
, 0, 0);
1566 ctx
->pm4
[ctx
->pm4_cdwords
++] = r600_context_bo_reloc(ctx
, fence_bo
, RADEON_USAGE_WRITE
);
1569 static boolean
r600_query_result(struct r600_context
*ctx
, struct r600_query
*query
, boolean wait
)
1571 unsigned results_base
= query
->results_start
;
1573 u32
*results
, *current_result
;
1576 results
= r600_bo_map(ctx
->radeon
, query
->buffer
, ctx
->cs
, PIPE_TRANSFER_READ
);
1578 results
= r600_bo_map(ctx
->radeon
, query
->buffer
, ctx
->cs
, PIPE_TRANSFER_DONTBLOCK
| PIPE_TRANSFER_READ
);
1583 /* count all results across all data blocks */
1584 while (results_base
!= query
->results_end
) {
1585 current_result
= (u32
*)((char*)results
+ results_base
);
1587 start
= (u64
)current_result
[0] | (u64
)current_result
[1] << 32;
1588 end
= (u64
)current_result
[2] | (u64
)current_result
[3] << 32;
1589 if (((start
& 0x8000000000000000UL
) && (end
& 0x8000000000000000UL
))
1590 || query
->type
== PIPE_QUERY_TIME_ELAPSED
) {
1591 query
->result
+= end
- start
;
1594 results_base
+= 4 * 4;
1595 if (results_base
>= query
->buffer_size
)
1599 query
->results_start
= query
->results_end
;
1600 r600_bo_unmap(ctx
->radeon
, query
->buffer
);
1604 void r600_query_begin(struct r600_context
*ctx
, struct r600_query
*query
)
1606 unsigned required_space
, new_results_end
;
1608 /* query request needs 6/8 dwords for begin + 6/8 dwords for end */
1609 if (query
->type
== PIPE_QUERY_TIME_ELAPSED
)
1610 required_space
= 16;
1612 required_space
= 12;
1614 if ((required_space
+ ctx
->pm4_cdwords
) > ctx
->pm4_ndwords
) {
1616 r600_context_flush(ctx
, RADEON_FLUSH_ASYNC
);
1619 if (query
->type
== PIPE_QUERY_OCCLUSION_COUNTER
) {
1620 /* Count queries emitted without flushes, and flush if more than
1621 * half of buffer used, to avoid overwriting results which may be
1623 if (query
->state
& R600_QUERY_STATE_FLUSHED
) {
1624 query
->queries_emitted
= 1;
1626 if (++query
->queries_emitted
> query
->buffer_size
/ query
->result_size
/ 2)
1627 r600_context_flush(ctx
, RADEON_FLUSH_ASYNC
);
1631 new_results_end
= query
->results_end
+ query
->result_size
;
1632 if (new_results_end
>= query
->buffer_size
)
1633 new_results_end
= 0;
1635 /* collect current results if query buffer is full */
1636 if (new_results_end
== query
->results_start
) {
1637 if (!(query
->state
& R600_QUERY_STATE_FLUSHED
))
1638 r600_context_flush(ctx
, 0);
1639 r600_query_result(ctx
, query
, TRUE
);
1642 if (query
->type
== PIPE_QUERY_OCCLUSION_COUNTER
) {
1646 results
= r600_bo_map(ctx
->radeon
, query
->buffer
, ctx
->cs
, PIPE_TRANSFER_WRITE
);
1648 results
= (u32
*)((char*)results
+ query
->results_end
);
1649 memset(results
, 0, query
->result_size
);
1651 /* Set top bits for unused backends */
1652 for (i
= 0; i
< ctx
->max_db
; i
++) {
1653 if (!(ctx
->backend_mask
& (1<<i
))) {
1654 results
[(i
* 4)+1] = 0x80000000;
1655 results
[(i
* 4)+3] = 0x80000000;
1658 r600_bo_unmap(ctx
->radeon
, query
->buffer
);
1662 /* emit begin query */
1663 if (query
->type
== PIPE_QUERY_TIME_ELAPSED
) {
1664 ctx
->pm4
[ctx
->pm4_cdwords
++] = PKT3(PKT3_EVENT_WRITE_EOP
, 4, 0);
1665 ctx
->pm4
[ctx
->pm4_cdwords
++] = EVENT_TYPE(EVENT_TYPE_CACHE_FLUSH_AND_INV_TS_EVENT
) | EVENT_INDEX(5);
1666 ctx
->pm4
[ctx
->pm4_cdwords
++] = query
->results_end
;
1667 ctx
->pm4
[ctx
->pm4_cdwords
++] = (3 << 29);
1668 ctx
->pm4
[ctx
->pm4_cdwords
++] = 0;
1669 ctx
->pm4
[ctx
->pm4_cdwords
++] = 0;
1671 ctx
->pm4
[ctx
->pm4_cdwords
++] = PKT3(PKT3_EVENT_WRITE
, 2, 0);
1672 ctx
->pm4
[ctx
->pm4_cdwords
++] = EVENT_TYPE(EVENT_TYPE_ZPASS_DONE
) | EVENT_INDEX(1);
1673 ctx
->pm4
[ctx
->pm4_cdwords
++] = query
->results_end
;
1674 ctx
->pm4
[ctx
->pm4_cdwords
++] = 0;
1676 ctx
->pm4
[ctx
->pm4_cdwords
++] = PKT3(PKT3_NOP
, 0, 0);
1677 ctx
->pm4
[ctx
->pm4_cdwords
++] = r600_context_bo_reloc(ctx
, query
->buffer
, RADEON_USAGE_WRITE
);
1679 query
->state
|= R600_QUERY_STATE_STARTED
;
1680 query
->state
^= R600_QUERY_STATE_ENDED
;
1681 ctx
->num_query_running
++;
1684 void r600_query_end(struct r600_context
*ctx
, struct r600_query
*query
)
1686 /* emit end query */
1687 if (query
->type
== PIPE_QUERY_TIME_ELAPSED
) {
1688 ctx
->pm4
[ctx
->pm4_cdwords
++] = PKT3(PKT3_EVENT_WRITE_EOP
, 4, 0);
1689 ctx
->pm4
[ctx
->pm4_cdwords
++] = EVENT_TYPE(EVENT_TYPE_CACHE_FLUSH_AND_INV_TS_EVENT
) | EVENT_INDEX(5);
1690 ctx
->pm4
[ctx
->pm4_cdwords
++] = query
->results_end
+ 8;
1691 ctx
->pm4
[ctx
->pm4_cdwords
++] = (3 << 29);
1692 ctx
->pm4
[ctx
->pm4_cdwords
++] = 0;
1693 ctx
->pm4
[ctx
->pm4_cdwords
++] = 0;
1695 ctx
->pm4
[ctx
->pm4_cdwords
++] = PKT3(PKT3_EVENT_WRITE
, 2, 0);
1696 ctx
->pm4
[ctx
->pm4_cdwords
++] = EVENT_TYPE(EVENT_TYPE_ZPASS_DONE
) | EVENT_INDEX(1);
1697 ctx
->pm4
[ctx
->pm4_cdwords
++] = query
->results_end
+ 8;
1698 ctx
->pm4
[ctx
->pm4_cdwords
++] = 0;
1700 ctx
->pm4
[ctx
->pm4_cdwords
++] = PKT3(PKT3_NOP
, 0, 0);
1701 ctx
->pm4
[ctx
->pm4_cdwords
++] = r600_context_bo_reloc(ctx
, query
->buffer
, RADEON_USAGE_WRITE
);
1703 query
->results_end
+= query
->result_size
;
1704 if (query
->results_end
>= query
->buffer_size
)
1705 query
->results_end
= 0;
1707 query
->state
^= R600_QUERY_STATE_STARTED
;
1708 query
->state
|= R600_QUERY_STATE_ENDED
;
1709 query
->state
&= ~R600_QUERY_STATE_FLUSHED
;
1711 ctx
->num_query_running
--;
1714 void r600_query_predication(struct r600_context
*ctx
, struct r600_query
*query
, int operation
,
1717 if (operation
== PREDICATION_OP_CLEAR
) {
1718 if (ctx
->pm4_cdwords
+ 3 > ctx
->pm4_ndwords
)
1719 r600_context_flush(ctx
, RADEON_FLUSH_ASYNC
);
1721 ctx
->pm4
[ctx
->pm4_cdwords
++] = PKT3(PKT3_SET_PREDICATION
, 1, 0);
1722 ctx
->pm4
[ctx
->pm4_cdwords
++] = 0;
1723 ctx
->pm4
[ctx
->pm4_cdwords
++] = PRED_OP(PREDICATION_OP_CLEAR
);
1725 unsigned results_base
= query
->results_start
;
1729 /* find count of the query data blocks */
1730 count
= query
->buffer_size
+ query
->results_end
- query
->results_start
;
1731 if (count
>= query
->buffer_size
) count
-=query
->buffer_size
;
1732 count
/= query
->result_size
;
1734 if (ctx
->pm4_cdwords
+ 5 * count
> ctx
->pm4_ndwords
)
1735 r600_context_flush(ctx
, RADEON_FLUSH_ASYNC
);
1737 op
= PRED_OP(operation
) | PREDICATION_DRAW_VISIBLE
|
1738 (flag_wait
? PREDICATION_HINT_WAIT
: PREDICATION_HINT_NOWAIT_DRAW
);
1740 /* emit predicate packets for all data blocks */
1741 while (results_base
!= query
->results_end
) {
1742 ctx
->pm4
[ctx
->pm4_cdwords
++] = PKT3(PKT3_SET_PREDICATION
, 1, 0);
1743 ctx
->pm4
[ctx
->pm4_cdwords
++] = results_base
;
1744 ctx
->pm4
[ctx
->pm4_cdwords
++] = op
;
1745 ctx
->pm4
[ctx
->pm4_cdwords
++] = PKT3(PKT3_NOP
, 0, 0);
1746 ctx
->pm4
[ctx
->pm4_cdwords
++] = r600_context_bo_reloc(ctx
, query
->buffer
,
1748 results_base
+= query
->result_size
;
1749 if (results_base
>= query
->buffer_size
)
1751 /* set CONTINUE bit for all packets except the first */
1752 op
|= PREDICATION_CONTINUE
;
1757 struct r600_query
*r600_context_query_create(struct r600_context
*ctx
, unsigned query_type
)
1759 struct r600_query
*query
;
1761 if (query_type
!= PIPE_QUERY_OCCLUSION_COUNTER
&& query_type
!= PIPE_QUERY_TIME_ELAPSED
)
1764 query
= calloc(1, sizeof(struct r600_query
));
1768 query
->type
= query_type
;
1769 query
->buffer_size
= 4096;
1771 if (query_type
== PIPE_QUERY_OCCLUSION_COUNTER
)
1772 query
->result_size
= 4 * 4 * ctx
->max_db
;
1774 query
->result_size
= 4 * 4;
1776 /* adjust buffer size to simplify offsets wrapping math */
1777 query
->buffer_size
-= query
->buffer_size
% query
->result_size
;
1779 /* As of GL4, query buffers are normally read by the CPU after
1780 * being written by the gpu, hence staging is probably a good
1783 query
->buffer
= r600_bo(ctx
->radeon
, query
->buffer_size
, 1, 0,
1784 PIPE_USAGE_STAGING
);
1785 if (!query
->buffer
) {
1790 LIST_ADDTAIL(&query
->list
, &ctx
->query_list
);
1795 void r600_context_query_destroy(struct r600_context
*ctx
, struct r600_query
*query
)
1797 r600_bo_reference(&query
->buffer
, NULL
);
1798 LIST_DELINIT(&query
->list
);
1802 boolean
r600_context_query_result(struct r600_context
*ctx
,
1803 struct r600_query
*query
,
1804 boolean wait
, void *vresult
)
1806 uint64_t *result
= (uint64_t*)vresult
;
1808 if (!(query
->state
& R600_QUERY_STATE_FLUSHED
)) {
1809 r600_context_flush(ctx
, 0);
1811 if (!r600_query_result(ctx
, query
, wait
))
1813 if (query
->type
== PIPE_QUERY_TIME_ELAPSED
)
1814 *result
= (1000000*query
->result
)/r600_get_clock_crystal_freq(ctx
->radeon
);
1816 *result
= query
->result
;
1821 void r600_context_queries_suspend(struct r600_context
*ctx
)
1823 struct r600_query
*query
;
1825 LIST_FOR_EACH_ENTRY(query
, &ctx
->query_list
, list
) {
1826 if (query
->state
& R600_QUERY_STATE_STARTED
) {
1827 r600_query_end(ctx
, query
);
1828 query
->state
|= R600_QUERY_STATE_SUSPENDED
;
1833 void r600_context_queries_resume(struct r600_context
*ctx
, boolean flushed
)
1835 struct r600_query
*query
;
1837 LIST_FOR_EACH_ENTRY(query
, &ctx
->query_list
, list
) {
1839 query
->state
|= R600_QUERY_STATE_FLUSHED
;
1841 if (query
->state
& R600_QUERY_STATE_SUSPENDED
) {
1842 r600_query_begin(ctx
, query
);
1843 query
->state
^= R600_QUERY_STATE_SUSPENDED
;