projects / mesa.git / blob
? search:
summary | shortlog | log | commit | commitdiff | tree
history | raw | HEAD
r600g: no need to drop the references here.
[mesa.git] / src / gallium / winsys / r600 / drm / r600_hw_context.c
1 /*
2 * Copyright 2010 Jerome Glisse <glisse@freedesktop.org>
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * on the rights to use, copy, modify, merge, publish, distribute, sub
8 * license, and/or sell copies of the Software, and to permit persons to whom
9 * the Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
22 *
23 * Authors:
24 * Jerome Glisse
25 */
26 #include <errno.h>
27 #include <stdint.h>
28 #include <string.h>
29 #include <stdlib.h>
30 #include <assert.h>
31 #include <pipe/p_compiler.h>
32 #include <util/u_inlines.h>
33 #include <util/u_memory.h>
34 #include <pipebuffer/pb_bufmgr.h>
35 #include "xf86drm.h"
36 #include "radeon_drm.h"
37 #include "r600_priv.h"
38 #include "bof.h"
39 #include "r600d.h"
40
41 #define GROUP_FORCE_NEW_BLOCK 0
42
43 void r600_init_cs(struct r600_context *ctx)
44 {
45 /* R6xx requires this packet at the start of each command buffer */
46 if (ctx->radeon->family < CHIP_RV770) {
47 ctx->pm4[ctx->pm4_cdwords++] = PKT3(PKT3_START_3D_CMDBUF, 0, 0);
48 ctx->pm4[ctx->pm4_cdwords++] = 0x00000000;
49 }
50 /* All asics require this one */
51 ctx->pm4[ctx->pm4_cdwords++] = PKT3(PKT3_CONTEXT_CONTROL, 1, 0);
52 ctx->pm4[ctx->pm4_cdwords++] = 0x80000000;
53 ctx->pm4[ctx->pm4_cdwords++] = 0x80000000;
54 }
55
56 static void INLINE r600_context_update_fenced_list(struct r600_context *ctx)
57 {
58 for (int i = 0; i < ctx->creloc; i++) {
59 if (!LIST_IS_EMPTY(&ctx->bo[i]->fencedlist))
60 LIST_DELINIT(&ctx->bo[i]->fencedlist);
61 LIST_ADDTAIL(&ctx->bo[i]->fencedlist, &ctx->fenced_bo);
62 ctx->bo[i]->fence = ctx->radeon->fence;
63 ctx->bo[i]->ctx = ctx;
64 }
65 }
66
67 static void INLINE r600_context_fence_wraparound(struct r600_context *ctx, unsigned fence)
68 {
69 struct radeon_bo *bo = NULL;
70 struct radeon_bo *tmp;
71
72 LIST_FOR_EACH_ENTRY_SAFE(bo, tmp, &ctx->fenced_bo, fencedlist) {
73 if (bo->fence <= *ctx->radeon->cfence) {
74 LIST_DELINIT(&bo->fencedlist);
75 bo->fence = 0;
76 } else {
77 bo->fence = fence;
78 }
79 }
80 }
81
82 static void r600_init_block(struct r600_context *ctx,
83 struct r600_block *block,
84 const struct r600_reg *reg, int index, int nreg,
85 unsigned opcode, unsigned offset_base)
86 {
87 int i = index;
88 int j, n = nreg;
89
90 /* initialize block */
91 block->status |= R600_BLOCK_STATUS_DIRTY; /* dirty all blocks at start */
92 block->start_offset = reg[i].offset;
93 block->pm4[block->pm4_ndwords++] = PKT3(opcode, n, 0);
94 block->pm4[block->pm4_ndwords++] = (block->start_offset - offset_base) >> 2;
95 block->reg = &block->pm4[block->pm4_ndwords];
96 block->pm4_ndwords += n;
97 block->nreg = n;
98 block->nreg_dirty = n;
99 block->flags = 0;
100 LIST_INITHEAD(&block->list);
101 LIST_INITHEAD(&block->enable_list);
102
103 for (j = 0; j < n; j++) {
104 if (reg[i+j].flags & REG_FLAG_DIRTY_ALWAYS) {
105 block->flags |= REG_FLAG_DIRTY_ALWAYS;
106 }
107 if (reg[i+j].flags & REG_FLAG_ENABLE_ALWAYS) {
108 block->status |= R600_BLOCK_STATUS_ENABLED;
109 LIST_ADDTAIL(&block->enable_list, &ctx->enable_list);
110 }
111
112 if (reg[i+j].flags & REG_FLAG_NEED_BO) {
113 block->nbo++;
114 assert(block->nbo < R600_BLOCK_MAX_BO);
115 block->pm4_bo_index[j] = block->nbo;
116 block->pm4[block->pm4_ndwords++] = PKT3(PKT3_NOP, 0, 0);
117 block->pm4[block->pm4_ndwords++] = 0x00000000;
118 if (reg[i+j].flags & REG_FLAG_RV6XX_SBU) {
119 block->reloc[block->nbo].flush_flags = 0;
120 block->reloc[block->nbo].flush_mask = 0;
121 } else {
122 block->reloc[block->nbo].flush_flags = reg[i+j].flush_flags;
123 block->reloc[block->nbo].flush_mask = reg[i+j].flush_mask;
124 }
125 block->reloc[block->nbo].bo_pm4_index = block->pm4_ndwords - 1;
126 }
127 if ((ctx->radeon->family > CHIP_R600) &&
128 (ctx->radeon->family < CHIP_RV770) && reg[i+j].flags & REG_FLAG_RV6XX_SBU) {
129 block->pm4[block->pm4_ndwords++] = PKT3(PKT3_SURFACE_BASE_UPDATE, 0, 0);
130 block->pm4[block->pm4_ndwords++] = reg[i+j].flush_flags;
131 }
132 }
133 for (j = 0; j < n; j++) {
134 if (reg[i+j].flush_flags) {
135 block->pm4_flush_ndwords += 7;
136 }
137 }
138 /* check that we stay in limit */
139 assert(block->pm4_ndwords < R600_BLOCK_MAX_REG);
140 }
141
142 int r600_context_add_block(struct r600_context *ctx, const struct r600_reg *reg, unsigned nreg,
143 unsigned opcode, unsigned offset_base)
144 {
145 struct r600_block *block;
146 struct r600_range *range;
147 int offset;
148
149 for (unsigned i = 0, n = 0; i < nreg; i += n) {
150 /* ignore new block balise */
151 if (reg[i].offset == GROUP_FORCE_NEW_BLOCK) {
152 n = 1;
153 continue;
154 }
155
156 /* ignore regs not on R600 on R600 */
157 if ((reg[i].flags & REG_FLAG_NOT_R600) && ctx->radeon->family == CHIP_R600) {
158 n = 1;
159 continue;
160 }
161
162 /* register that need relocation are in their own group */
163 /* find number of consecutive registers */
164 n = 0;
165 offset = reg[i].offset;
166 while (reg[i + n].offset == offset) {
167 n++;
168 offset += 4;
169 if ((n + i) >= nreg)
170 break;
171 if (n >= (R600_BLOCK_MAX_REG - 2))
172 break;
173 }
174
175 /* allocate new block */
176 block = calloc(1, sizeof(struct r600_block));
177 if (block == NULL) {
178 return -ENOMEM;
179 }
180 ctx->nblocks++;
181 for (int j = 0; j < n; j++) {
182 range = &ctx->range[CTX_RANGE_ID(reg[i + j].offset)];
183 /* create block table if it doesn't exist */
184 if (!range->blocks)
185 range->blocks = calloc(1 << HASH_SHIFT, sizeof(void *));
186 if (!range->blocks)
187 return -1;
188
189 range->blocks[CTX_BLOCK_ID(reg[i + j].offset)] = block;
190 }
191
192 r600_init_block(ctx, block, reg, i, n, opcode, offset_base);
193
194 }
195 return 0;
196 }
197
198 /* R600/R700 configuration */
199 static const struct r600_reg r600_config_reg_list[] = {
200 {R_008958_VGT_PRIMITIVE_TYPE, 0, 0, 0},
201 {R_008C00_SQ_CONFIG, 0, 0, 0},
202 {R_008C04_SQ_GPR_RESOURCE_MGMT_1, 0, 0, 0},
203 {R_008C08_SQ_GPR_RESOURCE_MGMT_2, 0, 0, 0},
204 {R_008C0C_SQ_THREAD_RESOURCE_MGMT, 0, 0, 0},
205 {R_008C10_SQ_STACK_RESOURCE_MGMT_1, 0, 0, 0},
206 {R_008C14_SQ_STACK_RESOURCE_MGMT_2, 0, 0, 0},
207 {R_008D8C_SQ_DYN_GPR_CNTL_PS_FLUSH_REQ, 0, 0, 0},
208 {R_009508_TA_CNTL_AUX, 0, 0, 0},
209 {R_009714_VC_ENHANCE, 0, 0, 0},
210 {R_009830_DB_DEBUG, 0, 0, 0},
211 {R_009838_DB_WATERMARKS, 0, 0, 0},
212 };
213
214 static const struct r600_reg r600_ctl_const_list[] = {
215 {R_03CFF0_SQ_VTX_BASE_VTX_LOC, 0, 0, 0},
216 {R_03CFF4_SQ_VTX_START_INST_LOC, 0, 0, 0},
217 };
218
219 static const struct r600_reg r600_context_reg_list[] = {
220 {R_028350_SX_MISC, 0, 0, 0},
221 {R_0286C8_SPI_THREAD_GROUPING, 0, 0, 0},
222 {R_0288A8_SQ_ESGS_RING_ITEMSIZE, 0, 0, 0},
223 {R_0288AC_SQ_GSVS_RING_ITEMSIZE, 0, 0, 0},
224 {R_0288B0_SQ_ESTMP_RING_ITEMSIZE, 0, 0, 0},
225 {R_0288B4_SQ_GSTMP_RING_ITEMSIZE, 0, 0, 0},
226 {R_0288B8_SQ_VSTMP_RING_ITEMSIZE, 0, 0, 0},
227 {R_0288BC_SQ_PSTMP_RING_ITEMSIZE, 0, 0, 0},
228 {R_0288C0_SQ_FBUF_RING_ITEMSIZE, 0, 0, 0},
229 {R_0288C4_SQ_REDUC_RING_ITEMSIZE, 0, 0, 0},
230 {R_0288C8_SQ_GS_VERT_ITEMSIZE, 0, 0, 0},
231 {R_028A10_VGT_OUTPUT_PATH_CNTL, 0, 0, 0},
232 {R_028A14_VGT_HOS_CNTL, 0, 0, 0},
233 {R_028A18_VGT_HOS_MAX_TESS_LEVEL, 0, 0, 0},
234 {R_028A1C_VGT_HOS_MIN_TESS_LEVEL, 0, 0, 0},
235 {R_028A20_VGT_HOS_REUSE_DEPTH, 0, 0, 0},
236 {R_028A24_VGT_GROUP_PRIM_TYPE, 0, 0, 0},
237 {R_028A28_VGT_GROUP_FIRST_DECR, 0, 0, 0},
238 {R_028A2C_VGT_GROUP_DECR, 0, 0, 0},
239 {R_028A30_VGT_GROUP_VECT_0_CNTL, 0, 0, 0},
240 {R_028A34_VGT_GROUP_VECT_1_CNTL, 0, 0, 0},
241 {R_028A38_VGT_GROUP_VECT_0_FMT_CNTL, 0, 0, 0},
242 {R_028A3C_VGT_GROUP_VECT_1_FMT_CNTL, 0, 0, 0},
243 {R_028A40_VGT_GS_MODE, 0, 0, 0},
244 {R_028A4C_PA_SC_MODE_CNTL, 0, 0, 0},
245 {R_028AB0_VGT_STRMOUT_EN, 0, 0, 0},
246 {R_028AB4_VGT_REUSE_OFF, 0, 0, 0},
247 {R_028AB8_VGT_VTX_CNT_EN, 0, 0, 0},
248 {R_028B20_VGT_STRMOUT_BUFFER_EN, 0, 0, 0},
249 {R_028028_DB_STENCIL_CLEAR, 0, 0, 0},
250 {R_02802C_DB_DEPTH_CLEAR, 0, 0, 0},
251 {GROUP_FORCE_NEW_BLOCK, 0, 0, 0},
252 {R_028040_CB_COLOR0_BASE, REG_FLAG_NEED_BO|REG_FLAG_RV6XX_SBU, SURFACE_BASE_UPDATE_COLOR(0), 0},
253 {GROUP_FORCE_NEW_BLOCK, 0, 0, 0},
254 {R_0280A0_CB_COLOR0_INFO, REG_FLAG_NEED_BO, 0, 0xFFFFFFFF},
255 {R_028060_CB_COLOR0_SIZE, 0, 0, 0},
256 {R_028080_CB_COLOR0_VIEW, 0, 0, 0},
257 {GROUP_FORCE_NEW_BLOCK, 0, 0, 0},
258 {R_0280E0_CB_COLOR0_FRAG, REG_FLAG_NEED_BO, 0, 0},
259 {GROUP_FORCE_NEW_BLOCK, 0, 0, 0},
260 {R_0280C0_CB_COLOR0_TILE, REG_FLAG_NEED_BO, 0, 0},
261 {R_028100_CB_COLOR0_MASK, 0, 0, 0},
262 {GROUP_FORCE_NEW_BLOCK, 0, 0, 0},
263 {R_028044_CB_COLOR1_BASE, REG_FLAG_NEED_BO|REG_FLAG_RV6XX_SBU, SURFACE_BASE_UPDATE_COLOR(1), 0},
264 {GROUP_FORCE_NEW_BLOCK, 0, 0, 0},
265 {R_0280A4_CB_COLOR1_INFO, REG_FLAG_NEED_BO, 0, 0xFFFFFFFF},
266 {R_028064_CB_COLOR1_SIZE, 0, 0, 0},
267 {R_028084_CB_COLOR1_VIEW, 0, 0, 0},
268 {GROUP_FORCE_NEW_BLOCK, 0, 0, 0},
269 {R_0280E4_CB_COLOR1_FRAG, REG_FLAG_NEED_BO, 0, 0},
270 {GROUP_FORCE_NEW_BLOCK, 0, 0, 0},
271 {R_0280C4_CB_COLOR1_TILE, REG_FLAG_NEED_BO, 0, 0},
272 {R_028104_CB_COLOR1_MASK, 0, 0, 0},
273 {GROUP_FORCE_NEW_BLOCK, 0, 0, 0},
274 {R_028048_CB_COLOR2_BASE, REG_FLAG_NEED_BO|REG_FLAG_RV6XX_SBU, SURFACE_BASE_UPDATE_COLOR(2), 0},
275 {GROUP_FORCE_NEW_BLOCK, 0, 0, 0},
276 {R_0280A8_CB_COLOR2_INFO, REG_FLAG_NEED_BO, 0, 0xFFFFFFFF},
277 {R_028068_CB_COLOR2_SIZE, 0, 0, 0},
278 {R_028088_CB_COLOR2_VIEW, 0, 0, 0},
279 {GROUP_FORCE_NEW_BLOCK, 0, 0, 0},
280 {R_0280E8_CB_COLOR2_FRAG, REG_FLAG_NEED_BO, 0, 0},
281 {GROUP_FORCE_NEW_BLOCK, 0, 0, 0},
282 {R_0280C8_CB_COLOR2_TILE, REG_FLAG_NEED_BO, 0, 0},
283 {R_028108_CB_COLOR2_MASK, 0, 0, 0},
284 {GROUP_FORCE_NEW_BLOCK, 0, 0, 0},
285 {R_02804C_CB_COLOR3_BASE, REG_FLAG_NEED_BO|REG_FLAG_RV6XX_SBU, SURFACE_BASE_UPDATE_COLOR(3), 0},
286 {GROUP_FORCE_NEW_BLOCK, 0, 0, 0},
287 {R_0280AC_CB_COLOR3_INFO, REG_FLAG_NEED_BO, 0, 0xFFFFFFFF},
288 {R_02806C_CB_COLOR3_SIZE, 0, 0, 0},
289 {R_02808C_CB_COLOR3_VIEW, 0, 0, 0},
290 {GROUP_FORCE_NEW_BLOCK, 0, 0, 0},
291 {R_0280EC_CB_COLOR3_FRAG, REG_FLAG_NEED_BO, 0, 0},
292 {GROUP_FORCE_NEW_BLOCK, 0, 0, 0},
293 {R_0280CC_CB_COLOR3_TILE, REG_FLAG_NEED_BO, 0, 0},
294 {R_02810C_CB_COLOR3_MASK, 0, 0, 0},
295 {GROUP_FORCE_NEW_BLOCK, 0, 0, 0},
296 {R_028050_CB_COLOR4_BASE, REG_FLAG_NEED_BO|REG_FLAG_RV6XX_SBU, SURFACE_BASE_UPDATE_COLOR(4), 0},
297 {GROUP_FORCE_NEW_BLOCK, 0, 0, 0},
298 {R_0280B0_CB_COLOR4_INFO, REG_FLAG_NEED_BO, 0, 0xFFFFFFFF},
299 {R_028070_CB_COLOR4_SIZE, 0, 0, 0},
300 {R_028090_CB_COLOR4_VIEW, 0, 0, 0},
301 {GROUP_FORCE_NEW_BLOCK, 0, 0, 0},
302 {R_0280F0_CB_COLOR4_FRAG, REG_FLAG_NEED_BO, 0, 0},
303 {GROUP_FORCE_NEW_BLOCK, 0, 0, 0},
304 {R_0280D0_CB_COLOR4_TILE, REG_FLAG_NEED_BO, 0, 0},
305 {R_028110_CB_COLOR4_MASK, 0, 0, 0},
306 {GROUP_FORCE_NEW_BLOCK, 0, 0, 0},
307 {R_028054_CB_COLOR5_BASE, REG_FLAG_NEED_BO|REG_FLAG_RV6XX_SBU, SURFACE_BASE_UPDATE_COLOR(5), 0},
308 {GROUP_FORCE_NEW_BLOCK, 0, 0, 0},
309 {R_0280B4_CB_COLOR5_INFO, REG_FLAG_NEED_BO, 0, 0xFFFFFFFF},
310 {R_028074_CB_COLOR5_SIZE, 0, 0, 0},
311 {R_028094_CB_COLOR5_VIEW, 0, 0, 0},
312 {GROUP_FORCE_NEW_BLOCK, 0, 0, 0},
313 {R_0280F4_CB_COLOR5_FRAG, REG_FLAG_NEED_BO, 0, 0},
314 {GROUP_FORCE_NEW_BLOCK, 0, 0, 0},
315 {R_0280D4_CB_COLOR5_TILE, REG_FLAG_NEED_BO, 0, 0},
316 {R_028114_CB_COLOR5_MASK, 0, 0, 0},
317 {R_028058_CB_COLOR6_BASE, REG_FLAG_NEED_BO|REG_FLAG_RV6XX_SBU, SURFACE_BASE_UPDATE_COLOR(6), 0},
318 {R_0280B8_CB_COLOR6_INFO, REG_FLAG_NEED_BO, 0, 0xFFFFFFFF},
319 {R_028078_CB_COLOR6_SIZE, 0, 0, 0},
320 {R_028098_CB_COLOR6_VIEW, 0, 0, 0},
321 {GROUP_FORCE_NEW_BLOCK, 0, 0, 0},
322 {R_0280F8_CB_COLOR6_FRAG, REG_FLAG_NEED_BO, 0, 0},
323 {GROUP_FORCE_NEW_BLOCK, 0, 0, 0},
324 {R_0280D8_CB_COLOR6_TILE, REG_FLAG_NEED_BO, 0, 0},
325 {R_028118_CB_COLOR6_MASK, 0, 0, 0},
326 {GROUP_FORCE_NEW_BLOCK, 0, 0, 0},
327 {R_02805C_CB_COLOR7_BASE, REG_FLAG_NEED_BO|REG_FLAG_RV6XX_SBU, SURFACE_BASE_UPDATE_COLOR(7), 0},
328 {GROUP_FORCE_NEW_BLOCK, 0, 0, 0},
329 {R_0280BC_CB_COLOR7_INFO, REG_FLAG_NEED_BO, 0, 0xFFFFFFFF},
330 {R_02807C_CB_COLOR7_SIZE, 0, 0, 0},
331 {R_02809C_CB_COLOR7_VIEW, 0, 0, 0},
332 {R_0280FC_CB_COLOR7_FRAG, REG_FLAG_NEED_BO, 0, 0},
333 {R_0280DC_CB_COLOR7_TILE, REG_FLAG_NEED_BO, 0, 0},
334 {R_02811C_CB_COLOR7_MASK, 0, 0, 0},
335 {R_028120_CB_CLEAR_RED, 0, 0, 0},
336 {R_028124_CB_CLEAR_GREEN, 0, 0, 0},
337 {R_028128_CB_CLEAR_BLUE, 0, 0, 0},
338 {R_02812C_CB_CLEAR_ALPHA, 0, 0, 0},
339 {R_028140_ALU_CONST_BUFFER_SIZE_PS_0, REG_FLAG_DIRTY_ALWAYS, 0, 0},
340 {R_028180_ALU_CONST_BUFFER_SIZE_VS_0, REG_FLAG_DIRTY_ALWAYS, 0, 0},
341 {R_028940_ALU_CONST_CACHE_PS_0, REG_FLAG_NEED_BO, S_0085F0_SH_ACTION_ENA(1), 0xFFFFFFFF},
342 {R_028980_ALU_CONST_CACHE_VS_0, REG_FLAG_NEED_BO, S_0085F0_SH_ACTION_ENA(1), 0xFFFFFFFF},
343 {R_02823C_CB_SHADER_MASK, 0, 0, 0},
344 {R_028238_CB_TARGET_MASK, 0, 0, 0},
345 {R_028410_SX_ALPHA_TEST_CONTROL, 0, 0, 0},
346 {R_028414_CB_BLEND_RED, 0, 0, 0},
347 {R_028418_CB_BLEND_GREEN, 0, 0, 0},
348 {R_02841C_CB_BLEND_BLUE, 0, 0, 0},
349 {R_028420_CB_BLEND_ALPHA, 0, 0, 0},
350 {R_028424_CB_FOG_RED, 0, 0, 0},
351 {R_028428_CB_FOG_GREEN, 0, 0, 0},
352 {R_02842C_CB_FOG_BLUE, 0, 0, 0},
353 {R_028430_DB_STENCILREFMASK, 0, 0, 0},
354 {R_028434_DB_STENCILREFMASK_BF, 0, 0, 0},
355 {R_028438_SX_ALPHA_REF, 0, 0, 0},
356 {R_0286DC_SPI_FOG_CNTL, 0, 0, 0},
357 {R_0286E0_SPI_FOG_FUNC_SCALE, 0, 0, 0},
358 {R_0286E4_SPI_FOG_FUNC_BIAS, 0, 0, 0},
359 {R_028780_CB_BLEND0_CONTROL, REG_FLAG_NOT_R600, 0, 0},
360 {R_028784_CB_BLEND1_CONTROL, REG_FLAG_NOT_R600, 0, 0},
361 {R_028788_CB_BLEND2_CONTROL, REG_FLAG_NOT_R600, 0, 0},
362 {R_02878C_CB_BLEND3_CONTROL, REG_FLAG_NOT_R600, 0, 0},
363 {R_028790_CB_BLEND4_CONTROL, REG_FLAG_NOT_R600, 0, 0},
364 {R_028794_CB_BLEND5_CONTROL, REG_FLAG_NOT_R600, 0, 0},
365 {R_028798_CB_BLEND6_CONTROL, REG_FLAG_NOT_R600, 0, 0},
366 {R_02879C_CB_BLEND7_CONTROL, REG_FLAG_NOT_R600, 0, 0},
367 {R_0287A0_CB_SHADER_CONTROL, 0, 0, 0},
368 {R_028800_DB_DEPTH_CONTROL, 0, 0, 0},
369 {R_028804_CB_BLEND_CONTROL, 0, 0, 0},
370 {R_028808_CB_COLOR_CONTROL, 0, 0, 0},
371 {R_02880C_DB_SHADER_CONTROL, 0, 0, 0},
372 {R_028C04_PA_SC_AA_CONFIG, 0, 0, 0},
373 {R_028C1C_PA_SC_AA_SAMPLE_LOCS_MCTX, 0, 0, 0},
374 {R_028C20_PA_SC_AA_SAMPLE_LOCS_8S_WD1_MCTX, 0, 0, 0},
375 {R_028C30_CB_CLRCMP_CONTROL, 0, 0, 0},
376 {R_028C34_CB_CLRCMP_SRC, 0, 0, 0},
377 {R_028C38_CB_CLRCMP_DST, 0, 0, 0},
378 {R_028C3C_CB_CLRCMP_MSK, 0, 0, 0},
379 {R_028C48_PA_SC_AA_MASK, 0, 0, 0},
380 {R_028D2C_DB_SRESULTS_COMPARE_STATE1, 0, 0, 0},
381 {R_028D44_DB_ALPHA_TO_MASK, 0, 0, 0},
382 {R_02800C_DB_DEPTH_BASE, REG_FLAG_NEED_BO|REG_FLAG_RV6XX_SBU, SURFACE_BASE_UPDATE_DEPTH, 0},
383 {R_028000_DB_DEPTH_SIZE, 0, 0, 0},
384 {R_028004_DB_DEPTH_VIEW, 0, 0, 0},
385 {GROUP_FORCE_NEW_BLOCK, 0, 0, 0},
386 {R_028010_DB_DEPTH_INFO, REG_FLAG_NEED_BO, 0, 0},
387 {R_028D0C_DB_RENDER_CONTROL, 0, 0, 0},
388 {R_028D10_DB_RENDER_OVERRIDE, 0, 0, 0},
389 {R_028D24_DB_HTILE_SURFACE, 0, 0, 0},
390 {R_028D30_DB_PRELOAD_CONTROL, 0, 0, 0},
391 {R_028D34_DB_PREFETCH_LIMIT, 0, 0, 0},
392 {R_028030_PA_SC_SCREEN_SCISSOR_TL, 0, 0, 0},
393 {R_028034_PA_SC_SCREEN_SCISSOR_BR, 0, 0, 0},
394 {R_028200_PA_SC_WINDOW_OFFSET, 0, 0, 0},
395 {R_028204_PA_SC_WINDOW_SCISSOR_TL, 0, 0, 0},
396 {R_028208_PA_SC_WINDOW_SCISSOR_BR, 0, 0, 0},
397 {R_02820C_PA_SC_CLIPRECT_RULE, 0, 0, 0},
398 {R_028210_PA_SC_CLIPRECT_0_TL, 0, 0, 0},
399 {R_028214_PA_SC_CLIPRECT_0_BR, 0, 0, 0},
400 {R_028218_PA_SC_CLIPRECT_1_TL, 0, 0, 0},
401 {R_02821C_PA_SC_CLIPRECT_1_BR, 0, 0, 0},
402 {R_028220_PA_SC_CLIPRECT_2_TL, 0, 0, 0},
403 {R_028224_PA_SC_CLIPRECT_2_BR, 0, 0, 0},
404 {R_028228_PA_SC_CLIPRECT_3_TL, 0, 0, 0},
405 {R_02822C_PA_SC_CLIPRECT_3_BR, 0, 0, 0},
406 {R_028230_PA_SC_EDGERULE, 0, 0, 0},
407 {R_028240_PA_SC_GENERIC_SCISSOR_TL, 0, 0, 0},
408 {R_028244_PA_SC_GENERIC_SCISSOR_BR, 0, 0, 0},
409 {R_028250_PA_SC_VPORT_SCISSOR_0_TL, 0, 0, 0},
410 {R_028254_PA_SC_VPORT_SCISSOR_0_BR, 0, 0, 0},
411 {R_0282D0_PA_SC_VPORT_ZMIN_0, 0, 0, 0},
412 {R_0282D4_PA_SC_VPORT_ZMAX_0, 0, 0, 0},
413 {R_02843C_PA_CL_VPORT_XSCALE_0, 0, 0, 0},
414 {R_028440_PA_CL_VPORT_XOFFSET_0, 0, 0, 0},
415 {R_028444_PA_CL_VPORT_YSCALE_0, 0, 0, 0},
416 {R_028448_PA_CL_VPORT_YOFFSET_0, 0, 0, 0},
417 {R_02844C_PA_CL_VPORT_ZSCALE_0, 0, 0, 0},
418 {R_028450_PA_CL_VPORT_ZOFFSET_0, 0, 0, 0},
419 {R_0286D4_SPI_INTERP_CONTROL_0, 0, 0, 0},
420 {R_028810_PA_CL_CLIP_CNTL, 0, 0, 0},
421 {R_028814_PA_SU_SC_MODE_CNTL, 0, 0, 0},
422 {R_028818_PA_CL_VTE_CNTL, 0, 0, 0},
423 {R_02881C_PA_CL_VS_OUT_CNTL, 0, 0, 0},
424 {R_028820_PA_CL_NANINF_CNTL, 0, 0, 0},
425 {R_028A00_PA_SU_POINT_SIZE, 0, 0, 0},
426 {R_028A04_PA_SU_POINT_MINMAX, 0, 0, 0},
427 {R_028A08_PA_SU_LINE_CNTL, 0, 0, 0},
428 {R_028A0C_PA_SC_LINE_STIPPLE, 0, 0, 0},
429 {R_028A48_PA_SC_MPASS_PS_CNTL, 0, 0, 0},
430 {R_028C00_PA_SC_LINE_CNTL, 0, 0, 0},
431 {R_028C08_PA_SU_VTX_CNTL, 0, 0, 0},
432 {R_028C0C_PA_CL_GB_VERT_CLIP_ADJ, 0, 0, 0},
433 {R_028C10_PA_CL_GB_VERT_DISC_ADJ, 0, 0, 0},
434 {R_028C14_PA_CL_GB_HORZ_CLIP_ADJ, 0, 0, 0},
435 {R_028C18_PA_CL_GB_HORZ_DISC_ADJ, 0, 0, 0},
436 {R_028DF8_PA_SU_POLY_OFFSET_DB_FMT_CNTL, 0, 0, 0},
437 {R_028DFC_PA_SU_POLY_OFFSET_CLAMP, 0, 0, 0},
438 {R_028E00_PA_SU_POLY_OFFSET_FRONT_SCALE, 0, 0, 0},
439 {R_028E04_PA_SU_POLY_OFFSET_FRONT_OFFSET, 0, 0, 0},
440 {R_028E08_PA_SU_POLY_OFFSET_BACK_SCALE, 0, 0, 0},
441 {R_028E0C_PA_SU_POLY_OFFSET_BACK_OFFSET, 0, 0, 0},
442 {R_028E20_PA_CL_UCP0_X, 0, 0, 0},
443 {R_028E24_PA_CL_UCP0_Y, 0, 0, 0},
444 {R_028E28_PA_CL_UCP0_Z, 0, 0, 0},
445 {R_028E2C_PA_CL_UCP0_W, 0, 0, 0},
446 {R_028E30_PA_CL_UCP1_X, 0, 0, 0},
447 {R_028E34_PA_CL_UCP1_Y, 0, 0, 0},
448 {R_028E38_PA_CL_UCP1_Z, 0, 0, 0},
449 {R_028E3C_PA_CL_UCP1_W, 0, 0, 0},
450 {R_028E40_PA_CL_UCP2_X, 0, 0, 0},
451 {R_028E44_PA_CL_UCP2_Y, 0, 0, 0},
452 {R_028E48_PA_CL_UCP2_Z, 0, 0, 0},
453 {R_028E4C_PA_CL_UCP2_W, 0, 0, 0},
454 {R_028E50_PA_CL_UCP3_X, 0, 0, 0},
455 {R_028E54_PA_CL_UCP3_Y, 0, 0, 0},
456 {R_028E58_PA_CL_UCP3_Z, 0, 0, 0},
457 {R_028E5C_PA_CL_UCP3_W, 0, 0, 0},
458 {R_028E60_PA_CL_UCP4_X, 0, 0, 0},
459 {R_028E64_PA_CL_UCP4_Y, 0, 0, 0},
460 {R_028E68_PA_CL_UCP4_Z, 0, 0, 0},
461 {R_028E6C_PA_CL_UCP4_W, 0, 0, 0},
462 {R_028E70_PA_CL_UCP5_X, 0, 0, 0},
463 {R_028E74_PA_CL_UCP5_Y, 0, 0, 0},
464 {R_028E78_PA_CL_UCP5_Z, 0, 0, 0},
465 {R_028E7C_PA_CL_UCP5_W, 0, 0, 0},
466 {R_028380_SQ_VTX_SEMANTIC_0, 0, 0, 0},
467 {R_028384_SQ_VTX_SEMANTIC_1, 0, 0, 0},
468 {R_028388_SQ_VTX_SEMANTIC_2, 0, 0, 0},
469 {R_02838C_SQ_VTX_SEMANTIC_3, 0, 0, 0},
470 {R_028390_SQ_VTX_SEMANTIC_4, 0, 0, 0},
471 {R_028394_SQ_VTX_SEMANTIC_5, 0, 0, 0},
472 {R_028398_SQ_VTX_SEMANTIC_6, 0, 0, 0},
473 {R_02839C_SQ_VTX_SEMANTIC_7, 0, 0, 0},
474 {R_0283A0_SQ_VTX_SEMANTIC_8, 0, 0, 0},
475 {R_0283A4_SQ_VTX_SEMANTIC_9, 0, 0, 0},
476 {R_0283A8_SQ_VTX_SEMANTIC_10, 0, 0, 0},
477 {R_0283AC_SQ_VTX_SEMANTIC_11, 0, 0, 0},
478 {R_0283B0_SQ_VTX_SEMANTIC_12, 0, 0, 0},
479 {R_0283B4_SQ_VTX_SEMANTIC_13, 0, 0, 0},
480 {R_0283B8_SQ_VTX_SEMANTIC_14, 0, 0, 0},
481 {R_0283BC_SQ_VTX_SEMANTIC_15, 0, 0, 0},
482 {R_0283C0_SQ_VTX_SEMANTIC_16, 0, 0, 0},
483 {R_0283C4_SQ_VTX_SEMANTIC_17, 0, 0, 0},
484 {R_0283C8_SQ_VTX_SEMANTIC_18, 0, 0, 0},
485 {R_0283CC_SQ_VTX_SEMANTIC_19, 0, 0, 0},
486 {R_0283D0_SQ_VTX_SEMANTIC_20, 0, 0, 0},
487 {R_0283D4_SQ_VTX_SEMANTIC_21, 0, 0, 0},
488 {R_0283D8_SQ_VTX_SEMANTIC_22, 0, 0, 0},
489 {R_0283DC_SQ_VTX_SEMANTIC_23, 0, 0, 0},
490 {R_0283E0_SQ_VTX_SEMANTIC_24, 0, 0, 0},
491 {R_0283E4_SQ_VTX_SEMANTIC_25, 0, 0, 0},
492 {R_0283E8_SQ_VTX_SEMANTIC_26, 0, 0, 0},
493 {R_0283EC_SQ_VTX_SEMANTIC_27, 0, 0, 0},
494 {R_0283F0_SQ_VTX_SEMANTIC_28, 0, 0, 0},
495 {R_0283F4_SQ_VTX_SEMANTIC_29, 0, 0, 0},
496 {R_0283F8_SQ_VTX_SEMANTIC_30, 0, 0, 0},
497 {R_0283FC_SQ_VTX_SEMANTIC_31, 0, 0, 0},
498 {R_028614_SPI_VS_OUT_ID_0, 0, 0, 0},
499 {R_028618_SPI_VS_OUT_ID_1, 0, 0, 0},
500 {R_02861C_SPI_VS_OUT_ID_2, 0, 0, 0},
501 {R_028620_SPI_VS_OUT_ID_3, 0, 0, 0},
502 {R_028624_SPI_VS_OUT_ID_4, 0, 0, 0},
503 {R_028628_SPI_VS_OUT_ID_5, 0, 0, 0},
504 {R_02862C_SPI_VS_OUT_ID_6, 0, 0, 0},
505 {R_028630_SPI_VS_OUT_ID_7, 0, 0, 0},
506 {R_028634_SPI_VS_OUT_ID_8, 0, 0, 0},
507 {R_028638_SPI_VS_OUT_ID_9, 0, 0, 0},
508 {R_0286C4_SPI_VS_OUT_CONFIG, 0, 0, 0},
509 {GROUP_FORCE_NEW_BLOCK, 0, 0, 0},
510 {R_028858_SQ_PGM_START_VS, REG_FLAG_NEED_BO, S_0085F0_SH_ACTION_ENA(1), 0xFFFFFFFF},
511 {GROUP_FORCE_NEW_BLOCK, 0, 0, 0},
512 {R_028868_SQ_PGM_RESOURCES_VS, 0, 0, 0},
513 {GROUP_FORCE_NEW_BLOCK, 0, 0, 0},
514 {R_028894_SQ_PGM_START_FS, REG_FLAG_NEED_BO, S_0085F0_SH_ACTION_ENA(1), 0xFFFFFFFF},
515 {GROUP_FORCE_NEW_BLOCK, 0, 0, 0},
516 {R_0288A4_SQ_PGM_RESOURCES_FS, 0, 0, 0},
517 {R_0288D0_SQ_PGM_CF_OFFSET_VS, 0, 0, 0},
518 {R_0288DC_SQ_PGM_CF_OFFSET_FS, 0, 0, 0},
519 {R_028644_SPI_PS_INPUT_CNTL_0, 0, 0, 0},
520 {R_028648_SPI_PS_INPUT_CNTL_1, 0, 0, 0},
521 {R_02864C_SPI_PS_INPUT_CNTL_2, 0, 0, 0},
522 {R_028650_SPI_PS_INPUT_CNTL_3, 0, 0, 0},
523 {R_028654_SPI_PS_INPUT_CNTL_4, 0, 0, 0},
524 {R_028658_SPI_PS_INPUT_CNTL_5, 0, 0, 0},
525 {R_02865C_SPI_PS_INPUT_CNTL_6, 0, 0, 0},
526 {R_028660_SPI_PS_INPUT_CNTL_7, 0, 0, 0},
527 {R_028664_SPI_PS_INPUT_CNTL_8, 0, 0, 0},
528 {R_028668_SPI_PS_INPUT_CNTL_9, 0, 0, 0},
529 {R_02866C_SPI_PS_INPUT_CNTL_10, 0, 0, 0},
530 {R_028670_SPI_PS_INPUT_CNTL_11, 0, 0, 0},
531 {R_028674_SPI_PS_INPUT_CNTL_12, 0, 0, 0},
532 {R_028678_SPI_PS_INPUT_CNTL_13, 0, 0, 0},
533 {R_02867C_SPI_PS_INPUT_CNTL_14, 0, 0, 0},
534 {R_028680_SPI_PS_INPUT_CNTL_15, 0, 0, 0},
535 {R_028684_SPI_PS_INPUT_CNTL_16, 0, 0, 0},
536 {R_028688_SPI_PS_INPUT_CNTL_17, 0, 0, 0},
537 {R_02868C_SPI_PS_INPUT_CNTL_18, 0, 0, 0},
538 {R_028690_SPI_PS_INPUT_CNTL_19, 0, 0, 0},
539 {R_028694_SPI_PS_INPUT_CNTL_20, 0, 0, 0},
540 {R_028698_SPI_PS_INPUT_CNTL_21, 0, 0, 0},
541 {R_02869C_SPI_PS_INPUT_CNTL_22, 0, 0, 0},
542 {R_0286A0_SPI_PS_INPUT_CNTL_23, 0, 0, 0},
543 {R_0286A4_SPI_PS_INPUT_CNTL_24, 0, 0, 0},
544 {R_0286A8_SPI_PS_INPUT_CNTL_25, 0, 0, 0},
545 {R_0286AC_SPI_PS_INPUT_CNTL_26, 0, 0, 0},
546 {R_0286B0_SPI_PS_INPUT_CNTL_27, 0, 0, 0},
547 {R_0286B4_SPI_PS_INPUT_CNTL_28, 0, 0, 0},
548 {R_0286B8_SPI_PS_INPUT_CNTL_29, 0, 0, 0},
549 {R_0286BC_SPI_PS_INPUT_CNTL_30, 0, 0, 0},
550 {R_0286C0_SPI_PS_INPUT_CNTL_31, 0, 0, 0},
551 {R_0286CC_SPI_PS_IN_CONTROL_0, 0, 0, 0},
552 {R_0286D0_SPI_PS_IN_CONTROL_1, 0, 0, 0},
553 {R_0286D8_SPI_INPUT_Z, 0, 0, 0},
554 {GROUP_FORCE_NEW_BLOCK, 0, 0, 0},
555 {R_028840_SQ_PGM_START_PS, REG_FLAG_NEED_BO, S_0085F0_SH_ACTION_ENA(1), 0xFFFFFFFF},
556 {GROUP_FORCE_NEW_BLOCK, 0, 0, 0},
557 {R_028850_SQ_PGM_RESOURCES_PS, 0, 0, 0},
558 {R_028854_SQ_PGM_EXPORTS_PS, 0, 0, 0},
559 {R_0288CC_SQ_PGM_CF_OFFSET_PS, 0, 0, 0},
560 {R_028400_VGT_MAX_VTX_INDX, 0, 0, 0},
561 {R_028404_VGT_MIN_VTX_INDX, 0, 0, 0},
562 {R_028408_VGT_INDX_OFFSET, 0, 0, 0},
563 {R_02840C_VGT_MULTI_PRIM_IB_RESET_INDX, 0, 0, 0},
564 {R_028A84_VGT_PRIMITIVEID_EN, 0, 0, 0},
565 {R_028A94_VGT_MULTI_PRIM_IB_RESET_EN, 0, 0, 0},
566 {R_028AA0_VGT_INSTANCE_STEP_RATE_0, 0, 0, 0},
567 {R_028AA4_VGT_INSTANCE_STEP_RATE_1, 0, 0, 0},
568 };
569
570 /* SHADER RESOURCE R600/R700 */
571 int r600_resource_init(struct r600_context *ctx, struct r600_range *range, unsigned offset, unsigned nblocks, unsigned stride, struct r600_reg *reg, int nreg, unsigned offset_base)
572 {
573 int i;
574 struct r600_block *block;
575 range->blocks = calloc(nblocks, sizeof(struct r600_block *));
576 if (range->blocks == NULL)
577 return -ENOMEM;
578
579 reg[0].offset += offset;
580 for (i = 0; i < nblocks; i++) {
581 block = calloc(1, sizeof(struct r600_block));
582 if (block == NULL) {
583 return -ENOMEM;
584 }
585 ctx->nblocks++;
586 range->blocks[i] = block;
587 r600_init_block(ctx, block, reg, 0, nreg, PKT3_SET_RESOURCE, offset_base);
588
589 reg[0].offset += stride;
590 }
591 return 0;
592 }
593
594
595 static int r600_resource_range_init(struct r600_context *ctx, struct r600_range *range, unsigned offset, unsigned nblocks, unsigned stride)
596 {
597 struct r600_reg r600_shader_resource[] = {
598 {R_038000_RESOURCE0_WORD0, 0, 0, 0},
599 {R_038004_RESOURCE0_WORD1, 0, 0, 0},
600 {R_038008_RESOURCE0_WORD2, REG_FLAG_NEED_BO, S_0085F0_TC_ACTION_ENA(1) | S_0085F0_VC_ACTION_ENA(1), 0xFFFFFFFF},
601 {R_03800C_RESOURCE0_WORD3, REG_FLAG_NEED_BO, S_0085F0_TC_ACTION_ENA(1) | S_0085F0_VC_ACTION_ENA(1), 0xFFFFFFFF},
602 {R_038010_RESOURCE0_WORD4, 0, 0, 0},
603 {R_038014_RESOURCE0_WORD5, 0, 0, 0},
604 {R_038018_RESOURCE0_WORD6, 0, 0, 0},
605 };
606 unsigned nreg = Elements(r600_shader_resource);
607
608 return r600_resource_init(ctx, range, offset, nblocks, stride, r600_shader_resource, nreg, R600_RESOURCE_OFFSET);
609 }
610
611 /* SHADER SAMPLER R600/R700 */
612 static int r600_state_sampler_init(struct r600_context *ctx, u32 offset)
613 {
614 struct r600_reg r600_shader_sampler[] = {
615 {R_03C000_SQ_TEX_SAMPLER_WORD0_0, 0, 0, 0},
616 {R_03C004_SQ_TEX_SAMPLER_WORD1_0, 0, 0, 0},
617 {R_03C008_SQ_TEX_SAMPLER_WORD2_0, 0, 0, 0},
618 };
619 unsigned nreg = Elements(r600_shader_sampler);
620
621 for (int i = 0; i < nreg; i++) {
622 r600_shader_sampler[i].offset += offset;
623 }
624 return r600_context_add_block(ctx, r600_shader_sampler, nreg, PKT3_SET_SAMPLER, R600_SAMPLER_OFFSET);
625 }
626
627 /* SHADER SAMPLER BORDER R600/R700 */
628 static int r600_state_sampler_border_init(struct r600_context *ctx, u32 offset)
629 {
630 struct r600_reg r600_shader_sampler_border[] = {
631 {R_00A400_TD_PS_SAMPLER0_BORDER_RED, 0, 0, 0},
632 {R_00A404_TD_PS_SAMPLER0_BORDER_GREEN, 0, 0, 0},
633 {R_00A408_TD_PS_SAMPLER0_BORDER_BLUE, 0, 0, 0},
634 {R_00A40C_TD_PS_SAMPLER0_BORDER_ALPHA, 0, 0, 0},
635 };
636 unsigned nreg = Elements(r600_shader_sampler_border);
637
638 for (int i = 0; i < nreg; i++) {
639 r600_shader_sampler_border[i].offset += offset;
640 }
641 return r600_context_add_block(ctx, r600_shader_sampler_border, nreg, PKT3_SET_CONFIG_REG, R600_CONFIG_REG_OFFSET);
642 }
643
644 static int r600_loop_const_init(struct r600_context *ctx, u32 offset)
645 {
646 unsigned nreg = 32;
647 struct r600_reg r600_loop_consts[32];
648 int i;
649
650 for (i = 0; i < nreg; i++) {
651 r600_loop_consts[i].offset = R600_LOOP_CONST_OFFSET + ((offset + i) * 4);
652 r600_loop_consts[i].flags = REG_FLAG_DIRTY_ALWAYS;
653 r600_loop_consts[i].flush_flags = 0;
654 r600_loop_consts[i].flush_mask = 0;
655 }
656 return r600_context_add_block(ctx, r600_loop_consts, nreg, PKT3_SET_LOOP_CONST, R600_LOOP_CONST_OFFSET);
657 }
658
659 static void r600_context_clear_fenced_bo(struct r600_context *ctx)
660 {
661 struct radeon_bo *bo, *tmp;
662
663 LIST_FOR_EACH_ENTRY_SAFE(bo, tmp, &ctx->fenced_bo, fencedlist) {
664 LIST_DELINIT(&bo->fencedlist);
665 bo->fence = 0;
666 bo->ctx = NULL;
667 }
668 }
669
670 static void r600_free_resource_range(struct r600_context *ctx, struct r600_range *range, int nblocks)
671 {
672 struct r600_block *block;
673 int i;
674 for (i = 0; i < nblocks; i++) {
675 block = range->blocks[i];
676 if (block) {
677 for (int k = 1; k <= block->nbo; k++)
678 r600_bo_reference(ctx->radeon, &block->reloc[k].bo, NULL);
679 free(block);
680 }
681 }
682 free(range->blocks);
683
684 }
685
686 /* initialize */
687 void r600_context_fini(struct r600_context *ctx)
688 {
689 struct r600_block *block;
690 struct r600_range *range;
691
692 for (int i = 0; i < NUM_RANGES; i++) {
693 if (!ctx->range[i].blocks)
694 continue;
695 for (int j = 0; j < (1 << HASH_SHIFT); j++) {
696 block = ctx->range[i].blocks[j];
697 if (block) {
698 for (int k = 0, offset = block->start_offset; k < block->nreg; k++, offset += 4) {
699 range = &ctx->range[CTX_RANGE_ID(offset)];
700 range->blocks[CTX_BLOCK_ID(offset)] = NULL;
701 }
702 for (int k = 1; k <= block->nbo; k++) {
703 r600_bo_reference(ctx->radeon, &block->reloc[k].bo, NULL);
704 }
705 free(block);
706 }
707 }
708 free(ctx->range[i].blocks);
709 }
710 r600_free_resource_range(ctx, &ctx->ps_resources, ctx->num_ps_resources);
711 r600_free_resource_range(ctx, &ctx->vs_resources, ctx->num_vs_resources);
712 r600_free_resource_range(ctx, &ctx->fs_resources, ctx->num_fs_resources);
713 free(ctx->range);
714 free(ctx->blocks);
715 free(ctx->reloc);
716 free(ctx->bo);
717 free(ctx->pm4);
718
719 r600_context_clear_fenced_bo(ctx);
720 memset(ctx, 0, sizeof(struct r600_context));
721 }
722
723 static void r600_add_resource_block(struct r600_context *ctx, struct r600_range *range, int num_blocks, int *index)
724 {
725 int c = *index;
726 for (int j = 0; j < num_blocks; j++) {
727 if (!range->blocks[j])
728 continue;
729
730 ctx->blocks[c++] = range->blocks[j];
731 }
732 *index = c;
733 }
734
735 int r600_setup_block_table(struct r600_context *ctx)
736 {
737 /* setup block table */
738 int c = 0;
739 ctx->blocks = calloc(ctx->nblocks, sizeof(void*));
740 if (!ctx->blocks)
741 return -ENOMEM;
742 for (int i = 0; i < NUM_RANGES; i++) {
743 if (!ctx->range[i].blocks)
744 continue;
745 for (int j = 0, add; j < (1 << HASH_SHIFT); j++) {
746 if (!ctx->range[i].blocks[j])
747 continue;
748
749 add = 1;
750 for (int k = 0; k < c; k++) {
751 if (ctx->blocks[k] == ctx->range[i].blocks[j]) {
752 add = 0;
753 break;
754 }
755 }
756 if (add) {
757 assert(c < ctx->nblocks);
758 ctx->blocks[c++] = ctx->range[i].blocks[j];
759 j += (ctx->range[i].blocks[j]->nreg) - 1;
760 }
761 }
762 }
763
764 r600_add_resource_block(ctx, &ctx->ps_resources, ctx->num_ps_resources, &c);
765 r600_add_resource_block(ctx, &ctx->vs_resources, ctx->num_vs_resources, &c);
766 r600_add_resource_block(ctx, &ctx->fs_resources, ctx->num_fs_resources, &c);
767 return 0;
768 }
769
770 int r600_context_init(struct r600_context *ctx, struct radeon *radeon)
771 {
772 int r;
773
774 memset(ctx, 0, sizeof(struct r600_context));
775 ctx->radeon = radeon;
776 LIST_INITHEAD(&ctx->query_list);
777
778 /* init dirty list */
779 LIST_INITHEAD(&ctx->dirty);
780 LIST_INITHEAD(&ctx->enable_list);
781
782 ctx->range = calloc(NUM_RANGES, sizeof(struct r600_range));
783 if (!ctx->range) {
784 r = -ENOMEM;
785 goto out_err;
786 }
787
788 /* add blocks */
789 r = r600_context_add_block(ctx, r600_config_reg_list,
790 Elements(r600_config_reg_list), PKT3_SET_CONFIG_REG, R600_CONFIG_REG_OFFSET);
791 if (r)
792 goto out_err;
793 r = r600_context_add_block(ctx, r600_context_reg_list,
794 Elements(r600_context_reg_list), PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET);
795 if (r)
796 goto out_err;
797 r = r600_context_add_block(ctx, r600_ctl_const_list,
798 Elements(r600_ctl_const_list), PKT3_SET_CTL_CONST, R600_CTL_CONST_OFFSET);
799 if (r)
800 goto out_err;
801
802 /* PS SAMPLER BORDER */
803 for (int j = 0, offset = 0; j < 18; j++, offset += 0x10) {
804 r = r600_state_sampler_border_init(ctx, offset);
805 if (r)
806 goto out_err;
807 }
808
809 /* VS SAMPLER BORDER */
810 for (int j = 0, offset = 0x200; j < 18; j++, offset += 0x10) {
811 r = r600_state_sampler_border_init(ctx, offset);
812 if (r)
813 goto out_err;
814 }
815 /* PS SAMPLER */
816 for (int j = 0, offset = 0; j < 18; j++, offset += 0xC) {
817 r = r600_state_sampler_init(ctx, offset);
818 if (r)
819 goto out_err;
820 }
821 /* VS SAMPLER */
822 for (int j = 0, offset = 0xD8; j < 18; j++, offset += 0xC) {
823 r = r600_state_sampler_init(ctx, offset);
824 if (r)
825 goto out_err;
826 }
827
828 ctx->num_ps_resources = 160;
829 ctx->num_vs_resources = 160;
830 ctx->num_fs_resources = 16;
831 r = r600_resource_range_init(ctx, &ctx->ps_resources, 0, 160, 0x1c);
832 if (r)
833 goto out_err;
834 r = r600_resource_range_init(ctx, &ctx->vs_resources, 0x1180, 160, 0x1c);
835 if (r)
836 goto out_err;
837 r = r600_resource_range_init(ctx, &ctx->fs_resources, 0x2300, 16, 0x1c);
838 if (r)
839 goto out_err;
840
841 /* PS loop const */
842 r600_loop_const_init(ctx, 0);
843 /* VS loop const */
844 r600_loop_const_init(ctx, 32);
845
846 r = r600_setup_block_table(ctx);
847 if (r)
848 goto out_err;
849
850 /* allocate cs variables */
851 ctx->nreloc = RADEON_CTX_MAX_PM4;
852 ctx->reloc = calloc(ctx->nreloc, sizeof(struct r600_reloc));
853 if (ctx->reloc == NULL) {
854 r = -ENOMEM;
855 goto out_err;
856 }
857 ctx->bo = calloc(ctx->nreloc, sizeof(void *));
858 if (ctx->bo == NULL) {
859 r = -ENOMEM;
860 goto out_err;
861 }
862 ctx->pm4_ndwords = RADEON_CTX_MAX_PM4;
863 ctx->pm4 = calloc(ctx->pm4_ndwords, 4);
864 if (ctx->pm4 == NULL) {
865 r = -ENOMEM;
866 goto out_err;
867 }
868
869 r600_init_cs(ctx);
870 /* save 16dwords space for fence mecanism */
871 ctx->pm4_ndwords -= 16;
872
873 LIST_INITHEAD(&ctx->fenced_bo);
874
875 ctx->max_db = 4;
876
877 return 0;
878 out_err:
879 r600_context_fini(ctx);
880 return r;
881 }
882
883 /* Flushes all surfaces */
884 void r600_context_flush_all(struct r600_context *ctx, unsigned flush_flags)
885 {
886 unsigned ndwords = 5;
887
888 if ((ctx->pm4_dirty_cdwords + ndwords + ctx->pm4_cdwords) > ctx->pm4_ndwords) {
889 /* need to flush */
890 r600_context_flush(ctx);
891 }
892
893 ctx->pm4[ctx->pm4_cdwords++] = PKT3(PKT3_SURFACE_SYNC, 3, ctx->predicate_drawing);
894 ctx->pm4[ctx->pm4_cdwords++] = flush_flags; /* CP_COHER_CNTL */
895 ctx->pm4[ctx->pm4_cdwords++] = 0xffffffff; /* CP_COHER_SIZE */
896 ctx->pm4[ctx->pm4_cdwords++] = 0; /* CP_COHER_BASE */
897 ctx->pm4[ctx->pm4_cdwords++] = 0x0000000A; /* POLL_INTERVAL */
898 }
899
900 void r600_context_bo_flush(struct r600_context *ctx, unsigned flush_flags,
901 unsigned flush_mask, struct r600_bo *rbo)
902 {
903 struct radeon_bo *bo;
904
905 bo = rbo->bo;
906 /* if bo has already been flushed */
907 if (!(~bo->last_flush & flush_flags)) {
908 bo->last_flush &= flush_mask;
909 return;
910 }
911
912 if ((ctx->radeon->family < CHIP_RV770) &&
913 (G_0085F0_CB_ACTION_ENA(flush_flags) ||
914 G_0085F0_DB_ACTION_ENA(flush_flags))) {
915 if (ctx->flags & R600_CONTEXT_CHECK_EVENT_FLUSH) {
916 /* the rv670 seems to fail fbo-generatemipmap unless we flush the CB1 dest base ena */
917 if ((bo->binding & BO_BOUND_TEXTURE) &&
918 (flush_flags & S_0085F0_CB_ACTION_ENA(1))) {
919 if ((ctx->radeon->family == CHIP_RV670) ||
920 (ctx->radeon->family == CHIP_RS780) ||
921 (ctx->radeon->family == CHIP_RS880)) {
922 ctx->pm4[ctx->pm4_cdwords++] = PKT3(PKT3_SURFACE_SYNC, 3, ctx->predicate_drawing);
923 ctx->pm4[ctx->pm4_cdwords++] = S_0085F0_CB1_DEST_BASE_ENA(1); /* CP_COHER_CNTL */
924 ctx->pm4[ctx->pm4_cdwords++] = 0xffffffff; /* CP_COHER_SIZE */
925 ctx->pm4[ctx->pm4_cdwords++] = 0; /* CP_COHER_BASE */
926 ctx->pm4[ctx->pm4_cdwords++] = 0x0000000A; /* POLL_INTERVAL */
927 }
928 }
929
930 ctx->pm4[ctx->pm4_cdwords++] = PKT3(PKT3_EVENT_WRITE, 0, ctx->predicate_drawing);
931 ctx->pm4[ctx->pm4_cdwords++] = EVENT_TYPE(EVENT_TYPE_CACHE_FLUSH_AND_INV_EVENT) | EVENT_INDEX(0);
932 ctx->flags &= ~R600_CONTEXT_CHECK_EVENT_FLUSH;
933 }
934 } else {
935 ctx->pm4[ctx->pm4_cdwords++] = PKT3(PKT3_SURFACE_SYNC, 3, ctx->predicate_drawing);
936 ctx->pm4[ctx->pm4_cdwords++] = flush_flags;
937 ctx->pm4[ctx->pm4_cdwords++] = (bo->size + 255) >> 8;
938 ctx->pm4[ctx->pm4_cdwords++] = 0x00000000;
939 ctx->pm4[ctx->pm4_cdwords++] = 0x0000000A;
940 ctx->pm4[ctx->pm4_cdwords++] = PKT3(PKT3_NOP, 0, ctx->predicate_drawing);
941 ctx->pm4[ctx->pm4_cdwords++] = bo->reloc_id;
942 }
943 bo->last_flush = (bo->last_flush | flush_flags) & flush_mask;
944 }
945
946 void r600_context_bo_reloc(struct r600_context *ctx, u32 *pm4, struct r600_bo *rbo)
947 {
948 struct radeon_bo *bo;
949
950 bo = rbo->bo;
951 assert(bo != NULL);
952 if (bo->reloc) {
953 *pm4 = bo->reloc_id;
954 return;
955 }
956 bo->reloc = &ctx->reloc[ctx->creloc];
957 bo->reloc_id = ctx->creloc * sizeof(struct r600_reloc) / 4;
958 ctx->reloc[ctx->creloc].handle = bo->handle;
959 ctx->reloc[ctx->creloc].read_domain = rbo->domains & (RADEON_GEM_DOMAIN_GTT | RADEON_GEM_DOMAIN_VRAM);
960 ctx->reloc[ctx->creloc].write_domain = rbo->domains & (RADEON_GEM_DOMAIN_GTT | RADEON_GEM_DOMAIN_VRAM);
961 ctx->reloc[ctx->creloc].flags = 0;
962 radeon_bo_reference(ctx->radeon, &ctx->bo[ctx->creloc], bo);
963 rbo->fence = ctx->radeon->fence;
964 ctx->creloc++;
965 /* set PKT3 to point to proper reloc */
966 *pm4 = bo->reloc_id;
967 }
968
969 void r600_context_reg(struct r600_context *ctx,
970 unsigned offset, unsigned value,
971 unsigned mask)
972 {
973 struct r600_range *range;
974 struct r600_block *block;
975 unsigned id;
976 unsigned new_val;
977 int dirty;
978
979 range = &ctx->range[CTX_RANGE_ID(offset)];
980 block = range->blocks[CTX_BLOCK_ID(offset)];
981 id = (offset - block->start_offset) >> 2;
982
983 dirty = block->status & R600_BLOCK_STATUS_DIRTY;
984
985 new_val = block->reg[id];
986 new_val &= ~mask;
987 new_val |= value;
988 if (new_val != block->reg[id]) {
989 dirty |= R600_BLOCK_STATUS_DIRTY;
990 block->reg[id] = new_val;
991 }
992 if (dirty)
993 r600_context_dirty_block(ctx, block, dirty, id);
994 }
995
996 void r600_context_dirty_block(struct r600_context *ctx,
997 struct r600_block *block,
998 int dirty, int index)
999 {
1000 if ((index + 1) > block->nreg_dirty)
1001 block->nreg_dirty = index + 1;
1002
1003 if ((dirty != (block->status & R600_BLOCK_STATUS_DIRTY)) || !(block->status & R600_BLOCK_STATUS_ENABLED)) {
1004 block->status |= R600_BLOCK_STATUS_DIRTY;
1005 ctx->pm4_dirty_cdwords += block->pm4_ndwords + block->pm4_flush_ndwords;
1006 if (!(block->status & R600_BLOCK_STATUS_ENABLED)) {
1007 block->status |= R600_BLOCK_STATUS_ENABLED;
1008 LIST_ADDTAIL(&block->enable_list, &ctx->enable_list);
1009 }
1010 LIST_ADDTAIL(&block->list,&ctx->dirty);
1011 }
1012 }
1013
1014 void r600_context_pipe_state_set(struct r600_context *ctx, struct r600_pipe_state *state)
1015 {
1016 struct r600_block *block;
1017 unsigned new_val;
1018 int dirty;
1019 for (int i = 0; i < state->nregs; i++) {
1020 unsigned id, reloc_id;
1021 struct r600_pipe_reg *reg = &state->regs[i];
1022
1023 block = reg->block;
1024 id = reg->id;
1025
1026 dirty = block->status & R600_BLOCK_STATUS_DIRTY;
1027
1028 new_val = block->reg[id];
1029 new_val &= ~reg->mask;
1030 new_val |= reg->value;
1031 if (new_val != block->reg[id]) {
1032 block->reg[id] = new_val;
1033 dirty |= R600_BLOCK_STATUS_DIRTY;
1034 }
1035 if (block->flags & REG_FLAG_DIRTY_ALWAYS)
1036 dirty |= R600_BLOCK_STATUS_DIRTY;
1037 if (block->pm4_bo_index[id]) {
1038 /* find relocation */
1039 reloc_id = block->pm4_bo_index[id];
1040 r600_bo_reference(ctx->radeon, &block->reloc[reloc_id].bo, reg->bo);
1041 reg->bo->fence = ctx->radeon->fence;
1042 /* always force dirty for relocs for now */
1043 dirty |= R600_BLOCK_STATUS_DIRTY;
1044 }
1045
1046 if (dirty)
1047 r600_context_dirty_block(ctx, block, dirty, id);
1048 }
1049 }
1050
1051 void r600_context_pipe_state_set_resource(struct r600_context *ctx, struct r600_pipe_resource_state *state, struct r600_block *block)
1052 {
1053 int i;
1054 int dirty;
1055 int num_regs = ctx->radeon->chip_class >= EVERGREEN ? 8 : 7;
1056 boolean is_vertex;
1057
1058 if (state == NULL) {
1059 block->status &= ~(R600_BLOCK_STATUS_ENABLED | R600_BLOCK_STATUS_DIRTY);
1060 if (block->reloc[1].bo)
1061 block->reloc[1].bo->bo->binding &= ~BO_BOUND_TEXTURE;
1062
1063 r600_bo_reference(ctx->radeon, &block->reloc[1].bo, NULL);
1064 r600_bo_reference(ctx->radeon , &block->reloc[2].bo, NULL);
1065 LIST_DELINIT(&block->list);
1066 LIST_DELINIT(&block->enable_list);
1067 return;
1068 }
1069
1070 is_vertex = ((state->val[num_regs-1] & 0xc0000000) == 0xc0000000);
1071 dirty = block->status & R600_BLOCK_STATUS_DIRTY;
1072
1073 if (memcmp(block->reg, state->val, num_regs*4)) {
1074 memcpy(block->reg, state->val, num_regs * 4);
1075 dirty |= R600_BLOCK_STATUS_DIRTY;
1076 }
1077
1078 /* if no BOs on block, force dirty */
1079 if (!block->reloc[1].bo || !block->reloc[2].bo)
1080 dirty |= R600_BLOCK_STATUS_DIRTY;
1081
1082 if (!dirty) {
1083 if (is_vertex) {
1084 if ((block->reloc[1].bo->bo->handle != state->bo[0]->bo->handle) ||
1085 (block->reloc[2].bo->bo->handle != state->bo[0]->bo->handle))
1086 dirty |= R600_BLOCK_STATUS_DIRTY;
1087 } else {
1088 if ((block->reloc[1].bo->bo->handle != state->bo[0]->bo->handle) ||
1089 (block->reloc[2].bo->bo->handle != state->bo[1]->bo->handle))
1090 dirty |= R600_BLOCK_STATUS_DIRTY;
1091 }
1092 }
1093 if (!dirty) {
1094 if (is_vertex)
1095 state->bo[0]->fence = ctx->radeon->fence;
1096 else {
1097 state->bo[0]->fence = ctx->radeon->fence;
1098 state->bo[1]->fence = ctx->radeon->fence;
1099 }
1100 } else {
1101 if (is_vertex) {
1102 /* VERTEX RESOURCE, we preted there is 2 bo to relocate so
1103 * we have single case btw VERTEX & TEXTURE resource
1104 */
1105 r600_bo_reference(ctx->radeon, &block->reloc[1].bo, state->bo[0]);
1106 r600_bo_reference(ctx->radeon, &block->reloc[2].bo, state->bo[0]);
1107 state->bo[0]->fence = ctx->radeon->fence;
1108 } else {
1109 /* TEXTURE RESOURCE */
1110 r600_bo_reference(ctx->radeon, &block->reloc[1].bo, state->bo[0]);
1111 r600_bo_reference(ctx->radeon, &block->reloc[2].bo, state->bo[1]);
1112 state->bo[0]->fence = ctx->radeon->fence;
1113 state->bo[1]->fence = ctx->radeon->fence;
1114 state->bo[0]->bo->binding |= BO_BOUND_TEXTURE;
1115 }
1116 }
1117 if (dirty)
1118 r600_context_dirty_block(ctx, block, dirty, num_regs - 1);
1119 }
1120
1121 void r600_context_pipe_state_set_ps_resource(struct r600_context *ctx, struct r600_pipe_resource_state *state, unsigned rid)
1122 {
1123 struct r600_block *block = ctx->ps_resources.blocks[rid];
1124
1125 r600_context_pipe_state_set_resource(ctx, state, block);
1126 }
1127
1128 void r600_context_pipe_state_set_vs_resource(struct r600_context *ctx, struct r600_pipe_resource_state *state, unsigned rid)
1129 {
1130 struct r600_block *block = ctx->vs_resources.blocks[rid];
1131
1132 r600_context_pipe_state_set_resource(ctx, state, block);
1133 }
1134
1135 void r600_context_pipe_state_set_fs_resource(struct r600_context *ctx, struct r600_pipe_resource_state *state, unsigned rid)
1136 {
1137 struct r600_block *block = ctx->fs_resources.blocks[rid];
1138
1139 r600_context_pipe_state_set_resource(ctx, state, block);
1140 }
1141
1142 static inline void r600_context_pipe_state_set_sampler(struct r600_context *ctx, struct r600_pipe_state *state, unsigned offset)
1143 {
1144 struct r600_range *range;
1145 struct r600_block *block;
1146 int i;
1147 int dirty;
1148
1149 range = &ctx->range[CTX_RANGE_ID(offset)];
1150 block = range->blocks[CTX_BLOCK_ID(offset)];
1151 if (state == NULL) {
1152 block->status &= ~(R600_BLOCK_STATUS_ENABLED | R600_BLOCK_STATUS_DIRTY);
1153 LIST_DELINIT(&block->list);
1154 LIST_DELINIT(&block->enable_list);
1155 return;
1156 }
1157 dirty = block->status & R600_BLOCK_STATUS_DIRTY;
1158 for (i = 0; i < 3; i++) {
1159 if (block->reg[i] != state->regs[i].value) {
1160 block->reg[i] = state->regs[i].value;
1161 dirty |= R600_BLOCK_STATUS_DIRTY;
1162 }
1163 }
1164
1165 if (dirty)
1166 r600_context_dirty_block(ctx, block, dirty, 2);
1167 }
1168
1169 static inline void r600_context_ps_partial_flush(struct r600_context *ctx)
1170 {
1171 if (!(ctx->flags & R600_CONTEXT_DRAW_PENDING))
1172 return;
1173
1174 ctx->pm4[ctx->pm4_cdwords++] = PKT3(PKT3_EVENT_WRITE, 0, 0);
1175 ctx->pm4[ctx->pm4_cdwords++] = EVENT_TYPE(EVENT_TYPE_PS_PARTIAL_FLUSH) | EVENT_INDEX(4);
1176
1177 ctx->flags &= ~R600_CONTEXT_DRAW_PENDING;
1178 }
1179
1180 static inline void r600_context_pipe_state_set_sampler_border(struct r600_context *ctx, struct r600_pipe_state *state, unsigned offset)
1181 {
1182 struct r600_range *range;
1183 struct r600_block *block;
1184 int i;
1185 int dirty;
1186
1187 range = &ctx->range[CTX_RANGE_ID(offset)];
1188 block = range->blocks[CTX_BLOCK_ID(offset)];
1189 if (state == NULL) {
1190 block->status &= ~(R600_BLOCK_STATUS_ENABLED | R600_BLOCK_STATUS_DIRTY);
1191 LIST_DELINIT(&block->list);
1192 LIST_DELINIT(&block->enable_list);
1193 return;
1194 }
1195 if (state->nregs <= 3) {
1196 return;
1197 }
1198 dirty = block->status & R600_BLOCK_STATUS_DIRTY;
1199 for (i = 0; i < 4; i++) {
1200 if (block->reg[i] != state->regs[i + 3].value) {
1201 block->reg[i] = state->regs[i + 3].value;
1202 dirty |= R600_BLOCK_STATUS_DIRTY;
1203 }
1204 }
1205
1206 /* We have to flush the shaders before we change the border color
1207 * registers, or previous draw commands that haven't completed yet
1208 * will end up using the new border color. */
1209 if (dirty & R600_BLOCK_STATUS_DIRTY)
1210 r600_context_ps_partial_flush(ctx);
1211 if (dirty)
1212 r600_context_dirty_block(ctx, block, dirty, 3);
1213 }
1214
1215 void r600_context_pipe_state_set_ps_sampler(struct r600_context *ctx, struct r600_pipe_state *state, unsigned id)
1216 {
1217 unsigned offset;
1218
1219 offset = 0x0003C000 + id * 0xc;
1220 r600_context_pipe_state_set_sampler(ctx, state, offset);
1221 offset = 0x0000A400 + id * 0x10;
1222 r600_context_pipe_state_set_sampler_border(ctx, state, offset);
1223 }
1224
1225 void r600_context_pipe_state_set_vs_sampler(struct r600_context *ctx, struct r600_pipe_state *state, unsigned id)
1226 {
1227 unsigned offset;
1228
1229 offset = 0x0003C0D8 + id * 0xc;
1230 r600_context_pipe_state_set_sampler(ctx, state, offset);
1231 offset = 0x0000A600 + id * 0x10;
1232 r600_context_pipe_state_set_sampler_border(ctx, state, offset);
1233 }
1234
1235 struct r600_bo *r600_context_reg_bo(struct r600_context *ctx, unsigned offset)
1236 {
1237 struct r600_range *range;
1238 struct r600_block *block;
1239 unsigned id;
1240
1241 range = &ctx->range[CTX_RANGE_ID(offset)];
1242 block = range->blocks[CTX_BLOCK_ID(offset)];
1243 offset -= block->start_offset;
1244 id = block->pm4_bo_index[offset >> 2];
1245 if (block->reloc[id].bo) {
1246 return block->reloc[id].bo;
1247 }
1248 return NULL;
1249 }
1250
1251 void r600_context_block_emit_dirty(struct r600_context *ctx, struct r600_block *block)
1252 {
1253 int id;
1254 int optional = block->nbo == 0 && !(block->flags & REG_FLAG_DIRTY_ALWAYS);
1255 int cp_dwords = block->pm4_ndwords, start_dword = 0;
1256 int new_dwords = 0;
1257
1258 if (block->nreg_dirty == 0 && optional) {
1259 goto out;
1260 }
1261
1262 if (block->nbo) {
1263 ctx->flags |= R600_CONTEXT_CHECK_EVENT_FLUSH;
1264
1265 for (int j = 0; j < block->nreg; j++) {
1266 if (block->pm4_bo_index[j]) {
1267 /* find relocation */
1268 id = block->pm4_bo_index[j];
1269 r600_context_bo_reloc(ctx,
1270 &block->pm4[block->reloc[id].bo_pm4_index],
1271 block->reloc[id].bo);
1272 r600_context_bo_flush(ctx,
1273 block->reloc[id].flush_flags,
1274 block->reloc[id].flush_mask,
1275 block->reloc[id].bo);
1276 }
1277 }
1278 ctx->flags &= ~R600_CONTEXT_CHECK_EVENT_FLUSH;
1279 }
1280
1281 optional &= (block->nreg_dirty != block->nreg);
1282 if (optional) {
1283 new_dwords = block->nreg_dirty;
1284 start_dword = ctx->pm4_cdwords;
1285 cp_dwords = new_dwords + 2;
1286 }
1287 memcpy(&ctx->pm4[ctx->pm4_cdwords], block->pm4, cp_dwords * 4);
1288 ctx->pm4_cdwords += cp_dwords;
1289
1290 if (optional) {
1291 uint32_t newword;
1292
1293 newword = ctx->pm4[start_dword];
1294 newword &= PKT_COUNT_C;
1295 newword |= PKT_COUNT_S(new_dwords);
1296 ctx->pm4[start_dword] = newword;
1297 }
1298 out:
1299 block->status ^= R600_BLOCK_STATUS_DIRTY;
1300 block->nreg_dirty = 0;
1301 LIST_DELINIT(&block->list);
1302 }
1303
1304 void r600_context_flush_dest_caches(struct r600_context *ctx)
1305 {
1306 struct r600_bo *cb[8];
1307 struct r600_bo *db;
1308 int i;
1309
1310 if (!(ctx->flags & R600_CONTEXT_DST_CACHES_DIRTY))
1311 return;
1312
1313 db = r600_context_reg_bo(ctx, R_02800C_DB_DEPTH_BASE);
1314 cb[0] = r600_context_reg_bo(ctx, R_028040_CB_COLOR0_BASE);
1315 cb[1] = r600_context_reg_bo(ctx, R_028044_CB_COLOR1_BASE);
1316 cb[2] = r600_context_reg_bo(ctx, R_028048_CB_COLOR2_BASE);
1317 cb[3] = r600_context_reg_bo(ctx, R_02804C_CB_COLOR3_BASE);
1318 cb[4] = r600_context_reg_bo(ctx, R_028050_CB_COLOR4_BASE);
1319 cb[5] = r600_context_reg_bo(ctx, R_028054_CB_COLOR5_BASE);
1320 cb[6] = r600_context_reg_bo(ctx, R_028058_CB_COLOR6_BASE);
1321 cb[7] = r600_context_reg_bo(ctx, R_02805C_CB_COLOR7_BASE);
1322
1323 ctx->flags |= R600_CONTEXT_CHECK_EVENT_FLUSH;
1324 /* flush the color buffers */
1325 for (i = 0; i < 8; i++) {
1326 if (!cb[i])
1327 continue;
1328
1329 r600_context_bo_flush(ctx,
1330 (S_0085F0_CB0_DEST_BASE_ENA(1) << i) |
1331 S_0085F0_CB_ACTION_ENA(1),
1332 0, cb[i]);
1333 }
1334 if (db) {
1335 r600_context_bo_flush(ctx, S_0085F0_DB_ACTION_ENA(1) | S_0085F0_DB_DEST_BASE_ENA(1), 0, db);
1336 }
1337 ctx->flags &= ~R600_CONTEXT_CHECK_EVENT_FLUSH;
1338 ctx->flags &= ~R600_CONTEXT_DST_CACHES_DIRTY;
1339 }
1340
1341 void r600_context_draw(struct r600_context *ctx, const struct r600_draw *draw)
1342 {
1343 unsigned ndwords = 7;
1344 struct r600_block *dirty_block = NULL;
1345 struct r600_block *next_block;
1346 uint32_t *pm4;
1347
1348 if (draw->indices) {
1349 ndwords = 11;
1350 /* make sure there is enough relocation space before scheduling draw */
1351 if (ctx->creloc >= (ctx->nreloc - 1)) {
1352 r600_context_flush(ctx);
1353 }
1354 }
1355
1356 /* queries need some special values */
1357 if (ctx->num_query_running) {
1358 if (ctx->radeon->family >= CHIP_RV770) {
1359 r600_context_reg(ctx,
1360 R_028D0C_DB_RENDER_CONTROL,
1361 S_028D0C_R700_PERFECT_ZPASS_COUNTS(1),
1362 S_028D0C_R700_PERFECT_ZPASS_COUNTS(1));
1363 }
1364 r600_context_reg(ctx,
1365 R_028D10_DB_RENDER_OVERRIDE,
1366 S_028D10_NOOP_CULL_DISABLE(1),
1367 S_028D10_NOOP_CULL_DISABLE(1));
1368 }
1369
1370 /* update the max dword count to make sure we have enough space
1371 * reserved for flushing the destination caches */
1372 ctx->pm4_ndwords = RADEON_CTX_MAX_PM4 - ctx->num_dest_buffers * 7 - 16;
1373
1374 if ((ctx->pm4_dirty_cdwords + ndwords + ctx->pm4_cdwords) > ctx->pm4_ndwords) {
1375 /* need to flush */
1376 r600_context_flush(ctx);
1377 }
1378 /* at that point everythings is flushed and ctx->pm4_cdwords = 0 */
1379 if ((ctx->pm4_dirty_cdwords + ndwords) > ctx->pm4_ndwords) {
1380 R600_ERR("context is too big to be scheduled\n");
1381 return;
1382 }
1383 /* enough room to copy packet */
1384 LIST_FOR_EACH_ENTRY_SAFE(dirty_block, next_block, &ctx->dirty, list) {
1385 r600_context_block_emit_dirty(ctx, dirty_block);
1386 }
1387
1388 /* draw packet */
1389 pm4 = &ctx->pm4[ctx->pm4_cdwords];
1390
1391 pm4[0] = PKT3(PKT3_INDEX_TYPE, 0, ctx->predicate_drawing);
1392 pm4[1] = draw->vgt_index_type;
1393 pm4[2] = PKT3(PKT3_NUM_INSTANCES, 0, ctx->predicate_drawing);
1394 pm4[3] = draw->vgt_num_instances;
1395 if (draw->indices) {
1396 pm4[4] = PKT3(PKT3_DRAW_INDEX, 3, ctx->predicate_drawing);
1397 pm4[5] = draw->indices_bo_offset + r600_bo_offset(draw->indices);
1398 pm4[6] = 0;
1399 pm4[7] = draw->vgt_num_indices;
1400 pm4[8] = draw->vgt_draw_initiator;
1401 pm4[9] = PKT3(PKT3_NOP, 0, ctx->predicate_drawing);
1402 pm4[10] = 0;
1403 r600_context_bo_reloc(ctx, &pm4[10], draw->indices);
1404 } else {
1405 pm4[4] = PKT3(PKT3_DRAW_INDEX_AUTO, 1, ctx->predicate_drawing);
1406 pm4[5] = draw->vgt_num_indices;
1407 pm4[6] = draw->vgt_draw_initiator;
1408 }
1409 ctx->pm4_cdwords += ndwords;
1410
1411 ctx->flags |= (R600_CONTEXT_DST_CACHES_DIRTY | R600_CONTEXT_DRAW_PENDING);
1412
1413 /* all dirty state have been scheduled in current cs */
1414 ctx->pm4_dirty_cdwords = 0;
1415 }
1416
1417 void r600_context_flush(struct r600_context *ctx)
1418 {
1419 struct drm_radeon_cs drmib = {};
1420 struct drm_radeon_cs_chunk chunks[2];
1421 uint64_t chunk_array[2];
1422 unsigned fence;
1423 int r;
1424 struct r600_block *enable_block = NULL, *next_block;
1425
1426 if (!ctx->pm4_cdwords)
1427 return;
1428
1429 /* suspend queries */
1430 r600_context_queries_suspend(ctx);
1431
1432 if (ctx->radeon->family >= CHIP_CEDAR)
1433 evergreen_context_flush_dest_caches(ctx);
1434 else
1435 r600_context_flush_dest_caches(ctx);
1436
1437 /* partial flush is needed to avoid lockups on some chips with user fences */
1438 ctx->pm4[ctx->pm4_cdwords++] = PKT3(PKT3_EVENT_WRITE, 0, 0);
1439 ctx->pm4[ctx->pm4_cdwords++] = EVENT_TYPE(EVENT_TYPE_PS_PARTIAL_FLUSH) | EVENT_INDEX(4);
1440 /* emit fence */
1441 ctx->pm4[ctx->pm4_cdwords++] = PKT3(PKT3_EVENT_WRITE_EOP, 4, 0);
1442 ctx->pm4[ctx->pm4_cdwords++] = EVENT_TYPE(EVENT_TYPE_CACHE_FLUSH_AND_INV_TS_EVENT) | EVENT_INDEX(5);
1443 ctx->pm4[ctx->pm4_cdwords++] = 0;
1444 ctx->pm4[ctx->pm4_cdwords++] = (1 << 29) | (0 << 24);
1445 ctx->pm4[ctx->pm4_cdwords++] = ctx->radeon->fence;
1446 ctx->pm4[ctx->pm4_cdwords++] = 0;
1447 ctx->pm4[ctx->pm4_cdwords++] = PKT3(PKT3_NOP, 0, 0);
1448 ctx->pm4[ctx->pm4_cdwords++] = 0;
1449 r600_context_bo_reloc(ctx, &ctx->pm4[ctx->pm4_cdwords - 1], ctx->radeon->fence_bo);
1450
1451 #if 1
1452 /* emit cs */
1453 drmib.num_chunks = 2;
1454 drmib.chunks = (uint64_t)(uintptr_t)chunk_array;
1455 chunks[0].chunk_id = RADEON_CHUNK_ID_IB;
1456 chunks[0].length_dw = ctx->pm4_cdwords;
1457 chunks[0].chunk_data = (uint64_t)(uintptr_t)ctx->pm4;
1458 chunks[1].chunk_id = RADEON_CHUNK_ID_RELOCS;
1459 chunks[1].length_dw = ctx->creloc * sizeof(struct r600_reloc) / 4;
1460 chunks[1].chunk_data = (uint64_t)(uintptr_t)ctx->reloc;
1461 chunk_array[0] = (uint64_t)(uintptr_t)&chunks[0];
1462 chunk_array[1] = (uint64_t)(uintptr_t)&chunks[1];
1463 r = drmCommandWriteRead(ctx->radeon->fd, DRM_RADEON_CS, &drmib,
1464 sizeof(struct drm_radeon_cs));
1465 #else
1466 *ctx->radeon->cfence = ctx->radeon->fence;
1467 #endif
1468
1469 r600_context_update_fenced_list(ctx);
1470
1471 fence = ctx->radeon->fence + 1;
1472 if (fence < ctx->radeon->fence) {
1473 /* wrap around */
1474 fence = 1;
1475 r600_context_fence_wraparound(ctx, fence);
1476 }
1477 ctx->radeon->fence = fence;
1478
1479 /* restart */
1480 for (int i = 0; i < ctx->creloc; i++) {
1481 ctx->bo[i]->reloc = NULL;
1482 ctx->bo[i]->last_flush = 0;
1483 radeon_bo_reference(ctx->radeon, &ctx->bo[i], NULL);
1484 }
1485 ctx->creloc = 0;
1486 ctx->pm4_dirty_cdwords = 0;
1487 ctx->pm4_cdwords = 0;
1488 ctx->flags = 0;
1489
1490 r600_init_cs(ctx);
1491
1492 /* resume queries */
1493 r600_context_queries_resume(ctx);
1494
1495 /* set all valid group as dirty so they get reemited on
1496 * next draw command
1497 */
1498 LIST_FOR_EACH_ENTRY(enable_block, &ctx->enable_list, enable_list) {
1499 if(!(enable_block->status & R600_BLOCK_STATUS_DIRTY)) {
1500 LIST_ADDTAIL(&enable_block->list,&ctx->dirty);
1501 }
1502 ctx->pm4_dirty_cdwords += enable_block->pm4_ndwords +
1503 enable_block->pm4_flush_ndwords;
1504 enable_block->status |= R600_BLOCK_STATUS_DIRTY;
1505 enable_block->nreg_dirty = enable_block->nreg;
1506 }
1507 }
1508
1509 void r600_context_emit_fence(struct r600_context *ctx, struct r600_bo *fence_bo, unsigned offset, unsigned value)
1510 {
1511 unsigned ndwords = 10;
1512
1513 if (((ctx->pm4_dirty_cdwords + ndwords + ctx->pm4_cdwords) > ctx->pm4_ndwords) ||
1514 (ctx->creloc >= (ctx->nreloc - 1))) {
1515 /* need to flush */
1516 r600_context_flush(ctx);
1517 }
1518
1519 ctx->pm4[ctx->pm4_cdwords++] = PKT3(PKT3_EVENT_WRITE, 0, 0);
1520 ctx->pm4[ctx->pm4_cdwords++] = EVENT_TYPE(EVENT_TYPE_PS_PARTIAL_FLUSH) | EVENT_INDEX(4);
1521 ctx->pm4[ctx->pm4_cdwords++] = PKT3(PKT3_EVENT_WRITE_EOP, 4, 0);
1522 ctx->pm4[ctx->pm4_cdwords++] = EVENT_TYPE(EVENT_TYPE_CACHE_FLUSH_AND_INV_TS_EVENT) | EVENT_INDEX(5);
1523 ctx->pm4[ctx->pm4_cdwords++] = offset << 2; /* ADDRESS_LO */
1524 ctx->pm4[ctx->pm4_cdwords++] = (1 << 29) | (0 << 24); /* DATA_SEL | INT_EN | ADDRESS_HI */
1525 ctx->pm4[ctx->pm4_cdwords++] = value; /* DATA_LO */
1526 ctx->pm4[ctx->pm4_cdwords++] = 0; /* DATA_HI */
1527 ctx->pm4[ctx->pm4_cdwords++] = PKT3(PKT3_NOP, 0, 0);
1528 ctx->pm4[ctx->pm4_cdwords++] = 0;
1529 r600_context_bo_reloc(ctx, &ctx->pm4[ctx->pm4_cdwords - 1], fence_bo);
1530 }
1531
1532 void r600_context_dump_bof(struct r600_context *ctx, const char *file)
1533 {
1534 bof_t *bcs, *blob, *array, *bo, *size, *handle, *device_id, *root;
1535 unsigned i;
1536
1537 root = device_id = bcs = blob = array = bo = size = handle = NULL;
1538 root = bof_object();
1539 if (root == NULL)
1540 goto out_err;
1541 device_id = bof_int32(ctx->radeon->device);
1542 if (device_id == NULL)
1543 goto out_err;
1544 if (bof_object_set(root, "device_id", device_id))
1545 goto out_err;
1546 bof_decref(device_id);
1547 device_id = NULL;
1548 /* dump relocs */
1549 blob = bof_blob(ctx->creloc * 16, ctx->reloc);
1550 if (blob == NULL)
1551 goto out_err;
1552 if (bof_object_set(root, "reloc", blob))
1553 goto out_err;
1554 bof_decref(blob);
1555 blob = NULL;
1556 /* dump cs */
1557 blob = bof_blob(ctx->pm4_cdwords * 4, ctx->pm4);
1558 if (blob == NULL)
1559 goto out_err;
1560 if (bof_object_set(root, "pm4", blob))
1561 goto out_err;
1562 bof_decref(blob);
1563 blob = NULL;
1564 /* dump bo */
1565 array = bof_array();
1566 if (array == NULL)
1567 goto out_err;
1568 for (i = 0; i < ctx->creloc; i++) {
1569 struct radeon_bo *rbo = ctx->bo[i];
1570 bo = bof_object();
1571 if (bo == NULL)
1572 goto out_err;
1573 size = bof_int32(rbo->size);
1574 if (size == NULL)
1575 goto out_err;
1576 if (bof_object_set(bo, "size", size))
1577 goto out_err;
1578 bof_decref(size);
1579 size = NULL;
1580 handle = bof_int32(rbo->handle);
1581 if (handle == NULL)
1582 goto out_err;
1583 if (bof_object_set(bo, "handle", handle))
1584 goto out_err;
1585 bof_decref(handle);
1586 handle = NULL;
1587 radeon_bo_map(ctx->radeon, rbo);
1588 blob = bof_blob(rbo->size, rbo->data);
1589 radeon_bo_unmap(ctx->radeon, rbo);
1590 if (blob == NULL)
1591 goto out_err;
1592 if (bof_object_set(bo, "data", blob))
1593 goto out_err;
1594 bof_decref(blob);
1595 blob = NULL;
1596 if (bof_array_append(array, bo))
1597 goto out_err;
1598 bof_decref(bo);
1599 bo = NULL;
1600 }
1601 if (bof_object_set(root, "bo", array))
1602 goto out_err;
1603 bof_dump_file(root, file);
1604 out_err:
1605 bof_decref(blob);
1606 bof_decref(array);
1607 bof_decref(bo);
1608 bof_decref(size);
1609 bof_decref(handle);
1610 bof_decref(device_id);
1611 bof_decref(root);
1612 }
1613
1614 static boolean r600_query_result(struct r600_context *ctx, struct r600_query *query, boolean wait)
1615 {
1616 u64 start, end;
1617 u32 *results;
1618 int i;
1619 int size;
1620
1621 if (wait)
1622 results = r600_bo_map(ctx->radeon, query->buffer, PB_USAGE_CPU_READ, NULL);
1623 else
1624 results = r600_bo_map(ctx->radeon, query->buffer, PB_USAGE_DONTBLOCK | PB_USAGE_CPU_READ, NULL);
1625 if (!results)
1626 return FALSE;
1627
1628 /* query->num_results contains how many dwords were used for the query */
1629 size = query->num_results;
1630 for (i = 0; i < size; i += 4) {
1631 start = (u64)results[i] | (u64)results[i + 1] << 32;
1632 end = (u64)results[i + 2] | (u64)results[i + 3] << 32;
1633 if (((start & 0x8000000000000000UL) && (end & 0x8000000000000000UL))
1634 || query->type == PIPE_QUERY_TIME_ELAPSED) {
1635 query->result += end - start;
1636 }
1637 }
1638 r600_bo_unmap(ctx->radeon, query->buffer);
1639 query->num_results = 0;
1640
1641 return TRUE;
1642 }
1643
1644 void r600_query_begin(struct r600_context *ctx, struct r600_query *query)
1645 {
1646 unsigned required_space;
1647 int num_backends = r600_get_num_backends(ctx->radeon);
1648
1649 /* query request needs 6/8 dwords for begin + 6/8 dwords for end */
1650 if (query->type == PIPE_QUERY_TIME_ELAPSED)
1651 required_space = 16;
1652 else
1653 required_space = 12;
1654
1655 if ((required_space + ctx->pm4_cdwords) > ctx->pm4_ndwords) {
1656 /* need to flush */
1657 r600_context_flush(ctx);
1658 }
1659
1660 /* if query buffer is full force a flush */
1661 if (query->num_results*4 >= query->buffer_size - 16) {
1662 r600_context_flush(ctx);
1663 r600_query_result(ctx, query, TRUE);
1664 }
1665
1666 if (query->type == PIPE_QUERY_OCCLUSION_COUNTER &&
1667 num_backends > 0) {
1668 /* as per info on ZPASS the driver must set the unusued DB top bits */
1669 u32 *results;
1670 int i;
1671
1672 results = r600_bo_map(ctx->radeon, query->buffer, PB_USAGE_DONTBLOCK | PB_USAGE_CPU_WRITE, NULL);
1673 if (results) {
1674 memset(results + (query->num_results * 4), 0, ctx->max_db * 4 * 4);
1675
1676 for (i = num_backends; i < ctx->max_db; i++) {
1677 results[(i * 4)+1] = 0x80000000;
1678 results[(i * 4)+3] = 0x80000000;
1679 }
1680 r600_bo_unmap(ctx->radeon, query->buffer);
1681 }
1682 }
1683
1684 /* emit begin query */
1685 if (query->type == PIPE_QUERY_TIME_ELAPSED) {
1686 ctx->pm4[ctx->pm4_cdwords++] = PKT3(PKT3_EVENT_WRITE_EOP, 4, 0);
1687 ctx->pm4[ctx->pm4_cdwords++] = EVENT_TYPE(EVENT_TYPE_CACHE_FLUSH_AND_INV_TS_EVENT) | EVENT_INDEX(5);
1688 ctx->pm4[ctx->pm4_cdwords++] = query->num_results*4 + r600_bo_offset(query->buffer);
1689 ctx->pm4[ctx->pm4_cdwords++] = (3 << 29);
1690 ctx->pm4[ctx->pm4_cdwords++] = 0;
1691 ctx->pm4[ctx->pm4_cdwords++] = 0;
1692 } else {
1693 ctx->pm4[ctx->pm4_cdwords++] = PKT3(PKT3_EVENT_WRITE, 2, 0);
1694 ctx->pm4[ctx->pm4_cdwords++] = EVENT_TYPE(EVENT_TYPE_ZPASS_DONE) | EVENT_INDEX(1);
1695 ctx->pm4[ctx->pm4_cdwords++] = query->num_results*4 + r600_bo_offset(query->buffer);
1696 ctx->pm4[ctx->pm4_cdwords++] = 0;
1697 }
1698 ctx->pm4[ctx->pm4_cdwords++] = PKT3(PKT3_NOP, 0, 0);
1699 ctx->pm4[ctx->pm4_cdwords++] = 0;
1700 r600_context_bo_reloc(ctx, &ctx->pm4[ctx->pm4_cdwords - 1], query->buffer);
1701
1702 query->state |= R600_QUERY_STATE_STARTED;
1703 query->state ^= R600_QUERY_STATE_ENDED;
1704 ctx->num_query_running++;
1705 }
1706
1707 void r600_query_end(struct r600_context *ctx, struct r600_query *query)
1708 {
1709 /* emit begin query */
1710 if (query->type == PIPE_QUERY_TIME_ELAPSED) {
1711 ctx->pm4[ctx->pm4_cdwords++] = PKT3(PKT3_EVENT_WRITE_EOP, 4, 0);
1712 ctx->pm4[ctx->pm4_cdwords++] = EVENT_TYPE(EVENT_TYPE_CACHE_FLUSH_AND_INV_TS_EVENT) | EVENT_INDEX(5);
1713 ctx->pm4[ctx->pm4_cdwords++] = query->num_results*4 + 8 + r600_bo_offset(query->buffer);
1714 ctx->pm4[ctx->pm4_cdwords++] = (3 << 29);
1715 ctx->pm4[ctx->pm4_cdwords++] = 0;
1716 ctx->pm4[ctx->pm4_cdwords++] = 0;
1717 } else {
1718 ctx->pm4[ctx->pm4_cdwords++] = PKT3(PKT3_EVENT_WRITE, 2, 0);
1719 ctx->pm4[ctx->pm4_cdwords++] = EVENT_TYPE(EVENT_TYPE_ZPASS_DONE) | EVENT_INDEX(1);
1720 ctx->pm4[ctx->pm4_cdwords++] = query->num_results*4 + 8 + r600_bo_offset(query->buffer);
1721 ctx->pm4[ctx->pm4_cdwords++] = 0;
1722 }
1723 ctx->pm4[ctx->pm4_cdwords++] = PKT3(PKT3_NOP, 0, 0);
1724 ctx->pm4[ctx->pm4_cdwords++] = 0;
1725 r600_context_bo_reloc(ctx, &ctx->pm4[ctx->pm4_cdwords - 1], query->buffer);
1726
1727 query->num_results += 4 * (query->type == PIPE_QUERY_OCCLUSION_COUNTER ? ctx->max_db : 1);
1728 query->state ^= R600_QUERY_STATE_STARTED;
1729 query->state |= R600_QUERY_STATE_ENDED;
1730 ctx->num_query_running--;
1731 }
1732
1733 void r600_query_predication(struct r600_context *ctx, struct r600_query *query, int operation,
1734 int flag_wait)
1735 {
1736 ctx->pm4[ctx->pm4_cdwords++] = PKT3(PKT3_SET_PREDICATION, 1, 0);
1737
1738 if (operation == PREDICATION_OP_CLEAR) {
1739 ctx->pm4[ctx->pm4_cdwords++] = 0;
1740 ctx->pm4[ctx->pm4_cdwords++] = PRED_OP(PREDICATION_OP_CLEAR);
1741 } else {
1742 int results_base = query->num_results - (4 * ctx->max_db);
1743
1744 if (results_base < 0)
1745 results_base = 0;
1746
1747 ctx->pm4[ctx->pm4_cdwords++] = results_base*4 + r600_bo_offset(query->buffer);
1748 ctx->pm4[ctx->pm4_cdwords++] = PRED_OP(operation) | (flag_wait ? PREDICATION_HINT_WAIT : PREDICATION_HINT_NOWAIT_DRAW) | PREDICATION_DRAW_VISIBLE;
1749 ctx->pm4[ctx->pm4_cdwords++] = PKT3(PKT3_NOP, 0, 0);
1750 ctx->pm4[ctx->pm4_cdwords++] = 0;
1751 r600_context_bo_reloc(ctx, &ctx->pm4[ctx->pm4_cdwords - 1], query->buffer);
1752 }
1753 }
1754
1755 struct r600_query *r600_context_query_create(struct r600_context *ctx, unsigned query_type)
1756 {
1757 struct r600_query *query;
1758
1759 if (query_type != PIPE_QUERY_OCCLUSION_COUNTER && query_type != PIPE_QUERY_TIME_ELAPSED)
1760 return NULL;
1761
1762 query = calloc(1, sizeof(struct r600_query));
1763 if (query == NULL)
1764 return NULL;
1765
1766 query->type = query_type;
1767 query->buffer_size = 4096;
1768
1769 /* As of GL4, query buffers are normally read by the CPU after
1770 * being written by the gpu, hence staging is probably a good
1771 * usage pattern.
1772 */
1773 query->buffer = r600_bo(ctx->radeon, query->buffer_size, 1, 0,
1774 PIPE_USAGE_STAGING);
1775 if (!query->buffer) {
1776 free(query);
1777 return NULL;
1778 }
1779
1780 LIST_ADDTAIL(&query->list, &ctx->query_list);
1781
1782 return query;
1783 }
1784
1785 void r600_context_query_destroy(struct r600_context *ctx, struct r600_query *query)
1786 {
1787 r600_bo_reference(ctx->radeon, &query->buffer, NULL);
1788 LIST_DELINIT(&query->list);
1789 free(query);
1790 }
1791
1792 boolean r600_context_query_result(struct r600_context *ctx,
1793 struct r600_query *query,
1794 boolean wait, void *vresult)
1795 {
1796 uint64_t *result = (uint64_t*)vresult;
1797
1798 if (query->num_results) {
1799 r600_context_flush(ctx);
1800 }
1801 if (!r600_query_result(ctx, query, wait))
1802 return FALSE;
1803 if (query->type == PIPE_QUERY_TIME_ELAPSED)
1804 *result = (1000000*query->result)/r600_get_clock_crystal_freq(ctx->radeon);
1805 else
1806 *result = query->result;
1807 query->result = 0;
1808 return TRUE;
1809 }
1810
1811 void r600_context_queries_suspend(struct r600_context *ctx)
1812 {
1813 struct r600_query *query;
1814
1815 LIST_FOR_EACH_ENTRY(query, &ctx->query_list, list) {
1816 if (query->state & R600_QUERY_STATE_STARTED) {
1817 r600_query_end(ctx, query);
1818 query->state |= R600_QUERY_STATE_SUSPENDED;
1819 }
1820 }
1821 }
1822
1823 void r600_context_queries_resume(struct r600_context *ctx)
1824 {
1825 struct r600_query *query;
1826
1827 LIST_FOR_EACH_ENTRY(query, &ctx->query_list, list) {
1828 if (query->state & R600_QUERY_STATE_SUSPENDED) {
1829 r600_query_begin(ctx, query);
1830 query->state ^= R600_QUERY_STATE_SUSPENDED;
1831 }
1832 }
1833 }