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[mesa.git] / src / gallium / winsys / r600 / drm / r600_hw_context.c
1 /*
2 * Copyright 2010 Jerome Glisse <glisse@freedesktop.org>
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * on the rights to use, copy, modify, merge, publish, distribute, sub
8 * license, and/or sell copies of the Software, and to permit persons to whom
9 * the Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
22 *
23 * Authors:
24 * Jerome Glisse
25 */
26 #include <errno.h>
27 #include <stdint.h>
28 #include <string.h>
29 #include <stdlib.h>
30 #include <assert.h>
31 #include <pipe/p_compiler.h>
32 #include <util/u_inlines.h>
33 #include <util/u_memory.h>
34 #include <pipebuffer/pb_bufmgr.h>
35 #include "xf86drm.h"
36 #include "radeon_drm.h"
37 #include "r600_priv.h"
38 #include "bof.h"
39 #include "r600d.h"
40
41 #define GROUP_FORCE_NEW_BLOCK 0
42
43 static inline void r600_context_ps_partial_flush(struct r600_context *ctx)
44 {
45 if (!(ctx->flags & R600_CONTEXT_DRAW_PENDING))
46 return;
47
48 ctx->pm4[ctx->pm4_cdwords++] = PKT3(PKT3_EVENT_WRITE, 0, 0);
49 ctx->pm4[ctx->pm4_cdwords++] = EVENT_TYPE(EVENT_TYPE_PS_PARTIAL_FLUSH) | EVENT_INDEX(4);
50
51 ctx->flags &= ~R600_CONTEXT_DRAW_PENDING;
52 }
53
54 void r600_init_cs(struct r600_context *ctx)
55 {
56 /* R6xx requires this packet at the start of each command buffer */
57 if (ctx->radeon->family < CHIP_RV770) {
58 ctx->pm4[ctx->pm4_cdwords++] = PKT3(PKT3_START_3D_CMDBUF, 0, 0);
59 ctx->pm4[ctx->pm4_cdwords++] = 0x00000000;
60 }
61 /* All asics require this one */
62 ctx->pm4[ctx->pm4_cdwords++] = PKT3(PKT3_CONTEXT_CONTROL, 1, 0);
63 ctx->pm4[ctx->pm4_cdwords++] = 0x80000000;
64 ctx->pm4[ctx->pm4_cdwords++] = 0x80000000;
65
66 ctx->init_dwords = ctx->pm4_cdwords;
67 }
68
69 static void INLINE r600_context_update_fenced_list(struct r600_context *ctx)
70 {
71 for (int i = 0; i < ctx->creloc; i++) {
72 if (!LIST_IS_EMPTY(&ctx->bo[i]->fencedlist))
73 LIST_DELINIT(&ctx->bo[i]->fencedlist);
74 LIST_ADDTAIL(&ctx->bo[i]->fencedlist, &ctx->fenced_bo);
75 ctx->bo[i]->fence = ctx->radeon->fence;
76 ctx->bo[i]->ctx = ctx;
77 }
78 }
79
80 static void INLINE r600_context_fence_wraparound(struct r600_context *ctx, unsigned fence)
81 {
82 struct radeon_bo *bo = NULL;
83 struct radeon_bo *tmp;
84
85 LIST_FOR_EACH_ENTRY_SAFE(bo, tmp, &ctx->fenced_bo, fencedlist) {
86 if (bo->fence <= *ctx->radeon->cfence) {
87 LIST_DELINIT(&bo->fencedlist);
88 bo->fence = 0;
89 } else {
90 bo->fence = fence;
91 }
92 }
93 }
94
95 static void r600_init_block(struct r600_context *ctx,
96 struct r600_block *block,
97 const struct r600_reg *reg, int index, int nreg,
98 unsigned opcode, unsigned offset_base)
99 {
100 int i = index;
101 int j, n = nreg;
102
103 /* initialize block */
104 if (opcode == PKT3_SET_RESOURCE) {
105 block->flags = BLOCK_FLAG_RESOURCE;
106 block->status |= R600_BLOCK_STATUS_RESOURCE_DIRTY; /* dirty all blocks at start */
107 } else {
108 block->flags = 0;
109 block->status |= R600_BLOCK_STATUS_DIRTY; /* dirty all blocks at start */
110 }
111 block->start_offset = reg[i].offset;
112 block->pm4[block->pm4_ndwords++] = PKT3(opcode, n, 0);
113 block->pm4[block->pm4_ndwords++] = (block->start_offset - offset_base) >> 2;
114 block->reg = &block->pm4[block->pm4_ndwords];
115 block->pm4_ndwords += n;
116 block->nreg = n;
117 block->nreg_dirty = n;
118 LIST_INITHEAD(&block->list);
119 LIST_INITHEAD(&block->enable_list);
120
121 for (j = 0; j < n; j++) {
122 if (reg[i+j].flags & REG_FLAG_DIRTY_ALWAYS) {
123 block->flags |= REG_FLAG_DIRTY_ALWAYS;
124 }
125 if (reg[i+j].flags & REG_FLAG_ENABLE_ALWAYS) {
126 if (!(block->status & R600_BLOCK_STATUS_ENABLED)) {
127 block->status |= R600_BLOCK_STATUS_ENABLED;
128 LIST_ADDTAIL(&block->enable_list, &ctx->enable_list);
129 LIST_ADDTAIL(&block->list,&ctx->dirty);
130 }
131 }
132 if (reg[i+j].flags & REG_FLAG_FLUSH_CHANGE) {
133 block->flags |= REG_FLAG_FLUSH_CHANGE;
134 }
135
136 if (reg[i+j].flags & REG_FLAG_NEED_BO) {
137 block->nbo++;
138 assert(block->nbo < R600_BLOCK_MAX_BO);
139 block->pm4_bo_index[j] = block->nbo;
140 block->pm4[block->pm4_ndwords++] = PKT3(PKT3_NOP, 0, 0);
141 block->pm4[block->pm4_ndwords++] = 0x00000000;
142 if (reg[i+j].flags & REG_FLAG_RV6XX_SBU) {
143 block->reloc[block->nbo].flush_flags = 0;
144 block->reloc[block->nbo].flush_mask = 0;
145 } else {
146 block->reloc[block->nbo].flush_flags = reg[i+j].flush_flags;
147 block->reloc[block->nbo].flush_mask = reg[i+j].flush_mask;
148 }
149 block->reloc[block->nbo].bo_pm4_index = block->pm4_ndwords - 1;
150 }
151 if ((ctx->radeon->family > CHIP_R600) &&
152 (ctx->radeon->family < CHIP_RV770) && reg[i+j].flags & REG_FLAG_RV6XX_SBU) {
153 block->pm4[block->pm4_ndwords++] = PKT3(PKT3_SURFACE_BASE_UPDATE, 0, 0);
154 block->pm4[block->pm4_ndwords++] = reg[i+j].flush_flags;
155 }
156 }
157 for (j = 0; j < n; j++) {
158 if (reg[i+j].flush_flags) {
159 block->pm4_flush_ndwords += 7;
160 }
161 }
162 /* check that we stay in limit */
163 assert(block->pm4_ndwords < R600_BLOCK_MAX_REG);
164 }
165
166 int r600_context_add_block(struct r600_context *ctx, const struct r600_reg *reg, unsigned nreg,
167 unsigned opcode, unsigned offset_base)
168 {
169 struct r600_block *block;
170 struct r600_range *range;
171 int offset;
172
173 for (unsigned i = 0, n = 0; i < nreg; i += n) {
174 /* ignore new block balise */
175 if (reg[i].offset == GROUP_FORCE_NEW_BLOCK) {
176 n = 1;
177 continue;
178 }
179
180 /* ignore regs not on R600 on R600 */
181 if ((reg[i].flags & REG_FLAG_NOT_R600) && ctx->radeon->family == CHIP_R600) {
182 n = 1;
183 continue;
184 }
185
186 /* register that need relocation are in their own group */
187 /* find number of consecutive registers */
188 n = 0;
189 offset = reg[i].offset;
190 while (reg[i + n].offset == offset) {
191 n++;
192 offset += 4;
193 if ((n + i) >= nreg)
194 break;
195 if (n >= (R600_BLOCK_MAX_REG - 2))
196 break;
197 }
198
199 /* allocate new block */
200 block = calloc(1, sizeof(struct r600_block));
201 if (block == NULL) {
202 return -ENOMEM;
203 }
204 ctx->nblocks++;
205 for (int j = 0; j < n; j++) {
206 range = &ctx->range[CTX_RANGE_ID(reg[i + j].offset)];
207 /* create block table if it doesn't exist */
208 if (!range->blocks)
209 range->blocks = calloc(1 << HASH_SHIFT, sizeof(void *));
210 if (!range->blocks)
211 return -1;
212
213 range->blocks[CTX_BLOCK_ID(reg[i + j].offset)] = block;
214 }
215
216 r600_init_block(ctx, block, reg, i, n, opcode, offset_base);
217
218 }
219 return 0;
220 }
221
222 /* R600/R700 configuration */
223 static const struct r600_reg r600_config_reg_list[] = {
224 {R_008958_VGT_PRIMITIVE_TYPE, 0, 0, 0},
225 {R_008C00_SQ_CONFIG, REG_FLAG_ENABLE_ALWAYS | REG_FLAG_FLUSH_CHANGE, 0, 0},
226 {R_008C04_SQ_GPR_RESOURCE_MGMT_1, REG_FLAG_ENABLE_ALWAYS | REG_FLAG_FLUSH_CHANGE, 0, 0},
227 {R_008C08_SQ_GPR_RESOURCE_MGMT_2, REG_FLAG_ENABLE_ALWAYS | REG_FLAG_FLUSH_CHANGE, 0, 0},
228 {R_008C0C_SQ_THREAD_RESOURCE_MGMT, REG_FLAG_ENABLE_ALWAYS | REG_FLAG_FLUSH_CHANGE, 0, 0},
229 {R_008C10_SQ_STACK_RESOURCE_MGMT_1, REG_FLAG_ENABLE_ALWAYS | REG_FLAG_FLUSH_CHANGE, 0, 0},
230 {R_008C14_SQ_STACK_RESOURCE_MGMT_2, REG_FLAG_ENABLE_ALWAYS | REG_FLAG_FLUSH_CHANGE, 0, 0},
231 {R_008D8C_SQ_DYN_GPR_CNTL_PS_FLUSH_REQ, REG_FLAG_ENABLE_ALWAYS | REG_FLAG_FLUSH_CHANGE, 0, 0},
232 {R_009508_TA_CNTL_AUX, REG_FLAG_ENABLE_ALWAYS | REG_FLAG_FLUSH_CHANGE, 0, 0},
233 {R_009714_VC_ENHANCE, REG_FLAG_ENABLE_ALWAYS | REG_FLAG_FLUSH_CHANGE, 0, 0},
234 {R_009830_DB_DEBUG, REG_FLAG_ENABLE_ALWAYS | REG_FLAG_FLUSH_CHANGE, 0, 0},
235 {R_009838_DB_WATERMARKS, REG_FLAG_ENABLE_ALWAYS | REG_FLAG_FLUSH_CHANGE, 0, 0},
236 };
237
238 static const struct r600_reg r600_ctl_const_list[] = {
239 {R_03CFF0_SQ_VTX_BASE_VTX_LOC, 0, 0, 0},
240 {R_03CFF4_SQ_VTX_START_INST_LOC, 0, 0, 0},
241 };
242
243 static const struct r600_reg r600_context_reg_list[] = {
244 {R_028350_SX_MISC, 0, 0, 0},
245 {R_0286C8_SPI_THREAD_GROUPING, 0, 0, 0},
246 {R_0288A8_SQ_ESGS_RING_ITEMSIZE, 0, 0, 0},
247 {R_0288AC_SQ_GSVS_RING_ITEMSIZE, 0, 0, 0},
248 {R_0288B0_SQ_ESTMP_RING_ITEMSIZE, 0, 0, 0},
249 {R_0288B4_SQ_GSTMP_RING_ITEMSIZE, 0, 0, 0},
250 {R_0288B8_SQ_VSTMP_RING_ITEMSIZE, 0, 0, 0},
251 {R_0288BC_SQ_PSTMP_RING_ITEMSIZE, 0, 0, 0},
252 {R_0288C0_SQ_FBUF_RING_ITEMSIZE, 0, 0, 0},
253 {R_0288C4_SQ_REDUC_RING_ITEMSIZE, 0, 0, 0},
254 {R_0288C8_SQ_GS_VERT_ITEMSIZE, 0, 0, 0},
255 {R_028A10_VGT_OUTPUT_PATH_CNTL, 0, 0, 0},
256 {R_028A14_VGT_HOS_CNTL, 0, 0, 0},
257 {R_028A18_VGT_HOS_MAX_TESS_LEVEL, 0, 0, 0},
258 {R_028A1C_VGT_HOS_MIN_TESS_LEVEL, 0, 0, 0},
259 {R_028A20_VGT_HOS_REUSE_DEPTH, 0, 0, 0},
260 {R_028A24_VGT_GROUP_PRIM_TYPE, 0, 0, 0},
261 {R_028A28_VGT_GROUP_FIRST_DECR, 0, 0, 0},
262 {R_028A2C_VGT_GROUP_DECR, 0, 0, 0},
263 {R_028A30_VGT_GROUP_VECT_0_CNTL, 0, 0, 0},
264 {R_028A34_VGT_GROUP_VECT_1_CNTL, 0, 0, 0},
265 {R_028A38_VGT_GROUP_VECT_0_FMT_CNTL, 0, 0, 0},
266 {R_028A3C_VGT_GROUP_VECT_1_FMT_CNTL, 0, 0, 0},
267 {R_028A40_VGT_GS_MODE, 0, 0, 0},
268 {R_028A4C_PA_SC_MODE_CNTL, 0, 0, 0},
269 {R_028AB0_VGT_STRMOUT_EN, 0, 0, 0},
270 {R_028AB4_VGT_REUSE_OFF, 0, 0, 0},
271 {R_028AB8_VGT_VTX_CNT_EN, 0, 0, 0},
272 {R_028B20_VGT_STRMOUT_BUFFER_EN, 0, 0, 0},
273 {R_028028_DB_STENCIL_CLEAR, 0, 0, 0},
274 {R_02802C_DB_DEPTH_CLEAR, 0, 0, 0},
275 {GROUP_FORCE_NEW_BLOCK, 0, 0, 0},
276 {R_028040_CB_COLOR0_BASE, REG_FLAG_NEED_BO|REG_FLAG_RV6XX_SBU, SURFACE_BASE_UPDATE_COLOR(0), 0},
277 {GROUP_FORCE_NEW_BLOCK, 0, 0, 0},
278 {R_0280A0_CB_COLOR0_INFO, REG_FLAG_NEED_BO, 0, 0xFFFFFFFF},
279 {R_028060_CB_COLOR0_SIZE, 0, 0, 0},
280 {R_028080_CB_COLOR0_VIEW, 0, 0, 0},
281 {GROUP_FORCE_NEW_BLOCK, 0, 0, 0},
282 {R_0280E0_CB_COLOR0_FRAG, REG_FLAG_NEED_BO, 0, 0},
283 {GROUP_FORCE_NEW_BLOCK, 0, 0, 0},
284 {R_0280C0_CB_COLOR0_TILE, REG_FLAG_NEED_BO, 0, 0},
285 {R_028100_CB_COLOR0_MASK, 0, 0, 0},
286 {GROUP_FORCE_NEW_BLOCK, 0, 0, 0},
287 {R_028044_CB_COLOR1_BASE, REG_FLAG_NEED_BO|REG_FLAG_RV6XX_SBU, SURFACE_BASE_UPDATE_COLOR(1), 0},
288 {GROUP_FORCE_NEW_BLOCK, 0, 0, 0},
289 {R_0280A4_CB_COLOR1_INFO, REG_FLAG_NEED_BO, 0, 0xFFFFFFFF},
290 {R_028064_CB_COLOR1_SIZE, 0, 0, 0},
291 {R_028084_CB_COLOR1_VIEW, 0, 0, 0},
292 {GROUP_FORCE_NEW_BLOCK, 0, 0, 0},
293 {R_0280E4_CB_COLOR1_FRAG, REG_FLAG_NEED_BO, 0, 0},
294 {GROUP_FORCE_NEW_BLOCK, 0, 0, 0},
295 {R_0280C4_CB_COLOR1_TILE, REG_FLAG_NEED_BO, 0, 0},
296 {R_028104_CB_COLOR1_MASK, 0, 0, 0},
297 {GROUP_FORCE_NEW_BLOCK, 0, 0, 0},
298 {R_028048_CB_COLOR2_BASE, REG_FLAG_NEED_BO|REG_FLAG_RV6XX_SBU, SURFACE_BASE_UPDATE_COLOR(2), 0},
299 {GROUP_FORCE_NEW_BLOCK, 0, 0, 0},
300 {R_0280A8_CB_COLOR2_INFO, REG_FLAG_NEED_BO, 0, 0xFFFFFFFF},
301 {R_028068_CB_COLOR2_SIZE, 0, 0, 0},
302 {R_028088_CB_COLOR2_VIEW, 0, 0, 0},
303 {GROUP_FORCE_NEW_BLOCK, 0, 0, 0},
304 {R_0280E8_CB_COLOR2_FRAG, REG_FLAG_NEED_BO, 0, 0},
305 {GROUP_FORCE_NEW_BLOCK, 0, 0, 0},
306 {R_0280C8_CB_COLOR2_TILE, REG_FLAG_NEED_BO, 0, 0},
307 {R_028108_CB_COLOR2_MASK, 0, 0, 0},
308 {GROUP_FORCE_NEW_BLOCK, 0, 0, 0},
309 {R_02804C_CB_COLOR3_BASE, REG_FLAG_NEED_BO|REG_FLAG_RV6XX_SBU, SURFACE_BASE_UPDATE_COLOR(3), 0},
310 {GROUP_FORCE_NEW_BLOCK, 0, 0, 0},
311 {R_0280AC_CB_COLOR3_INFO, REG_FLAG_NEED_BO, 0, 0xFFFFFFFF},
312 {R_02806C_CB_COLOR3_SIZE, 0, 0, 0},
313 {R_02808C_CB_COLOR3_VIEW, 0, 0, 0},
314 {GROUP_FORCE_NEW_BLOCK, 0, 0, 0},
315 {R_0280EC_CB_COLOR3_FRAG, REG_FLAG_NEED_BO, 0, 0},
316 {GROUP_FORCE_NEW_BLOCK, 0, 0, 0},
317 {R_0280CC_CB_COLOR3_TILE, REG_FLAG_NEED_BO, 0, 0},
318 {R_02810C_CB_COLOR3_MASK, 0, 0, 0},
319 {GROUP_FORCE_NEW_BLOCK, 0, 0, 0},
320 {R_028050_CB_COLOR4_BASE, REG_FLAG_NEED_BO|REG_FLAG_RV6XX_SBU, SURFACE_BASE_UPDATE_COLOR(4), 0},
321 {GROUP_FORCE_NEW_BLOCK, 0, 0, 0},
322 {R_0280B0_CB_COLOR4_INFO, REG_FLAG_NEED_BO, 0, 0xFFFFFFFF},
323 {R_028070_CB_COLOR4_SIZE, 0, 0, 0},
324 {R_028090_CB_COLOR4_VIEW, 0, 0, 0},
325 {GROUP_FORCE_NEW_BLOCK, 0, 0, 0},
326 {R_0280F0_CB_COLOR4_FRAG, REG_FLAG_NEED_BO, 0, 0},
327 {GROUP_FORCE_NEW_BLOCK, 0, 0, 0},
328 {R_0280D0_CB_COLOR4_TILE, REG_FLAG_NEED_BO, 0, 0},
329 {R_028110_CB_COLOR4_MASK, 0, 0, 0},
330 {GROUP_FORCE_NEW_BLOCK, 0, 0, 0},
331 {R_028054_CB_COLOR5_BASE, REG_FLAG_NEED_BO|REG_FLAG_RV6XX_SBU, SURFACE_BASE_UPDATE_COLOR(5), 0},
332 {GROUP_FORCE_NEW_BLOCK, 0, 0, 0},
333 {R_0280B4_CB_COLOR5_INFO, REG_FLAG_NEED_BO, 0, 0xFFFFFFFF},
334 {R_028074_CB_COLOR5_SIZE, 0, 0, 0},
335 {R_028094_CB_COLOR5_VIEW, 0, 0, 0},
336 {GROUP_FORCE_NEW_BLOCK, 0, 0, 0},
337 {R_0280F4_CB_COLOR5_FRAG, REG_FLAG_NEED_BO, 0, 0},
338 {GROUP_FORCE_NEW_BLOCK, 0, 0, 0},
339 {R_0280D4_CB_COLOR5_TILE, REG_FLAG_NEED_BO, 0, 0},
340 {R_028114_CB_COLOR5_MASK, 0, 0, 0},
341 {R_028058_CB_COLOR6_BASE, REG_FLAG_NEED_BO|REG_FLAG_RV6XX_SBU, SURFACE_BASE_UPDATE_COLOR(6), 0},
342 {R_0280B8_CB_COLOR6_INFO, REG_FLAG_NEED_BO, 0, 0xFFFFFFFF},
343 {R_028078_CB_COLOR6_SIZE, 0, 0, 0},
344 {R_028098_CB_COLOR6_VIEW, 0, 0, 0},
345 {GROUP_FORCE_NEW_BLOCK, 0, 0, 0},
346 {R_0280F8_CB_COLOR6_FRAG, REG_FLAG_NEED_BO, 0, 0},
347 {GROUP_FORCE_NEW_BLOCK, 0, 0, 0},
348 {R_0280D8_CB_COLOR6_TILE, REG_FLAG_NEED_BO, 0, 0},
349 {R_028118_CB_COLOR6_MASK, 0, 0, 0},
350 {GROUP_FORCE_NEW_BLOCK, 0, 0, 0},
351 {R_02805C_CB_COLOR7_BASE, REG_FLAG_NEED_BO|REG_FLAG_RV6XX_SBU, SURFACE_BASE_UPDATE_COLOR(7), 0},
352 {GROUP_FORCE_NEW_BLOCK, 0, 0, 0},
353 {R_0280BC_CB_COLOR7_INFO, REG_FLAG_NEED_BO, 0, 0xFFFFFFFF},
354 {R_02807C_CB_COLOR7_SIZE, 0, 0, 0},
355 {R_02809C_CB_COLOR7_VIEW, 0, 0, 0},
356 {R_0280FC_CB_COLOR7_FRAG, REG_FLAG_NEED_BO, 0, 0},
357 {R_0280DC_CB_COLOR7_TILE, REG_FLAG_NEED_BO, 0, 0},
358 {R_02811C_CB_COLOR7_MASK, 0, 0, 0},
359 {R_028120_CB_CLEAR_RED, 0, 0, 0},
360 {R_028124_CB_CLEAR_GREEN, 0, 0, 0},
361 {R_028128_CB_CLEAR_BLUE, 0, 0, 0},
362 {R_02812C_CB_CLEAR_ALPHA, 0, 0, 0},
363 {R_028140_ALU_CONST_BUFFER_SIZE_PS_0, REG_FLAG_DIRTY_ALWAYS, 0, 0},
364 {R_028180_ALU_CONST_BUFFER_SIZE_VS_0, REG_FLAG_DIRTY_ALWAYS, 0, 0},
365 {R_028940_ALU_CONST_CACHE_PS_0, REG_FLAG_NEED_BO, S_0085F0_SH_ACTION_ENA(1), 0xFFFFFFFF},
366 {R_028980_ALU_CONST_CACHE_VS_0, REG_FLAG_NEED_BO, S_0085F0_SH_ACTION_ENA(1), 0xFFFFFFFF},
367 {R_02823C_CB_SHADER_MASK, 0, 0, 0},
368 {R_028238_CB_TARGET_MASK, 0, 0, 0},
369 {R_028410_SX_ALPHA_TEST_CONTROL, 0, 0, 0},
370 {R_028414_CB_BLEND_RED, 0, 0, 0},
371 {R_028418_CB_BLEND_GREEN, 0, 0, 0},
372 {R_02841C_CB_BLEND_BLUE, 0, 0, 0},
373 {R_028420_CB_BLEND_ALPHA, 0, 0, 0},
374 {R_028424_CB_FOG_RED, 0, 0, 0},
375 {R_028428_CB_FOG_GREEN, 0, 0, 0},
376 {R_02842C_CB_FOG_BLUE, 0, 0, 0},
377 {R_028430_DB_STENCILREFMASK, 0, 0, 0},
378 {R_028434_DB_STENCILREFMASK_BF, 0, 0, 0},
379 {R_028438_SX_ALPHA_REF, 0, 0, 0},
380 {R_0286DC_SPI_FOG_CNTL, 0, 0, 0},
381 {R_0286E0_SPI_FOG_FUNC_SCALE, 0, 0, 0},
382 {R_0286E4_SPI_FOG_FUNC_BIAS, 0, 0, 0},
383 {R_028780_CB_BLEND0_CONTROL, REG_FLAG_NOT_R600, 0, 0},
384 {R_028784_CB_BLEND1_CONTROL, REG_FLAG_NOT_R600, 0, 0},
385 {R_028788_CB_BLEND2_CONTROL, REG_FLAG_NOT_R600, 0, 0},
386 {R_02878C_CB_BLEND3_CONTROL, REG_FLAG_NOT_R600, 0, 0},
387 {R_028790_CB_BLEND4_CONTROL, REG_FLAG_NOT_R600, 0, 0},
388 {R_028794_CB_BLEND5_CONTROL, REG_FLAG_NOT_R600, 0, 0},
389 {R_028798_CB_BLEND6_CONTROL, REG_FLAG_NOT_R600, 0, 0},
390 {R_02879C_CB_BLEND7_CONTROL, REG_FLAG_NOT_R600, 0, 0},
391 {R_0287A0_CB_SHADER_CONTROL, 0, 0, 0},
392 {R_028800_DB_DEPTH_CONTROL, 0, 0, 0},
393 {R_028804_CB_BLEND_CONTROL, 0, 0, 0},
394 {R_028808_CB_COLOR_CONTROL, 0, 0, 0},
395 {R_02880C_DB_SHADER_CONTROL, 0, 0, 0},
396 {R_028C04_PA_SC_AA_CONFIG, 0, 0, 0},
397 {R_028C1C_PA_SC_AA_SAMPLE_LOCS_MCTX, 0, 0, 0},
398 {R_028C20_PA_SC_AA_SAMPLE_LOCS_8S_WD1_MCTX, 0, 0, 0},
399 {R_028C30_CB_CLRCMP_CONTROL, 0, 0, 0},
400 {R_028C34_CB_CLRCMP_SRC, 0, 0, 0},
401 {R_028C38_CB_CLRCMP_DST, 0, 0, 0},
402 {R_028C3C_CB_CLRCMP_MSK, 0, 0, 0},
403 {R_028C48_PA_SC_AA_MASK, 0, 0, 0},
404 {R_028D2C_DB_SRESULTS_COMPARE_STATE1, 0, 0, 0},
405 {R_028D44_DB_ALPHA_TO_MASK, 0, 0, 0},
406 {R_02800C_DB_DEPTH_BASE, REG_FLAG_NEED_BO|REG_FLAG_RV6XX_SBU, SURFACE_BASE_UPDATE_DEPTH, 0},
407 {R_028000_DB_DEPTH_SIZE, 0, 0, 0},
408 {R_028004_DB_DEPTH_VIEW, 0, 0, 0},
409 {GROUP_FORCE_NEW_BLOCK, 0, 0, 0},
410 {R_028010_DB_DEPTH_INFO, REG_FLAG_NEED_BO, 0, 0},
411 {R_028D0C_DB_RENDER_CONTROL, 0, 0, 0},
412 {R_028D10_DB_RENDER_OVERRIDE, 0, 0, 0},
413 {R_028D24_DB_HTILE_SURFACE, 0, 0, 0},
414 {R_028D30_DB_PRELOAD_CONTROL, 0, 0, 0},
415 {R_028D34_DB_PREFETCH_LIMIT, 0, 0, 0},
416 {R_028030_PA_SC_SCREEN_SCISSOR_TL, 0, 0, 0},
417 {R_028034_PA_SC_SCREEN_SCISSOR_BR, 0, 0, 0},
418 {R_028200_PA_SC_WINDOW_OFFSET, 0, 0, 0},
419 {R_028204_PA_SC_WINDOW_SCISSOR_TL, 0, 0, 0},
420 {R_028208_PA_SC_WINDOW_SCISSOR_BR, 0, 0, 0},
421 {R_02820C_PA_SC_CLIPRECT_RULE, 0, 0, 0},
422 {R_028210_PA_SC_CLIPRECT_0_TL, 0, 0, 0},
423 {R_028214_PA_SC_CLIPRECT_0_BR, 0, 0, 0},
424 {R_028218_PA_SC_CLIPRECT_1_TL, 0, 0, 0},
425 {R_02821C_PA_SC_CLIPRECT_1_BR, 0, 0, 0},
426 {R_028220_PA_SC_CLIPRECT_2_TL, 0, 0, 0},
427 {R_028224_PA_SC_CLIPRECT_2_BR, 0, 0, 0},
428 {R_028228_PA_SC_CLIPRECT_3_TL, 0, 0, 0},
429 {R_02822C_PA_SC_CLIPRECT_3_BR, 0, 0, 0},
430 {R_028230_PA_SC_EDGERULE, 0, 0, 0},
431 {R_028240_PA_SC_GENERIC_SCISSOR_TL, 0, 0, 0},
432 {R_028244_PA_SC_GENERIC_SCISSOR_BR, 0, 0, 0},
433 {R_028250_PA_SC_VPORT_SCISSOR_0_TL, 0, 0, 0},
434 {R_028254_PA_SC_VPORT_SCISSOR_0_BR, 0, 0, 0},
435 {R_0282D0_PA_SC_VPORT_ZMIN_0, 0, 0, 0},
436 {R_0282D4_PA_SC_VPORT_ZMAX_0, 0, 0, 0},
437 {R_02843C_PA_CL_VPORT_XSCALE_0, 0, 0, 0},
438 {R_028440_PA_CL_VPORT_XOFFSET_0, 0, 0, 0},
439 {R_028444_PA_CL_VPORT_YSCALE_0, 0, 0, 0},
440 {R_028448_PA_CL_VPORT_YOFFSET_0, 0, 0, 0},
441 {R_02844C_PA_CL_VPORT_ZSCALE_0, 0, 0, 0},
442 {R_028450_PA_CL_VPORT_ZOFFSET_0, 0, 0, 0},
443 {R_0286D4_SPI_INTERP_CONTROL_0, 0, 0, 0},
444 {R_028810_PA_CL_CLIP_CNTL, 0, 0, 0},
445 {R_028814_PA_SU_SC_MODE_CNTL, 0, 0, 0},
446 {R_028818_PA_CL_VTE_CNTL, 0, 0, 0},
447 {R_02881C_PA_CL_VS_OUT_CNTL, 0, 0, 0},
448 {R_028820_PA_CL_NANINF_CNTL, 0, 0, 0},
449 {R_028A00_PA_SU_POINT_SIZE, 0, 0, 0},
450 {R_028A04_PA_SU_POINT_MINMAX, 0, 0, 0},
451 {R_028A08_PA_SU_LINE_CNTL, 0, 0, 0},
452 {R_028A0C_PA_SC_LINE_STIPPLE, 0, 0, 0},
453 {R_028A48_PA_SC_MPASS_PS_CNTL, 0, 0, 0},
454 {R_028C00_PA_SC_LINE_CNTL, 0, 0, 0},
455 {R_028C08_PA_SU_VTX_CNTL, 0, 0, 0},
456 {R_028C0C_PA_CL_GB_VERT_CLIP_ADJ, 0, 0, 0},
457 {R_028C10_PA_CL_GB_VERT_DISC_ADJ, 0, 0, 0},
458 {R_028C14_PA_CL_GB_HORZ_CLIP_ADJ, 0, 0, 0},
459 {R_028C18_PA_CL_GB_HORZ_DISC_ADJ, 0, 0, 0},
460 {R_028DF8_PA_SU_POLY_OFFSET_DB_FMT_CNTL, 0, 0, 0},
461 {R_028DFC_PA_SU_POLY_OFFSET_CLAMP, 0, 0, 0},
462 {R_028E00_PA_SU_POLY_OFFSET_FRONT_SCALE, 0, 0, 0},
463 {R_028E04_PA_SU_POLY_OFFSET_FRONT_OFFSET, 0, 0, 0},
464 {R_028E08_PA_SU_POLY_OFFSET_BACK_SCALE, 0, 0, 0},
465 {R_028E0C_PA_SU_POLY_OFFSET_BACK_OFFSET, 0, 0, 0},
466 {R_028E20_PA_CL_UCP0_X, 0, 0, 0},
467 {R_028E24_PA_CL_UCP0_Y, 0, 0, 0},
468 {R_028E28_PA_CL_UCP0_Z, 0, 0, 0},
469 {R_028E2C_PA_CL_UCP0_W, 0, 0, 0},
470 {R_028E30_PA_CL_UCP1_X, 0, 0, 0},
471 {R_028E34_PA_CL_UCP1_Y, 0, 0, 0},
472 {R_028E38_PA_CL_UCP1_Z, 0, 0, 0},
473 {R_028E3C_PA_CL_UCP1_W, 0, 0, 0},
474 {R_028E40_PA_CL_UCP2_X, 0, 0, 0},
475 {R_028E44_PA_CL_UCP2_Y, 0, 0, 0},
476 {R_028E48_PA_CL_UCP2_Z, 0, 0, 0},
477 {R_028E4C_PA_CL_UCP2_W, 0, 0, 0},
478 {R_028E50_PA_CL_UCP3_X, 0, 0, 0},
479 {R_028E54_PA_CL_UCP3_Y, 0, 0, 0},
480 {R_028E58_PA_CL_UCP3_Z, 0, 0, 0},
481 {R_028E5C_PA_CL_UCP3_W, 0, 0, 0},
482 {R_028E60_PA_CL_UCP4_X, 0, 0, 0},
483 {R_028E64_PA_CL_UCP4_Y, 0, 0, 0},
484 {R_028E68_PA_CL_UCP4_Z, 0, 0, 0},
485 {R_028E6C_PA_CL_UCP4_W, 0, 0, 0},
486 {R_028E70_PA_CL_UCP5_X, 0, 0, 0},
487 {R_028E74_PA_CL_UCP5_Y, 0, 0, 0},
488 {R_028E78_PA_CL_UCP5_Z, 0, 0, 0},
489 {R_028E7C_PA_CL_UCP5_W, 0, 0, 0},
490 {R_028380_SQ_VTX_SEMANTIC_0, 0, 0, 0},
491 {R_028384_SQ_VTX_SEMANTIC_1, 0, 0, 0},
492 {R_028388_SQ_VTX_SEMANTIC_2, 0, 0, 0},
493 {R_02838C_SQ_VTX_SEMANTIC_3, 0, 0, 0},
494 {R_028390_SQ_VTX_SEMANTIC_4, 0, 0, 0},
495 {R_028394_SQ_VTX_SEMANTIC_5, 0, 0, 0},
496 {R_028398_SQ_VTX_SEMANTIC_6, 0, 0, 0},
497 {R_02839C_SQ_VTX_SEMANTIC_7, 0, 0, 0},
498 {R_0283A0_SQ_VTX_SEMANTIC_8, 0, 0, 0},
499 {R_0283A4_SQ_VTX_SEMANTIC_9, 0, 0, 0},
500 {R_0283A8_SQ_VTX_SEMANTIC_10, 0, 0, 0},
501 {R_0283AC_SQ_VTX_SEMANTIC_11, 0, 0, 0},
502 {R_0283B0_SQ_VTX_SEMANTIC_12, 0, 0, 0},
503 {R_0283B4_SQ_VTX_SEMANTIC_13, 0, 0, 0},
504 {R_0283B8_SQ_VTX_SEMANTIC_14, 0, 0, 0},
505 {R_0283BC_SQ_VTX_SEMANTIC_15, 0, 0, 0},
506 {R_0283C0_SQ_VTX_SEMANTIC_16, 0, 0, 0},
507 {R_0283C4_SQ_VTX_SEMANTIC_17, 0, 0, 0},
508 {R_0283C8_SQ_VTX_SEMANTIC_18, 0, 0, 0},
509 {R_0283CC_SQ_VTX_SEMANTIC_19, 0, 0, 0},
510 {R_0283D0_SQ_VTX_SEMANTIC_20, 0, 0, 0},
511 {R_0283D4_SQ_VTX_SEMANTIC_21, 0, 0, 0},
512 {R_0283D8_SQ_VTX_SEMANTIC_22, 0, 0, 0},
513 {R_0283DC_SQ_VTX_SEMANTIC_23, 0, 0, 0},
514 {R_0283E0_SQ_VTX_SEMANTIC_24, 0, 0, 0},
515 {R_0283E4_SQ_VTX_SEMANTIC_25, 0, 0, 0},
516 {R_0283E8_SQ_VTX_SEMANTIC_26, 0, 0, 0},
517 {R_0283EC_SQ_VTX_SEMANTIC_27, 0, 0, 0},
518 {R_0283F0_SQ_VTX_SEMANTIC_28, 0, 0, 0},
519 {R_0283F4_SQ_VTX_SEMANTIC_29, 0, 0, 0},
520 {R_0283F8_SQ_VTX_SEMANTIC_30, 0, 0, 0},
521 {R_0283FC_SQ_VTX_SEMANTIC_31, 0, 0, 0},
522 {R_028614_SPI_VS_OUT_ID_0, 0, 0, 0},
523 {R_028618_SPI_VS_OUT_ID_1, 0, 0, 0},
524 {R_02861C_SPI_VS_OUT_ID_2, 0, 0, 0},
525 {R_028620_SPI_VS_OUT_ID_3, 0, 0, 0},
526 {R_028624_SPI_VS_OUT_ID_4, 0, 0, 0},
527 {R_028628_SPI_VS_OUT_ID_5, 0, 0, 0},
528 {R_02862C_SPI_VS_OUT_ID_6, 0, 0, 0},
529 {R_028630_SPI_VS_OUT_ID_7, 0, 0, 0},
530 {R_028634_SPI_VS_OUT_ID_8, 0, 0, 0},
531 {R_028638_SPI_VS_OUT_ID_9, 0, 0, 0},
532 {R_0286C4_SPI_VS_OUT_CONFIG, 0, 0, 0},
533 {GROUP_FORCE_NEW_BLOCK, 0, 0, 0},
534 {R_028858_SQ_PGM_START_VS, REG_FLAG_NEED_BO, S_0085F0_SH_ACTION_ENA(1), 0xFFFFFFFF},
535 {GROUP_FORCE_NEW_BLOCK, 0, 0, 0},
536 {R_028868_SQ_PGM_RESOURCES_VS, 0, 0, 0},
537 {GROUP_FORCE_NEW_BLOCK, 0, 0, 0},
538 {R_028894_SQ_PGM_START_FS, REG_FLAG_NEED_BO, S_0085F0_SH_ACTION_ENA(1), 0xFFFFFFFF},
539 {GROUP_FORCE_NEW_BLOCK, 0, 0, 0},
540 {R_0288A4_SQ_PGM_RESOURCES_FS, 0, 0, 0},
541 {R_0288D0_SQ_PGM_CF_OFFSET_VS, 0, 0, 0},
542 {R_0288DC_SQ_PGM_CF_OFFSET_FS, 0, 0, 0},
543 {R_028644_SPI_PS_INPUT_CNTL_0, 0, 0, 0},
544 {R_028648_SPI_PS_INPUT_CNTL_1, 0, 0, 0},
545 {R_02864C_SPI_PS_INPUT_CNTL_2, 0, 0, 0},
546 {R_028650_SPI_PS_INPUT_CNTL_3, 0, 0, 0},
547 {R_028654_SPI_PS_INPUT_CNTL_4, 0, 0, 0},
548 {R_028658_SPI_PS_INPUT_CNTL_5, 0, 0, 0},
549 {R_02865C_SPI_PS_INPUT_CNTL_6, 0, 0, 0},
550 {R_028660_SPI_PS_INPUT_CNTL_7, 0, 0, 0},
551 {R_028664_SPI_PS_INPUT_CNTL_8, 0, 0, 0},
552 {R_028668_SPI_PS_INPUT_CNTL_9, 0, 0, 0},
553 {R_02866C_SPI_PS_INPUT_CNTL_10, 0, 0, 0},
554 {R_028670_SPI_PS_INPUT_CNTL_11, 0, 0, 0},
555 {R_028674_SPI_PS_INPUT_CNTL_12, 0, 0, 0},
556 {R_028678_SPI_PS_INPUT_CNTL_13, 0, 0, 0},
557 {R_02867C_SPI_PS_INPUT_CNTL_14, 0, 0, 0},
558 {R_028680_SPI_PS_INPUT_CNTL_15, 0, 0, 0},
559 {R_028684_SPI_PS_INPUT_CNTL_16, 0, 0, 0},
560 {R_028688_SPI_PS_INPUT_CNTL_17, 0, 0, 0},
561 {R_02868C_SPI_PS_INPUT_CNTL_18, 0, 0, 0},
562 {R_028690_SPI_PS_INPUT_CNTL_19, 0, 0, 0},
563 {R_028694_SPI_PS_INPUT_CNTL_20, 0, 0, 0},
564 {R_028698_SPI_PS_INPUT_CNTL_21, 0, 0, 0},
565 {R_02869C_SPI_PS_INPUT_CNTL_22, 0, 0, 0},
566 {R_0286A0_SPI_PS_INPUT_CNTL_23, 0, 0, 0},
567 {R_0286A4_SPI_PS_INPUT_CNTL_24, 0, 0, 0},
568 {R_0286A8_SPI_PS_INPUT_CNTL_25, 0, 0, 0},
569 {R_0286AC_SPI_PS_INPUT_CNTL_26, 0, 0, 0},
570 {R_0286B0_SPI_PS_INPUT_CNTL_27, 0, 0, 0},
571 {R_0286B4_SPI_PS_INPUT_CNTL_28, 0, 0, 0},
572 {R_0286B8_SPI_PS_INPUT_CNTL_29, 0, 0, 0},
573 {R_0286BC_SPI_PS_INPUT_CNTL_30, 0, 0, 0},
574 {R_0286C0_SPI_PS_INPUT_CNTL_31, 0, 0, 0},
575 {R_0286CC_SPI_PS_IN_CONTROL_0, 0, 0, 0},
576 {R_0286D0_SPI_PS_IN_CONTROL_1, 0, 0, 0},
577 {R_0286D8_SPI_INPUT_Z, 0, 0, 0},
578 {GROUP_FORCE_NEW_BLOCK, 0, 0, 0},
579 {R_028840_SQ_PGM_START_PS, REG_FLAG_NEED_BO, S_0085F0_SH_ACTION_ENA(1), 0xFFFFFFFF},
580 {GROUP_FORCE_NEW_BLOCK, 0, 0, 0},
581 {R_028850_SQ_PGM_RESOURCES_PS, 0, 0, 0},
582 {R_028854_SQ_PGM_EXPORTS_PS, 0, 0, 0},
583 {R_0288CC_SQ_PGM_CF_OFFSET_PS, 0, 0, 0},
584 {R_028400_VGT_MAX_VTX_INDX, 0, 0, 0},
585 {R_028404_VGT_MIN_VTX_INDX, 0, 0, 0},
586 {R_028408_VGT_INDX_OFFSET, 0, 0, 0},
587 {R_02840C_VGT_MULTI_PRIM_IB_RESET_INDX, 0, 0, 0},
588 {R_028A84_VGT_PRIMITIVEID_EN, 0, 0, 0},
589 {R_028A94_VGT_MULTI_PRIM_IB_RESET_EN, 0, 0, 0},
590 {R_028AA0_VGT_INSTANCE_STEP_RATE_0, 0, 0, 0},
591 {R_028AA4_VGT_INSTANCE_STEP_RATE_1, 0, 0, 0},
592 };
593
594 /* SHADER RESOURCE R600/R700 */
595 int r600_resource_init(struct r600_context *ctx, struct r600_range *range, unsigned offset, unsigned nblocks, unsigned stride, struct r600_reg *reg, int nreg, unsigned offset_base)
596 {
597 int i;
598 struct r600_block *block;
599 range->blocks = calloc(nblocks, sizeof(struct r600_block *));
600 if (range->blocks == NULL)
601 return -ENOMEM;
602
603 reg[0].offset += offset;
604 for (i = 0; i < nblocks; i++) {
605 block = calloc(1, sizeof(struct r600_block));
606 if (block == NULL) {
607 return -ENOMEM;
608 }
609 ctx->nblocks++;
610 range->blocks[i] = block;
611 r600_init_block(ctx, block, reg, 0, nreg, PKT3_SET_RESOURCE, offset_base);
612
613 reg[0].offset += stride;
614 }
615 return 0;
616 }
617
618
619 static int r600_resource_range_init(struct r600_context *ctx, struct r600_range *range, unsigned offset, unsigned nblocks, unsigned stride)
620 {
621 struct r600_reg r600_shader_resource[] = {
622 {R_038000_RESOURCE0_WORD0, REG_FLAG_NEED_BO, S_0085F0_TC_ACTION_ENA(1) | S_0085F0_VC_ACTION_ENA(1), 0xFFFFFFFF},
623 {R_038004_RESOURCE0_WORD1, REG_FLAG_NEED_BO, S_0085F0_TC_ACTION_ENA(1) | S_0085F0_VC_ACTION_ENA(1), 0xFFFFFFFF},
624 {R_038008_RESOURCE0_WORD2, 0, 0, 0},
625 {R_03800C_RESOURCE0_WORD3, 0, 0, 0},
626 {R_038010_RESOURCE0_WORD4, 0, 0, 0},
627 {R_038014_RESOURCE0_WORD5, 0, 0, 0},
628 {R_038018_RESOURCE0_WORD6, 0, 0, 0},
629 };
630 unsigned nreg = Elements(r600_shader_resource);
631
632 return r600_resource_init(ctx, range, offset, nblocks, stride, r600_shader_resource, nreg, R600_RESOURCE_OFFSET);
633 }
634
635 /* SHADER SAMPLER R600/R700 */
636 static int r600_state_sampler_init(struct r600_context *ctx, u32 offset)
637 {
638 struct r600_reg r600_shader_sampler[] = {
639 {R_03C000_SQ_TEX_SAMPLER_WORD0_0, 0, 0, 0},
640 {R_03C004_SQ_TEX_SAMPLER_WORD1_0, 0, 0, 0},
641 {R_03C008_SQ_TEX_SAMPLER_WORD2_0, 0, 0, 0},
642 };
643 unsigned nreg = Elements(r600_shader_sampler);
644
645 for (int i = 0; i < nreg; i++) {
646 r600_shader_sampler[i].offset += offset;
647 }
648 return r600_context_add_block(ctx, r600_shader_sampler, nreg, PKT3_SET_SAMPLER, R600_SAMPLER_OFFSET);
649 }
650
651 /* SHADER SAMPLER BORDER R600/R700 */
652 static int r600_state_sampler_border_init(struct r600_context *ctx, u32 offset)
653 {
654 struct r600_reg r600_shader_sampler_border[] = {
655 {R_00A400_TD_PS_SAMPLER0_BORDER_RED, 0, 0, 0},
656 {R_00A404_TD_PS_SAMPLER0_BORDER_GREEN, 0, 0, 0},
657 {R_00A408_TD_PS_SAMPLER0_BORDER_BLUE, 0, 0, 0},
658 {R_00A40C_TD_PS_SAMPLER0_BORDER_ALPHA, 0, 0, 0},
659 };
660 unsigned nreg = Elements(r600_shader_sampler_border);
661
662 for (int i = 0; i < nreg; i++) {
663 r600_shader_sampler_border[i].offset += offset;
664 }
665 return r600_context_add_block(ctx, r600_shader_sampler_border, nreg, PKT3_SET_CONFIG_REG, R600_CONFIG_REG_OFFSET);
666 }
667
668 static int r600_loop_const_init(struct r600_context *ctx, u32 offset)
669 {
670 unsigned nreg = 32;
671 struct r600_reg r600_loop_consts[32];
672 int i;
673
674 for (i = 0; i < nreg; i++) {
675 r600_loop_consts[i].offset = R600_LOOP_CONST_OFFSET + ((offset + i) * 4);
676 r600_loop_consts[i].flags = REG_FLAG_DIRTY_ALWAYS;
677 r600_loop_consts[i].flush_flags = 0;
678 r600_loop_consts[i].flush_mask = 0;
679 }
680 return r600_context_add_block(ctx, r600_loop_consts, nreg, PKT3_SET_LOOP_CONST, R600_LOOP_CONST_OFFSET);
681 }
682
683 static void r600_context_clear_fenced_bo(struct r600_context *ctx)
684 {
685 struct radeon_bo *bo, *tmp;
686
687 LIST_FOR_EACH_ENTRY_SAFE(bo, tmp, &ctx->fenced_bo, fencedlist) {
688 LIST_DELINIT(&bo->fencedlist);
689 bo->fence = 0;
690 bo->ctx = NULL;
691 }
692 }
693
694 static void r600_free_resource_range(struct r600_context *ctx, struct r600_range *range, int nblocks)
695 {
696 struct r600_block *block;
697 int i;
698 for (i = 0; i < nblocks; i++) {
699 block = range->blocks[i];
700 if (block) {
701 for (int k = 1; k <= block->nbo; k++)
702 r600_bo_reference(ctx->radeon, &block->reloc[k].bo, NULL);
703 free(block);
704 }
705 }
706 free(range->blocks);
707
708 }
709
710 /* initialize */
711 void r600_context_fini(struct r600_context *ctx)
712 {
713 struct r600_block *block;
714 struct r600_range *range;
715
716 for (int i = 0; i < NUM_RANGES; i++) {
717 if (!ctx->range[i].blocks)
718 continue;
719 for (int j = 0; j < (1 << HASH_SHIFT); j++) {
720 block = ctx->range[i].blocks[j];
721 if (block) {
722 for (int k = 0, offset = block->start_offset; k < block->nreg; k++, offset += 4) {
723 range = &ctx->range[CTX_RANGE_ID(offset)];
724 range->blocks[CTX_BLOCK_ID(offset)] = NULL;
725 }
726 for (int k = 1; k <= block->nbo; k++) {
727 r600_bo_reference(ctx->radeon, &block->reloc[k].bo, NULL);
728 }
729 free(block);
730 }
731 }
732 free(ctx->range[i].blocks);
733 }
734 r600_free_resource_range(ctx, &ctx->ps_resources, ctx->num_ps_resources);
735 r600_free_resource_range(ctx, &ctx->vs_resources, ctx->num_vs_resources);
736 r600_free_resource_range(ctx, &ctx->fs_resources, ctx->num_fs_resources);
737 free(ctx->range);
738 free(ctx->blocks);
739 free(ctx->reloc);
740 free(ctx->bo);
741 free(ctx->pm4);
742
743 r600_context_clear_fenced_bo(ctx);
744 memset(ctx, 0, sizeof(struct r600_context));
745 }
746
747 static void r600_add_resource_block(struct r600_context *ctx, struct r600_range *range, int num_blocks, int *index)
748 {
749 int c = *index;
750 for (int j = 0; j < num_blocks; j++) {
751 if (!range->blocks[j])
752 continue;
753
754 ctx->blocks[c++] = range->blocks[j];
755 }
756 *index = c;
757 }
758
759 int r600_setup_block_table(struct r600_context *ctx)
760 {
761 /* setup block table */
762 int c = 0;
763 ctx->blocks = calloc(ctx->nblocks, sizeof(void*));
764 if (!ctx->blocks)
765 return -ENOMEM;
766 for (int i = 0; i < NUM_RANGES; i++) {
767 if (!ctx->range[i].blocks)
768 continue;
769 for (int j = 0, add; j < (1 << HASH_SHIFT); j++) {
770 if (!ctx->range[i].blocks[j])
771 continue;
772
773 add = 1;
774 for (int k = 0; k < c; k++) {
775 if (ctx->blocks[k] == ctx->range[i].blocks[j]) {
776 add = 0;
777 break;
778 }
779 }
780 if (add) {
781 assert(c < ctx->nblocks);
782 ctx->blocks[c++] = ctx->range[i].blocks[j];
783 j += (ctx->range[i].blocks[j]->nreg) - 1;
784 }
785 }
786 }
787
788 r600_add_resource_block(ctx, &ctx->ps_resources, ctx->num_ps_resources, &c);
789 r600_add_resource_block(ctx, &ctx->vs_resources, ctx->num_vs_resources, &c);
790 r600_add_resource_block(ctx, &ctx->fs_resources, ctx->num_fs_resources, &c);
791 return 0;
792 }
793
794 int r600_context_init(struct r600_context *ctx, struct radeon *radeon)
795 {
796 int r;
797
798 memset(ctx, 0, sizeof(struct r600_context));
799 ctx->radeon = radeon;
800 LIST_INITHEAD(&ctx->query_list);
801
802 /* init dirty list */
803 LIST_INITHEAD(&ctx->dirty);
804 LIST_INITHEAD(&ctx->resource_dirty);
805 LIST_INITHEAD(&ctx->enable_list);
806
807 ctx->range = calloc(NUM_RANGES, sizeof(struct r600_range));
808 if (!ctx->range) {
809 r = -ENOMEM;
810 goto out_err;
811 }
812
813 /* add blocks */
814 r = r600_context_add_block(ctx, r600_config_reg_list,
815 Elements(r600_config_reg_list), PKT3_SET_CONFIG_REG, R600_CONFIG_REG_OFFSET);
816 if (r)
817 goto out_err;
818 r = r600_context_add_block(ctx, r600_context_reg_list,
819 Elements(r600_context_reg_list), PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET);
820 if (r)
821 goto out_err;
822 r = r600_context_add_block(ctx, r600_ctl_const_list,
823 Elements(r600_ctl_const_list), PKT3_SET_CTL_CONST, R600_CTL_CONST_OFFSET);
824 if (r)
825 goto out_err;
826
827 /* PS SAMPLER BORDER */
828 for (int j = 0, offset = 0; j < 18; j++, offset += 0x10) {
829 r = r600_state_sampler_border_init(ctx, offset);
830 if (r)
831 goto out_err;
832 }
833
834 /* VS SAMPLER BORDER */
835 for (int j = 0, offset = 0x200; j < 18; j++, offset += 0x10) {
836 r = r600_state_sampler_border_init(ctx, offset);
837 if (r)
838 goto out_err;
839 }
840 /* PS SAMPLER */
841 for (int j = 0, offset = 0; j < 18; j++, offset += 0xC) {
842 r = r600_state_sampler_init(ctx, offset);
843 if (r)
844 goto out_err;
845 }
846 /* VS SAMPLER */
847 for (int j = 0, offset = 0xD8; j < 18; j++, offset += 0xC) {
848 r = r600_state_sampler_init(ctx, offset);
849 if (r)
850 goto out_err;
851 }
852
853 ctx->num_ps_resources = 160;
854 ctx->num_vs_resources = 160;
855 ctx->num_fs_resources = 16;
856 r = r600_resource_range_init(ctx, &ctx->ps_resources, 0, 160, 0x1c);
857 if (r)
858 goto out_err;
859 r = r600_resource_range_init(ctx, &ctx->vs_resources, 0x1180, 160, 0x1c);
860 if (r)
861 goto out_err;
862 r = r600_resource_range_init(ctx, &ctx->fs_resources, 0x2300, 16, 0x1c);
863 if (r)
864 goto out_err;
865
866 /* PS loop const */
867 r600_loop_const_init(ctx, 0);
868 /* VS loop const */
869 r600_loop_const_init(ctx, 32);
870
871 r = r600_setup_block_table(ctx);
872 if (r)
873 goto out_err;
874
875 /* allocate cs variables */
876 ctx->nreloc = RADEON_CTX_MAX_PM4;
877 ctx->reloc = calloc(ctx->nreloc, sizeof(struct r600_reloc));
878 if (ctx->reloc == NULL) {
879 r = -ENOMEM;
880 goto out_err;
881 }
882 ctx->bo = calloc(ctx->nreloc, sizeof(void *));
883 if (ctx->bo == NULL) {
884 r = -ENOMEM;
885 goto out_err;
886 }
887 ctx->pm4_ndwords = RADEON_CTX_MAX_PM4;
888 ctx->pm4 = calloc(ctx->pm4_ndwords, 4);
889 if (ctx->pm4 == NULL) {
890 r = -ENOMEM;
891 goto out_err;
892 }
893
894 r600_init_cs(ctx);
895 /* save 16dwords space for fence mecanism */
896 ctx->pm4_ndwords -= 16;
897
898 LIST_INITHEAD(&ctx->fenced_bo);
899
900 ctx->max_db = 4;
901
902 return 0;
903 out_err:
904 r600_context_fini(ctx);
905 return r;
906 }
907
908 /* Flushes all surfaces */
909 void r600_context_flush_all(struct r600_context *ctx, unsigned flush_flags)
910 {
911 unsigned ndwords = 5;
912
913 if ((ctx->pm4_dirty_cdwords + ndwords + ctx->pm4_cdwords) > ctx->pm4_ndwords) {
914 /* need to flush */
915 r600_context_flush(ctx);
916 }
917
918 ctx->pm4[ctx->pm4_cdwords++] = PKT3(PKT3_SURFACE_SYNC, 3, ctx->predicate_drawing);
919 ctx->pm4[ctx->pm4_cdwords++] = flush_flags; /* CP_COHER_CNTL */
920 ctx->pm4[ctx->pm4_cdwords++] = 0xffffffff; /* CP_COHER_SIZE */
921 ctx->pm4[ctx->pm4_cdwords++] = 0; /* CP_COHER_BASE */
922 ctx->pm4[ctx->pm4_cdwords++] = 0x0000000A; /* POLL_INTERVAL */
923 }
924
925 void r600_context_bo_flush(struct r600_context *ctx, unsigned flush_flags,
926 unsigned flush_mask, struct r600_bo *rbo)
927 {
928 struct radeon_bo *bo;
929
930 bo = rbo->bo;
931 /* if bo has already been flushed */
932 if (!(~bo->last_flush & flush_flags)) {
933 bo->last_flush &= flush_mask;
934 return;
935 }
936
937 if ((ctx->radeon->family < CHIP_RV770) &&
938 (G_0085F0_CB_ACTION_ENA(flush_flags) ||
939 G_0085F0_DB_ACTION_ENA(flush_flags))) {
940 if (ctx->flags & R600_CONTEXT_CHECK_EVENT_FLUSH) {
941 /* the rv670 seems to fail fbo-generatemipmap unless we flush the CB1 dest base ena */
942 if ((bo->binding & BO_BOUND_TEXTURE) &&
943 (flush_flags & S_0085F0_CB_ACTION_ENA(1))) {
944 if ((ctx->radeon->family == CHIP_RV670) ||
945 (ctx->radeon->family == CHIP_RS780) ||
946 (ctx->radeon->family == CHIP_RS880)) {
947 ctx->pm4[ctx->pm4_cdwords++] = PKT3(PKT3_SURFACE_SYNC, 3, ctx->predicate_drawing);
948 ctx->pm4[ctx->pm4_cdwords++] = S_0085F0_CB1_DEST_BASE_ENA(1); /* CP_COHER_CNTL */
949 ctx->pm4[ctx->pm4_cdwords++] = 0xffffffff; /* CP_COHER_SIZE */
950 ctx->pm4[ctx->pm4_cdwords++] = 0; /* CP_COHER_BASE */
951 ctx->pm4[ctx->pm4_cdwords++] = 0x0000000A; /* POLL_INTERVAL */
952 }
953 }
954
955 ctx->pm4[ctx->pm4_cdwords++] = PKT3(PKT3_EVENT_WRITE, 0, ctx->predicate_drawing);
956 ctx->pm4[ctx->pm4_cdwords++] = EVENT_TYPE(EVENT_TYPE_CACHE_FLUSH_AND_INV_EVENT) | EVENT_INDEX(0);
957 ctx->flags &= ~R600_CONTEXT_CHECK_EVENT_FLUSH;
958 }
959 } else {
960 ctx->pm4[ctx->pm4_cdwords++] = PKT3(PKT3_SURFACE_SYNC, 3, ctx->predicate_drawing);
961 ctx->pm4[ctx->pm4_cdwords++] = flush_flags;
962 ctx->pm4[ctx->pm4_cdwords++] = (bo->size + 255) >> 8;
963 ctx->pm4[ctx->pm4_cdwords++] = 0x00000000;
964 ctx->pm4[ctx->pm4_cdwords++] = 0x0000000A;
965 ctx->pm4[ctx->pm4_cdwords++] = PKT3(PKT3_NOP, 0, ctx->predicate_drawing);
966 ctx->pm4[ctx->pm4_cdwords++] = bo->reloc_id;
967 }
968 bo->last_flush = (bo->last_flush | flush_flags) & flush_mask;
969 }
970
971 void r600_context_get_reloc(struct r600_context *ctx, struct r600_bo *rbo)
972 {
973 struct radeon_bo *bo = rbo->bo;
974 bo->reloc = &ctx->reloc[ctx->creloc];
975 bo->reloc_id = ctx->creloc * sizeof(struct r600_reloc) / 4;
976 ctx->reloc[ctx->creloc].handle = bo->handle;
977 ctx->reloc[ctx->creloc].read_domain = rbo->domains & (RADEON_GEM_DOMAIN_GTT | RADEON_GEM_DOMAIN_VRAM);
978 ctx->reloc[ctx->creloc].write_domain = rbo->domains & (RADEON_GEM_DOMAIN_GTT | RADEON_GEM_DOMAIN_VRAM);
979 ctx->reloc[ctx->creloc].flags = 0;
980 radeon_bo_reference(ctx->radeon, &ctx->bo[ctx->creloc], bo);
981 rbo->fence = ctx->radeon->fence;
982 ctx->creloc++;
983 }
984
985 void r600_context_reg(struct r600_context *ctx,
986 unsigned offset, unsigned value,
987 unsigned mask)
988 {
989 struct r600_range *range;
990 struct r600_block *block;
991 unsigned id;
992 unsigned new_val;
993 int dirty;
994
995 range = &ctx->range[CTX_RANGE_ID(offset)];
996 block = range->blocks[CTX_BLOCK_ID(offset)];
997 id = (offset - block->start_offset) >> 2;
998
999 dirty = block->status & R600_BLOCK_STATUS_DIRTY;
1000
1001 new_val = block->reg[id];
1002 new_val &= ~mask;
1003 new_val |= value;
1004 if (new_val != block->reg[id]) {
1005 dirty |= R600_BLOCK_STATUS_DIRTY;
1006 block->reg[id] = new_val;
1007 }
1008 if (dirty)
1009 r600_context_dirty_block(ctx, block, dirty, id);
1010 }
1011
1012 void r600_context_dirty_block(struct r600_context *ctx,
1013 struct r600_block *block,
1014 int dirty, int index)
1015 {
1016 if ((index + 1) > block->nreg_dirty)
1017 block->nreg_dirty = index + 1;
1018
1019 if ((dirty != (block->status & R600_BLOCK_STATUS_DIRTY)) || !(block->status & R600_BLOCK_STATUS_ENABLED)) {
1020 block->status |= R600_BLOCK_STATUS_DIRTY;
1021 ctx->pm4_dirty_cdwords += block->pm4_ndwords + block->pm4_flush_ndwords;
1022 if (!(block->status & R600_BLOCK_STATUS_ENABLED)) {
1023 block->status |= R600_BLOCK_STATUS_ENABLED;
1024 LIST_ADDTAIL(&block->enable_list, &ctx->enable_list);
1025 }
1026 LIST_ADDTAIL(&block->list,&ctx->dirty);
1027
1028 if (block->flags & REG_FLAG_FLUSH_CHANGE) {
1029 r600_context_ps_partial_flush(ctx);
1030 }
1031 }
1032 }
1033
1034 void r600_context_pipe_state_set(struct r600_context *ctx, struct r600_pipe_state *state)
1035 {
1036 struct r600_block *block;
1037 unsigned new_val;
1038 int dirty;
1039 for (int i = 0; i < state->nregs; i++) {
1040 unsigned id, reloc_id;
1041 struct r600_pipe_reg *reg = &state->regs[i];
1042
1043 block = reg->block;
1044 id = reg->id;
1045
1046 dirty = block->status & R600_BLOCK_STATUS_DIRTY;
1047
1048 new_val = block->reg[id];
1049 new_val &= ~reg->mask;
1050 new_val |= reg->value;
1051 if (new_val != block->reg[id]) {
1052 block->reg[id] = new_val;
1053 dirty |= R600_BLOCK_STATUS_DIRTY;
1054 }
1055 if (block->flags & REG_FLAG_DIRTY_ALWAYS)
1056 dirty |= R600_BLOCK_STATUS_DIRTY;
1057 if (block->pm4_bo_index[id]) {
1058 /* find relocation */
1059 reloc_id = block->pm4_bo_index[id];
1060 r600_bo_reference(ctx->radeon, &block->reloc[reloc_id].bo, reg->bo);
1061 reg->bo->fence = ctx->radeon->fence;
1062 /* always force dirty for relocs for now */
1063 dirty |= R600_BLOCK_STATUS_DIRTY;
1064 }
1065
1066 if (dirty)
1067 r600_context_dirty_block(ctx, block, dirty, id);
1068 }
1069 }
1070
1071 static void r600_context_dirty_resource_block(struct r600_context *ctx,
1072 struct r600_block *block,
1073 int dirty, int index)
1074 {
1075 block->nreg_dirty = index + 1;
1076
1077 if ((dirty != (block->status & R600_BLOCK_STATUS_RESOURCE_DIRTY)) || !(block->status & R600_BLOCK_STATUS_ENABLED)) {
1078 block->status |= R600_BLOCK_STATUS_RESOURCE_DIRTY;
1079 ctx->pm4_dirty_cdwords += block->pm4_ndwords + block->pm4_flush_ndwords;
1080 if (!(block->status & R600_BLOCK_STATUS_ENABLED)) {
1081 block->status |= R600_BLOCK_STATUS_ENABLED;
1082 LIST_ADDTAIL(&block->enable_list, &ctx->enable_list);
1083 }
1084 LIST_ADDTAIL(&block->list,&ctx->resource_dirty);
1085 }
1086 }
1087
1088 void r600_context_pipe_state_set_resource(struct r600_context *ctx, struct r600_pipe_resource_state *state, struct r600_block *block)
1089 {
1090 int dirty;
1091 int num_regs = ctx->radeon->chip_class >= EVERGREEN ? 8 : 7;
1092 boolean is_vertex;
1093
1094 if (state == NULL) {
1095 block->status &= ~(R600_BLOCK_STATUS_ENABLED | R600_BLOCK_STATUS_RESOURCE_DIRTY);
1096 if (block->reloc[1].bo)
1097 block->reloc[1].bo->bo->binding &= ~BO_BOUND_TEXTURE;
1098
1099 r600_bo_reference(ctx->radeon, &block->reloc[1].bo, NULL);
1100 r600_bo_reference(ctx->radeon, &block->reloc[2].bo, NULL);
1101 LIST_DELINIT(&block->list);
1102 LIST_DELINIT(&block->enable_list);
1103 return;
1104 }
1105
1106 is_vertex = ((state->val[num_regs-1] & 0xc0000000) == 0xc0000000);
1107 dirty = block->status & R600_BLOCK_STATUS_RESOURCE_DIRTY;
1108
1109 if (memcmp(block->reg, state->val, num_regs*4)) {
1110 memcpy(block->reg, state->val, num_regs * 4);
1111 dirty |= R600_BLOCK_STATUS_RESOURCE_DIRTY;
1112 }
1113
1114 /* if no BOs on block, force dirty */
1115 if (!block->reloc[1].bo || !block->reloc[2].bo)
1116 dirty |= R600_BLOCK_STATUS_RESOURCE_DIRTY;
1117
1118 if (!dirty) {
1119 if (is_vertex) {
1120 if (block->reloc[1].bo->bo->handle != state->bo[0]->bo->handle)
1121 dirty |= R600_BLOCK_STATUS_RESOURCE_DIRTY;
1122 } else {
1123 if ((block->reloc[1].bo->bo->handle != state->bo[0]->bo->handle) ||
1124 (block->reloc[2].bo->bo->handle != state->bo[1]->bo->handle))
1125 dirty |= R600_BLOCK_STATUS_RESOURCE_DIRTY;
1126 }
1127 }
1128 if (!dirty) {
1129 if (is_vertex)
1130 state->bo[0]->fence = ctx->radeon->fence;
1131 else {
1132 state->bo[0]->fence = ctx->radeon->fence;
1133 state->bo[1]->fence = ctx->radeon->fence;
1134 }
1135 } else {
1136 if (is_vertex) {
1137 /* VERTEX RESOURCE, we preted there is 2 bo to relocate so
1138 * we have single case btw VERTEX & TEXTURE resource
1139 */
1140 r600_bo_reference(ctx->radeon, &block->reloc[1].bo, state->bo[0]);
1141 r600_bo_reference(ctx->radeon, &block->reloc[2].bo, NULL);
1142 state->bo[0]->fence = ctx->radeon->fence;
1143 } else {
1144 /* TEXTURE RESOURCE */
1145 r600_bo_reference(ctx->radeon, &block->reloc[1].bo, state->bo[0]);
1146 r600_bo_reference(ctx->radeon, &block->reloc[2].bo, state->bo[1]);
1147 state->bo[0]->fence = ctx->radeon->fence;
1148 state->bo[1]->fence = ctx->radeon->fence;
1149 state->bo[0]->bo->binding |= BO_BOUND_TEXTURE;
1150 }
1151 }
1152 if (dirty) {
1153 if (is_vertex)
1154 block->status |= R600_BLOCK_STATUS_RESOURCE_VERTEX;
1155 else
1156 block->status &= ~R600_BLOCK_STATUS_RESOURCE_VERTEX;
1157
1158 r600_context_dirty_resource_block(ctx, block, dirty, num_regs - 1);
1159 }
1160 }
1161
1162 void r600_context_pipe_state_set_ps_resource(struct r600_context *ctx, struct r600_pipe_resource_state *state, unsigned rid)
1163 {
1164 struct r600_block *block = ctx->ps_resources.blocks[rid];
1165
1166 r600_context_pipe_state_set_resource(ctx, state, block);
1167 }
1168
1169 void r600_context_pipe_state_set_vs_resource(struct r600_context *ctx, struct r600_pipe_resource_state *state, unsigned rid)
1170 {
1171 struct r600_block *block = ctx->vs_resources.blocks[rid];
1172
1173 r600_context_pipe_state_set_resource(ctx, state, block);
1174 }
1175
1176 void r600_context_pipe_state_set_fs_resource(struct r600_context *ctx, struct r600_pipe_resource_state *state, unsigned rid)
1177 {
1178 struct r600_block *block = ctx->fs_resources.blocks[rid];
1179
1180 r600_context_pipe_state_set_resource(ctx, state, block);
1181 }
1182
1183 static inline void r600_context_pipe_state_set_sampler(struct r600_context *ctx, struct r600_pipe_state *state, unsigned offset)
1184 {
1185 struct r600_range *range;
1186 struct r600_block *block;
1187 int i;
1188 int dirty;
1189
1190 range = &ctx->range[CTX_RANGE_ID(offset)];
1191 block = range->blocks[CTX_BLOCK_ID(offset)];
1192 if (state == NULL) {
1193 block->status &= ~(R600_BLOCK_STATUS_ENABLED | R600_BLOCK_STATUS_DIRTY);
1194 LIST_DELINIT(&block->list);
1195 LIST_DELINIT(&block->enable_list);
1196 return;
1197 }
1198 dirty = block->status & R600_BLOCK_STATUS_DIRTY;
1199 for (i = 0; i < 3; i++) {
1200 if (block->reg[i] != state->regs[i].value) {
1201 block->reg[i] = state->regs[i].value;
1202 dirty |= R600_BLOCK_STATUS_DIRTY;
1203 }
1204 }
1205
1206 if (dirty)
1207 r600_context_dirty_block(ctx, block, dirty, 2);
1208 }
1209
1210
1211 static inline void r600_context_pipe_state_set_sampler_border(struct r600_context *ctx, struct r600_pipe_state *state, unsigned offset)
1212 {
1213 struct r600_range *range;
1214 struct r600_block *block;
1215 int i;
1216 int dirty;
1217
1218 range = &ctx->range[CTX_RANGE_ID(offset)];
1219 block = range->blocks[CTX_BLOCK_ID(offset)];
1220 if (state == NULL) {
1221 block->status &= ~(R600_BLOCK_STATUS_ENABLED | R600_BLOCK_STATUS_DIRTY);
1222 LIST_DELINIT(&block->list);
1223 LIST_DELINIT(&block->enable_list);
1224 return;
1225 }
1226 if (state->nregs <= 3) {
1227 return;
1228 }
1229 dirty = block->status & R600_BLOCK_STATUS_DIRTY;
1230 for (i = 0; i < 4; i++) {
1231 if (block->reg[i] != state->regs[i + 3].value) {
1232 block->reg[i] = state->regs[i + 3].value;
1233 dirty |= R600_BLOCK_STATUS_DIRTY;
1234 }
1235 }
1236
1237 /* We have to flush the shaders before we change the border color
1238 * registers, or previous draw commands that haven't completed yet
1239 * will end up using the new border color. */
1240 if (dirty & R600_BLOCK_STATUS_DIRTY)
1241 r600_context_ps_partial_flush(ctx);
1242 if (dirty)
1243 r600_context_dirty_block(ctx, block, dirty, 3);
1244 }
1245
1246 void r600_context_pipe_state_set_ps_sampler(struct r600_context *ctx, struct r600_pipe_state *state, unsigned id)
1247 {
1248 unsigned offset;
1249
1250 offset = 0x0003C000 + id * 0xc;
1251 r600_context_pipe_state_set_sampler(ctx, state, offset);
1252 offset = 0x0000A400 + id * 0x10;
1253 r600_context_pipe_state_set_sampler_border(ctx, state, offset);
1254 }
1255
1256 void r600_context_pipe_state_set_vs_sampler(struct r600_context *ctx, struct r600_pipe_state *state, unsigned id)
1257 {
1258 unsigned offset;
1259
1260 offset = 0x0003C0D8 + id * 0xc;
1261 r600_context_pipe_state_set_sampler(ctx, state, offset);
1262 offset = 0x0000A600 + id * 0x10;
1263 r600_context_pipe_state_set_sampler_border(ctx, state, offset);
1264 }
1265
1266 struct r600_bo *r600_context_reg_bo(struct r600_context *ctx, unsigned offset)
1267 {
1268 struct r600_range *range;
1269 struct r600_block *block;
1270 unsigned id;
1271
1272 range = &ctx->range[CTX_RANGE_ID(offset)];
1273 block = range->blocks[CTX_BLOCK_ID(offset)];
1274 offset -= block->start_offset;
1275 id = block->pm4_bo_index[offset >> 2];
1276 if (block->reloc[id].bo) {
1277 return block->reloc[id].bo;
1278 }
1279 return NULL;
1280 }
1281
1282 void r600_context_block_emit_dirty(struct r600_context *ctx, struct r600_block *block)
1283 {
1284 int id;
1285 int optional = block->nbo == 0 && !(block->flags & REG_FLAG_DIRTY_ALWAYS);
1286 int cp_dwords = block->pm4_ndwords, start_dword = 0;
1287 int new_dwords = 0;
1288 int nbo = block->nbo;
1289
1290 if (block->nreg_dirty == 0 && optional) {
1291 goto out;
1292 }
1293
1294 if (nbo) {
1295 ctx->flags |= R600_CONTEXT_CHECK_EVENT_FLUSH;
1296
1297 for (int j = 0; j < block->nreg; j++) {
1298 if (block->pm4_bo_index[j]) {
1299 /* find relocation */
1300 id = block->pm4_bo_index[j];
1301 r600_context_bo_reloc(ctx,
1302 &block->pm4[block->reloc[id].bo_pm4_index],
1303 block->reloc[id].bo);
1304 r600_context_bo_flush(ctx,
1305 block->reloc[id].flush_flags,
1306 block->reloc[id].flush_mask,
1307 block->reloc[id].bo);
1308 nbo--;
1309 if (nbo == 0)
1310 break;
1311 }
1312 }
1313 ctx->flags &= ~R600_CONTEXT_CHECK_EVENT_FLUSH;
1314 }
1315
1316 optional &= (block->nreg_dirty != block->nreg);
1317 if (optional) {
1318 new_dwords = block->nreg_dirty;
1319 start_dword = ctx->pm4_cdwords;
1320 cp_dwords = new_dwords + 2;
1321 }
1322 memcpy(&ctx->pm4[ctx->pm4_cdwords], block->pm4, cp_dwords * 4);
1323 ctx->pm4_cdwords += cp_dwords;
1324
1325 if (optional) {
1326 uint32_t newword;
1327
1328 newword = ctx->pm4[start_dword];
1329 newword &= PKT_COUNT_C;
1330 newword |= PKT_COUNT_S(new_dwords);
1331 ctx->pm4[start_dword] = newword;
1332 }
1333 out:
1334 block->status ^= R600_BLOCK_STATUS_DIRTY;
1335 block->nreg_dirty = 0;
1336 LIST_DELINIT(&block->list);
1337 }
1338
1339 void r600_context_block_resource_emit_dirty(struct r600_context *ctx, struct r600_block *block)
1340 {
1341 int id;
1342 int cp_dwords = block->pm4_ndwords;
1343 int nbo = block->nbo;
1344
1345 ctx->flags |= R600_CONTEXT_CHECK_EVENT_FLUSH;
1346
1347 if (block->status & R600_BLOCK_STATUS_RESOURCE_VERTEX) {
1348 nbo = 1;
1349 cp_dwords -= 2; /* don't copy the second NOP */
1350 }
1351
1352 for (int j = 0; j < nbo; j++) {
1353 if (block->pm4_bo_index[j]) {
1354 /* find relocation */
1355 id = block->pm4_bo_index[j];
1356 r600_context_bo_reloc(ctx,
1357 &block->pm4[block->reloc[id].bo_pm4_index],
1358 block->reloc[id].bo);
1359 r600_context_bo_flush(ctx,
1360 block->reloc[id].flush_flags,
1361 block->reloc[id].flush_mask,
1362 block->reloc[id].bo);
1363 }
1364 }
1365 ctx->flags &= ~R600_CONTEXT_CHECK_EVENT_FLUSH;
1366
1367 memcpy(&ctx->pm4[ctx->pm4_cdwords], block->pm4, cp_dwords * 4);
1368 ctx->pm4_cdwords += cp_dwords;
1369
1370 block->status ^= R600_BLOCK_STATUS_RESOURCE_DIRTY;
1371 block->nreg_dirty = 0;
1372 LIST_DELINIT(&block->list);
1373 }
1374
1375 void r600_context_flush_dest_caches(struct r600_context *ctx)
1376 {
1377 struct r600_bo *cb[8];
1378 struct r600_bo *db;
1379 int i;
1380
1381 if (!(ctx->flags & R600_CONTEXT_DST_CACHES_DIRTY))
1382 return;
1383
1384 db = r600_context_reg_bo(ctx, R_02800C_DB_DEPTH_BASE);
1385 cb[0] = r600_context_reg_bo(ctx, R_028040_CB_COLOR0_BASE);
1386 cb[1] = r600_context_reg_bo(ctx, R_028044_CB_COLOR1_BASE);
1387 cb[2] = r600_context_reg_bo(ctx, R_028048_CB_COLOR2_BASE);
1388 cb[3] = r600_context_reg_bo(ctx, R_02804C_CB_COLOR3_BASE);
1389 cb[4] = r600_context_reg_bo(ctx, R_028050_CB_COLOR4_BASE);
1390 cb[5] = r600_context_reg_bo(ctx, R_028054_CB_COLOR5_BASE);
1391 cb[6] = r600_context_reg_bo(ctx, R_028058_CB_COLOR6_BASE);
1392 cb[7] = r600_context_reg_bo(ctx, R_02805C_CB_COLOR7_BASE);
1393
1394 ctx->flags |= R600_CONTEXT_CHECK_EVENT_FLUSH;
1395 /* flush the color buffers */
1396 for (i = 0; i < 8; i++) {
1397 if (!cb[i])
1398 continue;
1399
1400 r600_context_bo_flush(ctx,
1401 (S_0085F0_CB0_DEST_BASE_ENA(1) << i) |
1402 S_0085F0_CB_ACTION_ENA(1),
1403 0, cb[i]);
1404 }
1405 if (db) {
1406 r600_context_bo_flush(ctx, S_0085F0_DB_ACTION_ENA(1) | S_0085F0_DB_DEST_BASE_ENA(1), 0, db);
1407 }
1408 ctx->flags &= ~R600_CONTEXT_CHECK_EVENT_FLUSH;
1409 ctx->flags &= ~R600_CONTEXT_DST_CACHES_DIRTY;
1410 }
1411
1412 void r600_context_draw(struct r600_context *ctx, const struct r600_draw *draw)
1413 {
1414 unsigned ndwords = 7;
1415 struct r600_block *dirty_block = NULL;
1416 struct r600_block *next_block;
1417 uint32_t *pm4;
1418
1419 if (draw->indices) {
1420 ndwords = 11;
1421 /* make sure there is enough relocation space before scheduling draw */
1422 if (ctx->creloc >= (ctx->nreloc - 1)) {
1423 r600_context_flush(ctx);
1424 }
1425 }
1426
1427 /* queries need some special values */
1428 if (ctx->num_query_running) {
1429 if (ctx->radeon->family >= CHIP_RV770) {
1430 r600_context_reg(ctx,
1431 R_028D0C_DB_RENDER_CONTROL,
1432 S_028D0C_R700_PERFECT_ZPASS_COUNTS(1),
1433 S_028D0C_R700_PERFECT_ZPASS_COUNTS(1));
1434 }
1435 r600_context_reg(ctx,
1436 R_028D10_DB_RENDER_OVERRIDE,
1437 S_028D10_NOOP_CULL_DISABLE(1),
1438 S_028D10_NOOP_CULL_DISABLE(1));
1439 }
1440
1441 /* update the max dword count to make sure we have enough space
1442 * reserved for flushing the destination caches */
1443 ctx->pm4_ndwords = RADEON_CTX_MAX_PM4 - ctx->num_dest_buffers * 7 - 16;
1444
1445 if ((ctx->pm4_dirty_cdwords + ndwords + ctx->pm4_cdwords) > ctx->pm4_ndwords) {
1446 /* need to flush */
1447 r600_context_flush(ctx);
1448 }
1449 /* at that point everythings is flushed and ctx->pm4_cdwords = 0 */
1450 if ((ctx->pm4_dirty_cdwords + ndwords) > ctx->pm4_ndwords) {
1451 R600_ERR("context is too big to be scheduled\n");
1452 return;
1453 }
1454 /* enough room to copy packet */
1455 LIST_FOR_EACH_ENTRY_SAFE(dirty_block, next_block, &ctx->dirty, list) {
1456 r600_context_block_emit_dirty(ctx, dirty_block);
1457 }
1458
1459 LIST_FOR_EACH_ENTRY_SAFE(dirty_block, next_block, &ctx->resource_dirty, list) {
1460 r600_context_block_resource_emit_dirty(ctx, dirty_block);
1461 }
1462
1463 /* draw packet */
1464 pm4 = &ctx->pm4[ctx->pm4_cdwords];
1465
1466 pm4[0] = PKT3(PKT3_INDEX_TYPE, 0, ctx->predicate_drawing);
1467 pm4[1] = draw->vgt_index_type;
1468 pm4[2] = PKT3(PKT3_NUM_INSTANCES, 0, ctx->predicate_drawing);
1469 pm4[3] = draw->vgt_num_instances;
1470 if (draw->indices) {
1471 pm4[4] = PKT3(PKT3_DRAW_INDEX, 3, ctx->predicate_drawing);
1472 pm4[5] = draw->indices_bo_offset + r600_bo_offset(draw->indices);
1473 pm4[6] = 0;
1474 pm4[7] = draw->vgt_num_indices;
1475 pm4[8] = draw->vgt_draw_initiator;
1476 pm4[9] = PKT3(PKT3_NOP, 0, ctx->predicate_drawing);
1477 pm4[10] = 0;
1478 r600_context_bo_reloc(ctx, &pm4[10], draw->indices);
1479 } else {
1480 pm4[4] = PKT3(PKT3_DRAW_INDEX_AUTO, 1, ctx->predicate_drawing);
1481 pm4[5] = draw->vgt_num_indices;
1482 pm4[6] = draw->vgt_draw_initiator;
1483 }
1484 ctx->pm4_cdwords += ndwords;
1485
1486 ctx->flags |= (R600_CONTEXT_DST_CACHES_DIRTY | R600_CONTEXT_DRAW_PENDING);
1487
1488 /* all dirty state have been scheduled in current cs */
1489 ctx->pm4_dirty_cdwords = 0;
1490 }
1491
1492 void r600_context_flush(struct r600_context *ctx)
1493 {
1494 struct drm_radeon_cs drmib = {};
1495 struct drm_radeon_cs_chunk chunks[2];
1496 uint64_t chunk_array[2];
1497 unsigned fence;
1498 int r;
1499 struct r600_block *enable_block = NULL;
1500
1501 if (ctx->pm4_cdwords == ctx->init_dwords)
1502 return;
1503
1504 /* suspend queries */
1505 r600_context_queries_suspend(ctx);
1506
1507 if (ctx->radeon->chip_class >= EVERGREEN)
1508 evergreen_context_flush_dest_caches(ctx);
1509 else
1510 r600_context_flush_dest_caches(ctx);
1511
1512 /* partial flush is needed to avoid lockups on some chips with user fences */
1513 ctx->pm4[ctx->pm4_cdwords++] = PKT3(PKT3_EVENT_WRITE, 0, 0);
1514 ctx->pm4[ctx->pm4_cdwords++] = EVENT_TYPE(EVENT_TYPE_PS_PARTIAL_FLUSH) | EVENT_INDEX(4);
1515 /* emit fence */
1516 ctx->pm4[ctx->pm4_cdwords++] = PKT3(PKT3_EVENT_WRITE_EOP, 4, 0);
1517 ctx->pm4[ctx->pm4_cdwords++] = EVENT_TYPE(EVENT_TYPE_CACHE_FLUSH_AND_INV_TS_EVENT) | EVENT_INDEX(5);
1518 ctx->pm4[ctx->pm4_cdwords++] = 0;
1519 ctx->pm4[ctx->pm4_cdwords++] = (1 << 29) | (0 << 24);
1520 ctx->pm4[ctx->pm4_cdwords++] = ctx->radeon->fence;
1521 ctx->pm4[ctx->pm4_cdwords++] = 0;
1522 ctx->pm4[ctx->pm4_cdwords++] = PKT3(PKT3_NOP, 0, 0);
1523 ctx->pm4[ctx->pm4_cdwords++] = 0;
1524 r600_context_bo_reloc(ctx, &ctx->pm4[ctx->pm4_cdwords - 1], ctx->radeon->fence_bo);
1525
1526 #if 1
1527 /* emit cs */
1528 drmib.num_chunks = 2;
1529 drmib.chunks = (uint64_t)(uintptr_t)chunk_array;
1530 chunks[0].chunk_id = RADEON_CHUNK_ID_IB;
1531 chunks[0].length_dw = ctx->pm4_cdwords;
1532 chunks[0].chunk_data = (uint64_t)(uintptr_t)ctx->pm4;
1533 chunks[1].chunk_id = RADEON_CHUNK_ID_RELOCS;
1534 chunks[1].length_dw = ctx->creloc * sizeof(struct r600_reloc) / 4;
1535 chunks[1].chunk_data = (uint64_t)(uintptr_t)ctx->reloc;
1536 chunk_array[0] = (uint64_t)(uintptr_t)&chunks[0];
1537 chunk_array[1] = (uint64_t)(uintptr_t)&chunks[1];
1538 r = drmCommandWriteRead(ctx->radeon->fd, DRM_RADEON_CS, &drmib,
1539 sizeof(struct drm_radeon_cs));
1540 #else
1541 *ctx->radeon->cfence = ctx->radeon->fence;
1542 #endif
1543
1544 r600_context_update_fenced_list(ctx);
1545
1546 fence = ctx->radeon->fence + 1;
1547 if (fence < ctx->radeon->fence) {
1548 /* wrap around */
1549 fence = 1;
1550 r600_context_fence_wraparound(ctx, fence);
1551 }
1552 ctx->radeon->fence = fence;
1553
1554 /* restart */
1555 for (int i = 0; i < ctx->creloc; i++) {
1556 ctx->bo[i]->reloc = NULL;
1557 ctx->bo[i]->last_flush = 0;
1558 radeon_bo_reference(ctx->radeon, &ctx->bo[i], NULL);
1559 }
1560 ctx->creloc = 0;
1561 ctx->pm4_dirty_cdwords = 0;
1562 ctx->pm4_cdwords = 0;
1563 ctx->flags = 0;
1564
1565 r600_init_cs(ctx);
1566
1567 /* resume queries */
1568 r600_context_queries_resume(ctx, TRUE);
1569
1570 /* set all valid group as dirty so they get reemited on
1571 * next draw command
1572 */
1573 LIST_FOR_EACH_ENTRY(enable_block, &ctx->enable_list, enable_list) {
1574 if (!(enable_block->flags & BLOCK_FLAG_RESOURCE)) {
1575 if(!(enable_block->status & R600_BLOCK_STATUS_DIRTY)) {
1576 LIST_ADDTAIL(&enable_block->list,&ctx->dirty);
1577 enable_block->status |= R600_BLOCK_STATUS_DIRTY;
1578 }
1579 } else {
1580 if(!(enable_block->status & R600_BLOCK_STATUS_RESOURCE_DIRTY)) {
1581 LIST_ADDTAIL(&enable_block->list,&ctx->resource_dirty);
1582 enable_block->status |= R600_BLOCK_STATUS_RESOURCE_DIRTY;
1583 }
1584 }
1585 ctx->pm4_dirty_cdwords += enable_block->pm4_ndwords +
1586 enable_block->pm4_flush_ndwords;
1587 enable_block->nreg_dirty = enable_block->nreg;
1588 }
1589 }
1590
1591 void r600_context_emit_fence(struct r600_context *ctx, struct r600_bo *fence_bo, unsigned offset, unsigned value)
1592 {
1593 unsigned ndwords = 10;
1594
1595 if (((ctx->pm4_dirty_cdwords + ndwords + ctx->pm4_cdwords) > ctx->pm4_ndwords) ||
1596 (ctx->creloc >= (ctx->nreloc - 1))) {
1597 /* need to flush */
1598 r600_context_flush(ctx);
1599 }
1600
1601 ctx->pm4[ctx->pm4_cdwords++] = PKT3(PKT3_EVENT_WRITE, 0, 0);
1602 ctx->pm4[ctx->pm4_cdwords++] = EVENT_TYPE(EVENT_TYPE_PS_PARTIAL_FLUSH) | EVENT_INDEX(4);
1603 ctx->pm4[ctx->pm4_cdwords++] = PKT3(PKT3_EVENT_WRITE_EOP, 4, 0);
1604 ctx->pm4[ctx->pm4_cdwords++] = EVENT_TYPE(EVENT_TYPE_CACHE_FLUSH_AND_INV_TS_EVENT) | EVENT_INDEX(5);
1605 ctx->pm4[ctx->pm4_cdwords++] = offset << 2; /* ADDRESS_LO */
1606 ctx->pm4[ctx->pm4_cdwords++] = (1 << 29) | (0 << 24); /* DATA_SEL | INT_EN | ADDRESS_HI */
1607 ctx->pm4[ctx->pm4_cdwords++] = value; /* DATA_LO */
1608 ctx->pm4[ctx->pm4_cdwords++] = 0; /* DATA_HI */
1609 ctx->pm4[ctx->pm4_cdwords++] = PKT3(PKT3_NOP, 0, 0);
1610 ctx->pm4[ctx->pm4_cdwords++] = 0;
1611 r600_context_bo_reloc(ctx, &ctx->pm4[ctx->pm4_cdwords - 1], fence_bo);
1612 }
1613
1614 void r600_context_dump_bof(struct r600_context *ctx, const char *file)
1615 {
1616 bof_t *bcs, *blob, *array, *bo, *size, *handle, *device_id, *root;
1617 unsigned i;
1618
1619 root = device_id = bcs = blob = array = bo = size = handle = NULL;
1620 root = bof_object();
1621 if (root == NULL)
1622 goto out_err;
1623 device_id = bof_int32(ctx->radeon->device);
1624 if (device_id == NULL)
1625 goto out_err;
1626 if (bof_object_set(root, "device_id", device_id))
1627 goto out_err;
1628 bof_decref(device_id);
1629 device_id = NULL;
1630 /* dump relocs */
1631 blob = bof_blob(ctx->creloc * 16, ctx->reloc);
1632 if (blob == NULL)
1633 goto out_err;
1634 if (bof_object_set(root, "reloc", blob))
1635 goto out_err;
1636 bof_decref(blob);
1637 blob = NULL;
1638 /* dump cs */
1639 blob = bof_blob(ctx->pm4_cdwords * 4, ctx->pm4);
1640 if (blob == NULL)
1641 goto out_err;
1642 if (bof_object_set(root, "pm4", blob))
1643 goto out_err;
1644 bof_decref(blob);
1645 blob = NULL;
1646 /* dump bo */
1647 array = bof_array();
1648 if (array == NULL)
1649 goto out_err;
1650 for (i = 0; i < ctx->creloc; i++) {
1651 struct radeon_bo *rbo = ctx->bo[i];
1652 bo = bof_object();
1653 if (bo == NULL)
1654 goto out_err;
1655 size = bof_int32(rbo->size);
1656 if (size == NULL)
1657 goto out_err;
1658 if (bof_object_set(bo, "size", size))
1659 goto out_err;
1660 bof_decref(size);
1661 size = NULL;
1662 handle = bof_int32(rbo->handle);
1663 if (handle == NULL)
1664 goto out_err;
1665 if (bof_object_set(bo, "handle", handle))
1666 goto out_err;
1667 bof_decref(handle);
1668 handle = NULL;
1669 radeon_bo_map(ctx->radeon, rbo);
1670 blob = bof_blob(rbo->size, rbo->data);
1671 radeon_bo_unmap(ctx->radeon, rbo);
1672 if (blob == NULL)
1673 goto out_err;
1674 if (bof_object_set(bo, "data", blob))
1675 goto out_err;
1676 bof_decref(blob);
1677 blob = NULL;
1678 if (bof_array_append(array, bo))
1679 goto out_err;
1680 bof_decref(bo);
1681 bo = NULL;
1682 }
1683 if (bof_object_set(root, "bo", array))
1684 goto out_err;
1685 bof_dump_file(root, file);
1686 out_err:
1687 bof_decref(blob);
1688 bof_decref(array);
1689 bof_decref(bo);
1690 bof_decref(size);
1691 bof_decref(handle);
1692 bof_decref(device_id);
1693 bof_decref(root);
1694 }
1695
1696 static boolean r600_query_result(struct r600_context *ctx, struct r600_query *query, boolean wait)
1697 {
1698 u64 start, end;
1699 u32 *results;
1700 int i;
1701 int size;
1702
1703 if (wait)
1704 results = r600_bo_map(ctx->radeon, query->buffer, PB_USAGE_CPU_READ, NULL);
1705 else
1706 results = r600_bo_map(ctx->radeon, query->buffer, PB_USAGE_DONTBLOCK | PB_USAGE_CPU_READ, NULL);
1707 if (!results)
1708 return FALSE;
1709
1710 /* query->num_results contains how many dwords were used for the query */
1711 size = query->num_results;
1712 for (i = 0; i < size; i += 4) {
1713 start = (u64)results[i] | (u64)results[i + 1] << 32;
1714 end = (u64)results[i + 2] | (u64)results[i + 3] << 32;
1715 if (((start & 0x8000000000000000UL) && (end & 0x8000000000000000UL))
1716 || query->type == PIPE_QUERY_TIME_ELAPSED) {
1717 query->result += end - start;
1718 }
1719 }
1720 r600_bo_unmap(ctx->radeon, query->buffer);
1721 query->num_results = 0;
1722
1723 return TRUE;
1724 }
1725
1726 void r600_query_begin(struct r600_context *ctx, struct r600_query *query)
1727 {
1728 unsigned required_space, required_buffer;
1729 int num_backends = r600_get_num_backends(ctx->radeon);
1730
1731 /* query request needs 6/8 dwords for begin + 6/8 dwords for end */
1732 if (query->type == PIPE_QUERY_TIME_ELAPSED)
1733 required_space = 16;
1734 else
1735 required_space = 12;
1736
1737 if ((required_space + ctx->pm4_cdwords) > ctx->pm4_ndwords) {
1738 /* need to flush */
1739 r600_context_flush(ctx);
1740 }
1741
1742 required_buffer = query->num_results +
1743 4 * (query->type == PIPE_QUERY_OCCLUSION_COUNTER ? ctx->max_db : 1);
1744
1745 /* if query buffer is full force a flush */
1746 if (required_buffer*4 > query->buffer_size) {
1747 if (!(query->state & R600_QUERY_STATE_FLUSHED))
1748 r600_context_flush(ctx);
1749 r600_query_result(ctx, query, TRUE);
1750 }
1751
1752 if (query->type == PIPE_QUERY_OCCLUSION_COUNTER &&
1753 num_backends > 0) {
1754 /* as per info on ZPASS the driver must set the unusued DB top bits */
1755 u32 *results;
1756 int i;
1757
1758 results = r600_bo_map(ctx->radeon, query->buffer, PB_USAGE_CPU_WRITE, NULL);
1759 if (results) {
1760 memset(results + query->num_results, 0, ctx->max_db * 4 * 4);
1761
1762 for (i = num_backends; i < ctx->max_db; i++) {
1763 results[(i * 4)+1] = 0x80000000;
1764 results[(i * 4)+3] = 0x80000000;
1765 }
1766 r600_bo_unmap(ctx->radeon, query->buffer);
1767 }
1768 }
1769
1770 /* emit begin query */
1771 if (query->type == PIPE_QUERY_TIME_ELAPSED) {
1772 ctx->pm4[ctx->pm4_cdwords++] = PKT3(PKT3_EVENT_WRITE_EOP, 4, 0);
1773 ctx->pm4[ctx->pm4_cdwords++] = EVENT_TYPE(EVENT_TYPE_CACHE_FLUSH_AND_INV_TS_EVENT) | EVENT_INDEX(5);
1774 ctx->pm4[ctx->pm4_cdwords++] = query->num_results*4 + r600_bo_offset(query->buffer);
1775 ctx->pm4[ctx->pm4_cdwords++] = (3 << 29);
1776 ctx->pm4[ctx->pm4_cdwords++] = 0;
1777 ctx->pm4[ctx->pm4_cdwords++] = 0;
1778 } else {
1779 ctx->pm4[ctx->pm4_cdwords++] = PKT3(PKT3_EVENT_WRITE, 2, 0);
1780 ctx->pm4[ctx->pm4_cdwords++] = EVENT_TYPE(EVENT_TYPE_ZPASS_DONE) | EVENT_INDEX(1);
1781 ctx->pm4[ctx->pm4_cdwords++] = query->num_results*4 + r600_bo_offset(query->buffer);
1782 ctx->pm4[ctx->pm4_cdwords++] = 0;
1783 }
1784 ctx->pm4[ctx->pm4_cdwords++] = PKT3(PKT3_NOP, 0, 0);
1785 ctx->pm4[ctx->pm4_cdwords++] = 0;
1786 r600_context_bo_reloc(ctx, &ctx->pm4[ctx->pm4_cdwords - 1], query->buffer);
1787
1788 query->state |= R600_QUERY_STATE_STARTED;
1789 query->state ^= R600_QUERY_STATE_ENDED;
1790 ctx->num_query_running++;
1791 }
1792
1793 void r600_query_end(struct r600_context *ctx, struct r600_query *query)
1794 {
1795 /* emit begin query */
1796 if (query->type == PIPE_QUERY_TIME_ELAPSED) {
1797 ctx->pm4[ctx->pm4_cdwords++] = PKT3(PKT3_EVENT_WRITE_EOP, 4, 0);
1798 ctx->pm4[ctx->pm4_cdwords++] = EVENT_TYPE(EVENT_TYPE_CACHE_FLUSH_AND_INV_TS_EVENT) | EVENT_INDEX(5);
1799 ctx->pm4[ctx->pm4_cdwords++] = query->num_results*4 + 8 + r600_bo_offset(query->buffer);
1800 ctx->pm4[ctx->pm4_cdwords++] = (3 << 29);
1801 ctx->pm4[ctx->pm4_cdwords++] = 0;
1802 ctx->pm4[ctx->pm4_cdwords++] = 0;
1803 } else {
1804 ctx->pm4[ctx->pm4_cdwords++] = PKT3(PKT3_EVENT_WRITE, 2, 0);
1805 ctx->pm4[ctx->pm4_cdwords++] = EVENT_TYPE(EVENT_TYPE_ZPASS_DONE) | EVENT_INDEX(1);
1806 ctx->pm4[ctx->pm4_cdwords++] = query->num_results*4 + 8 + r600_bo_offset(query->buffer);
1807 ctx->pm4[ctx->pm4_cdwords++] = 0;
1808 }
1809 ctx->pm4[ctx->pm4_cdwords++] = PKT3(PKT3_NOP, 0, 0);
1810 ctx->pm4[ctx->pm4_cdwords++] = 0;
1811 r600_context_bo_reloc(ctx, &ctx->pm4[ctx->pm4_cdwords - 1], query->buffer);
1812
1813 query->num_results += 4 * (query->type == PIPE_QUERY_OCCLUSION_COUNTER ? ctx->max_db : 1);
1814 query->state ^= R600_QUERY_STATE_STARTED;
1815 query->state |= R600_QUERY_STATE_ENDED;
1816 query->state &= ~R600_QUERY_STATE_FLUSHED;
1817 ctx->num_query_running--;
1818 }
1819
1820 void r600_query_predication(struct r600_context *ctx, struct r600_query *query, int operation,
1821 int flag_wait)
1822 {
1823 ctx->pm4[ctx->pm4_cdwords++] = PKT3(PKT3_SET_PREDICATION, 1, 0);
1824
1825 if (operation == PREDICATION_OP_CLEAR) {
1826 ctx->pm4[ctx->pm4_cdwords++] = 0;
1827 ctx->pm4[ctx->pm4_cdwords++] = PRED_OP(PREDICATION_OP_CLEAR);
1828 } else {
1829 int results_base = query->num_results - (4 * ctx->max_db);
1830
1831 if (results_base < 0)
1832 results_base = 0;
1833
1834 ctx->pm4[ctx->pm4_cdwords++] = results_base*4 + r600_bo_offset(query->buffer);
1835 ctx->pm4[ctx->pm4_cdwords++] = PRED_OP(operation) | (flag_wait ? PREDICATION_HINT_WAIT : PREDICATION_HINT_NOWAIT_DRAW) | PREDICATION_DRAW_VISIBLE;
1836 ctx->pm4[ctx->pm4_cdwords++] = PKT3(PKT3_NOP, 0, 0);
1837 ctx->pm4[ctx->pm4_cdwords++] = 0;
1838 r600_context_bo_reloc(ctx, &ctx->pm4[ctx->pm4_cdwords - 1], query->buffer);
1839 }
1840 }
1841
1842 struct r600_query *r600_context_query_create(struct r600_context *ctx, unsigned query_type)
1843 {
1844 struct r600_query *query;
1845
1846 if (query_type != PIPE_QUERY_OCCLUSION_COUNTER && query_type != PIPE_QUERY_TIME_ELAPSED)
1847 return NULL;
1848
1849 query = calloc(1, sizeof(struct r600_query));
1850 if (query == NULL)
1851 return NULL;
1852
1853 query->type = query_type;
1854 query->buffer_size = 4096;
1855
1856 /* As of GL4, query buffers are normally read by the CPU after
1857 * being written by the gpu, hence staging is probably a good
1858 * usage pattern.
1859 */
1860 query->buffer = r600_bo(ctx->radeon, query->buffer_size, 1, 0,
1861 PIPE_USAGE_STAGING);
1862 if (!query->buffer) {
1863 free(query);
1864 return NULL;
1865 }
1866
1867 LIST_ADDTAIL(&query->list, &ctx->query_list);
1868
1869 return query;
1870 }
1871
1872 void r600_context_query_destroy(struct r600_context *ctx, struct r600_query *query)
1873 {
1874 r600_bo_reference(ctx->radeon, &query->buffer, NULL);
1875 LIST_DELINIT(&query->list);
1876 free(query);
1877 }
1878
1879 boolean r600_context_query_result(struct r600_context *ctx,
1880 struct r600_query *query,
1881 boolean wait, void *vresult)
1882 {
1883 uint64_t *result = (uint64_t*)vresult;
1884
1885 if (query->num_results && !(query->state & R600_QUERY_STATE_FLUSHED)) {
1886 r600_context_flush(ctx);
1887 }
1888 if (!r600_query_result(ctx, query, wait))
1889 return FALSE;
1890 if (query->type == PIPE_QUERY_TIME_ELAPSED)
1891 *result = (1000000*query->result)/r600_get_clock_crystal_freq(ctx->radeon);
1892 else
1893 *result = query->result;
1894 query->result = 0;
1895 return TRUE;
1896 }
1897
1898 void r600_context_queries_suspend(struct r600_context *ctx)
1899 {
1900 struct r600_query *query;
1901
1902 LIST_FOR_EACH_ENTRY(query, &ctx->query_list, list) {
1903 if (query->state & R600_QUERY_STATE_STARTED) {
1904 r600_query_end(ctx, query);
1905 query->state |= R600_QUERY_STATE_SUSPENDED;
1906 }
1907 }
1908 }
1909
1910 void r600_context_queries_resume(struct r600_context *ctx, boolean flushed)
1911 {
1912 struct r600_query *query;
1913
1914 LIST_FOR_EACH_ENTRY(query, &ctx->query_list, list) {
1915 if (query->state & R600_QUERY_STATE_SUSPENDED) {
1916 r600_query_begin(ctx, query);
1917 query->state ^= R600_QUERY_STATE_SUSPENDED;
1918 } else if (flushed && query->state==R600_QUERY_STATE_ENDED)
1919 query->state |= R600_QUERY_STATE_FLUSHED;
1920 }
1921 }