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r600g: Fix meaning of num_results for queries.
[mesa.git] / src / gallium / winsys / r600 / drm / r600_hw_context.c
1 /*
2 * Copyright 2010 Jerome Glisse <glisse@freedesktop.org>
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * on the rights to use, copy, modify, merge, publish, distribute, sub
8 * license, and/or sell copies of the Software, and to permit persons to whom
9 * the Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
22 *
23 * Authors:
24 * Jerome Glisse
25 */
26 #include <errno.h>
27 #include <stdint.h>
28 #include <string.h>
29 #include <stdlib.h>
30 #include <assert.h>
31 #include <pipe/p_compiler.h>
32 #include <util/u_inlines.h>
33 #include <util/u_memory.h>
34 #include <pipebuffer/pb_bufmgr.h>
35 #include "xf86drm.h"
36 #include "radeon_drm.h"
37 #include "r600_priv.h"
38 #include "bof.h"
39 #include "r600d.h"
40
41 #define GROUP_FORCE_NEW_BLOCK 0
42
43 static void INLINE r600_context_update_fenced_list(struct r600_context *ctx)
44 {
45 for (int i = 0; i < ctx->creloc; i++) {
46 if (!LIST_IS_EMPTY(&ctx->bo[i]->fencedlist))
47 LIST_DELINIT(&ctx->bo[i]->fencedlist);
48 LIST_ADDTAIL(&ctx->bo[i]->fencedlist, &ctx->fenced_bo);
49 ctx->bo[i]->fence = ctx->radeon->fence;
50 ctx->bo[i]->ctx = ctx;
51 }
52 }
53
54 static void INLINE r600_context_fence_wraparound(struct r600_context *ctx, unsigned fence)
55 {
56 struct radeon_bo *bo = NULL;
57 struct radeon_bo *tmp;
58
59 LIST_FOR_EACH_ENTRY_SAFE(bo, tmp, &ctx->fenced_bo, fencedlist) {
60 if (bo->fence <= *ctx->radeon->cfence) {
61 LIST_DELINIT(&bo->fencedlist);
62 bo->fence = 0;
63 } else {
64 bo->fence = fence;
65 }
66 }
67 }
68
69 int r600_context_add_block(struct r600_context *ctx, const struct r600_reg *reg, unsigned nreg)
70 {
71 struct r600_block *block;
72 struct r600_range *range;
73 int offset;
74
75 for (unsigned i = 0, n = 0; i < nreg; i += n) {
76 u32 j;
77
78 /* ignore new block balise */
79 if (reg[i].offset == GROUP_FORCE_NEW_BLOCK) {
80 n = 1;
81 continue;
82 }
83
84 /* register that need relocation are in their own group */
85 /* find number of consecutive registers */
86 n = 0;
87 offset = reg[i].offset;
88 while (reg[i + n].offset == offset) {
89 n++;
90 offset += 4;
91 if ((n + i) >= nreg)
92 break;
93 if (n >= (R600_BLOCK_MAX_REG - 2))
94 break;
95 }
96
97 /* allocate new block */
98 block = calloc(1, sizeof(struct r600_block));
99 if (block == NULL) {
100 return -ENOMEM;
101 }
102 ctx->nblocks++;
103 for (int j = 0; j < n; j++) {
104 range = &ctx->range[CTX_RANGE_ID(ctx, reg[i + j].offset)];
105 range->blocks[CTX_BLOCK_ID(ctx, reg[i + j].offset)] = block;
106 }
107
108 /* initialize block */
109 block->start_offset = reg[i].offset;
110 block->pm4[block->pm4_ndwords++] = PKT3(reg[i].opcode, n);
111 block->pm4[block->pm4_ndwords++] = (block->start_offset - reg[i].offset_base) >> 2;
112 block->reg = &block->pm4[block->pm4_ndwords];
113 block->pm4_ndwords += n;
114 block->nreg = n;
115 LIST_INITHEAD(&block->list);
116
117 for (j = 0; j < n; j++) {
118 if (reg[i+j].need_bo) {
119 block->nbo++;
120 assert(block->nbo < R600_BLOCK_MAX_BO);
121 block->pm4_bo_index[j] = block->nbo;
122 block->pm4[block->pm4_ndwords++] = PKT3(PKT3_NOP, 0);
123 block->pm4[block->pm4_ndwords++] = 0x00000000;
124 block->reloc[block->nbo].flush_flags = reg[i+j].flush_flags;
125 block->reloc[block->nbo].flush_mask = reg[i+j].flush_mask;
126 block->reloc[block->nbo].bo_pm4_index = block->pm4_ndwords - 1;
127 }
128 }
129 for (j = 0; j < n; j++) {
130 if (reg[i+j].flush_flags) {
131 block->pm4_flush_ndwords += 7;
132 }
133 }
134 /* check that we stay in limit */
135 assert(block->pm4_ndwords < R600_BLOCK_MAX_REG);
136 }
137 return 0;
138 }
139
140 /* R600/R700 configuration */
141 static const struct r600_reg r600_config_reg_list[] = {
142 {PKT3_SET_CONFIG_REG, R600_CONFIG_REG_OFFSET, R_008958_VGT_PRIMITIVE_TYPE, 0, 0, 0},
143 {PKT3_SET_CONFIG_REG, R600_CONFIG_REG_OFFSET, R_008C00_SQ_CONFIG, 0, 0, 0},
144 {PKT3_SET_CONFIG_REG, R600_CONFIG_REG_OFFSET, R_008C04_SQ_GPR_RESOURCE_MGMT_1, 0, 0, 0},
145 {PKT3_SET_CONFIG_REG, R600_CONFIG_REG_OFFSET, R_008C08_SQ_GPR_RESOURCE_MGMT_2, 0, 0, 0},
146 {PKT3_SET_CONFIG_REG, R600_CONFIG_REG_OFFSET, R_008C0C_SQ_THREAD_RESOURCE_MGMT, 0, 0, 0},
147 {PKT3_SET_CONFIG_REG, R600_CONFIG_REG_OFFSET, R_008C10_SQ_STACK_RESOURCE_MGMT_1, 0, 0, 0},
148 {PKT3_SET_CONFIG_REG, R600_CONFIG_REG_OFFSET, R_008C14_SQ_STACK_RESOURCE_MGMT_2, 0, 0, 0},
149 {PKT3_SET_CONFIG_REG, R600_CONFIG_REG_OFFSET, R_008D8C_SQ_DYN_GPR_CNTL_PS_FLUSH_REQ, 0, 0, 0},
150 {PKT3_SET_CONFIG_REG, R600_CONFIG_REG_OFFSET, R_009508_TA_CNTL_AUX, 0, 0, 0},
151 {PKT3_SET_CONFIG_REG, R600_CONFIG_REG_OFFSET, R_009714_VC_ENHANCE, 0, 0, 0},
152 {PKT3_SET_CONFIG_REG, R600_CONFIG_REG_OFFSET, R_009830_DB_DEBUG, 0, 0, 0},
153 {PKT3_SET_CONFIG_REG, R600_CONFIG_REG_OFFSET, R_009838_DB_WATERMARKS, 0, 0, 0},
154 };
155
156 static const struct r600_reg r600_ctl_const_list[] = {
157 {PKT3_SET_CTL_CONST, R600_CTL_CONST_OFFSET, R_03CFF0_SQ_VTX_BASE_VTX_LOC, 0, 0, 0},
158 {PKT3_SET_CTL_CONST, R600_CTL_CONST_OFFSET, R_03CFF4_SQ_VTX_START_INST_LOC, 0, 0, 0},
159 };
160
161 static const struct r600_reg r600_context_reg_list[] = {
162 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028350_SX_MISC, 0, 0, 0},
163 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_0286C8_SPI_THREAD_GROUPING, 0, 0, 0},
164 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_0288A8_SQ_ESGS_RING_ITEMSIZE, 0, 0, 0},
165 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_0288AC_SQ_GSVS_RING_ITEMSIZE, 0, 0, 0},
166 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_0288B0_SQ_ESTMP_RING_ITEMSIZE, 0, 0, 0},
167 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_0288B4_SQ_GSTMP_RING_ITEMSIZE, 0, 0, 0},
168 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_0288B8_SQ_VSTMP_RING_ITEMSIZE, 0, 0, 0},
169 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_0288BC_SQ_PSTMP_RING_ITEMSIZE, 0, 0, 0},
170 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_0288C0_SQ_FBUF_RING_ITEMSIZE, 0, 0, 0},
171 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_0288C4_SQ_REDUC_RING_ITEMSIZE, 0, 0, 0},
172 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_0288C8_SQ_GS_VERT_ITEMSIZE, 0, 0, 0},
173 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028A10_VGT_OUTPUT_PATH_CNTL, 0, 0, 0},
174 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028A14_VGT_HOS_CNTL, 0, 0, 0},
175 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028A18_VGT_HOS_MAX_TESS_LEVEL, 0, 0, 0},
176 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028A1C_VGT_HOS_MIN_TESS_LEVEL, 0, 0, 0},
177 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028A20_VGT_HOS_REUSE_DEPTH, 0, 0, 0},
178 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028A24_VGT_GROUP_PRIM_TYPE, 0, 0, 0},
179 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028A28_VGT_GROUP_FIRST_DECR, 0, 0, 0},
180 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028A2C_VGT_GROUP_DECR, 0, 0, 0},
181 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028A30_VGT_GROUP_VECT_0_CNTL, 0, 0, 0},
182 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028A34_VGT_GROUP_VECT_1_CNTL, 0, 0, 0},
183 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028A38_VGT_GROUP_VECT_0_FMT_CNTL, 0, 0, 0},
184 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028A3C_VGT_GROUP_VECT_1_FMT_CNTL, 0, 0, 0},
185 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028A40_VGT_GS_MODE, 0, 0, 0},
186 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028A4C_PA_SC_MODE_CNTL, 0, 0, 0},
187 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028AB0_VGT_STRMOUT_EN, 0, 0, 0},
188 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028AB4_VGT_REUSE_OFF, 0, 0, 0},
189 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028AB8_VGT_VTX_CNT_EN, 0, 0, 0},
190 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028B20_VGT_STRMOUT_BUFFER_EN, 0, 0, 0},
191 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028028_DB_STENCIL_CLEAR, 0, 0, 0},
192 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_02802C_DB_DEPTH_CLEAR, 0, 0, 0},
193 {0, 0, GROUP_FORCE_NEW_BLOCK, 0, 0, 0},
194 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028040_CB_COLOR0_BASE, 1, 0, 0},
195 {0, 0, GROUP_FORCE_NEW_BLOCK, 0, 0, 0},
196 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_0280A0_CB_COLOR0_INFO, 1, 0, 0xFFFFFFFF},
197 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028060_CB_COLOR0_SIZE, 0, 0, 0},
198 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028080_CB_COLOR0_VIEW, 0, 0, 0},
199 {0, 0, GROUP_FORCE_NEW_BLOCK, 0, 0, 0},
200 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_0280E0_CB_COLOR0_FRAG, 1, 0, 0},
201 {0, 0, GROUP_FORCE_NEW_BLOCK, 0, 0, 0},
202 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_0280C0_CB_COLOR0_TILE, 1, 0, 0},
203 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028100_CB_COLOR0_MASK, 0, 0, 0},
204 {0, 0, GROUP_FORCE_NEW_BLOCK, 0, 0, 0},
205 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028044_CB_COLOR1_BASE, 1, 0, 0},
206 {0, 0, GROUP_FORCE_NEW_BLOCK, 0, 0, 0},
207 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_0280A4_CB_COLOR1_INFO, 1, 0, 0xFFFFFFFF},
208 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028064_CB_COLOR1_SIZE, 0, 0, 0},
209 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028084_CB_COLOR1_VIEW, 0, 0, 0},
210 {0, 0, GROUP_FORCE_NEW_BLOCK, 0, 0, 0},
211 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_0280E4_CB_COLOR1_FRAG, 1, 0, 0},
212 {0, 0, GROUP_FORCE_NEW_BLOCK, 0, 0, 0},
213 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_0280C4_CB_COLOR1_TILE, 1, 0, 0},
214 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028104_CB_COLOR1_MASK, 0, 0, 0},
215 {0, 0, GROUP_FORCE_NEW_BLOCK, 0, 0, 0},
216 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028048_CB_COLOR2_BASE, 1, 0, 0},
217 {0, 0, GROUP_FORCE_NEW_BLOCK, 0, 0, 0},
218 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_0280A8_CB_COLOR2_INFO, 1, 0, 0xFFFFFFFF},
219 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028068_CB_COLOR2_SIZE, 0, 0, 0},
220 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028088_CB_COLOR2_VIEW, 0, 0, 0},
221 {0, 0, GROUP_FORCE_NEW_BLOCK, 0, 0, 0},
222 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_0280E8_CB_COLOR2_FRAG, 1, 0, 0},
223 {0, 0, GROUP_FORCE_NEW_BLOCK, 0, 0, 0},
224 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_0280C8_CB_COLOR2_TILE, 1, 0, 0},
225 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028108_CB_COLOR2_MASK, 0, 0, 0},
226 {0, 0, GROUP_FORCE_NEW_BLOCK, 0, 0, 0},
227 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_02804C_CB_COLOR3_BASE, 1, 0, 0},
228 {0, 0, GROUP_FORCE_NEW_BLOCK, 0, 0, 0},
229 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_0280AC_CB_COLOR3_INFO, 1, 0, 0xFFFFFFFF},
230 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_02806C_CB_COLOR3_SIZE, 0, 0, 0},
231 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_02808C_CB_COLOR3_VIEW, 0, 0, 0},
232 {0, 0, GROUP_FORCE_NEW_BLOCK, 0, 0, 0},
233 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_0280EC_CB_COLOR3_FRAG, 1, 0, 0},
234 {0, 0, GROUP_FORCE_NEW_BLOCK, 0, 0, 0},
235 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_0280CC_CB_COLOR3_TILE, 1, 0, 0},
236 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_02810C_CB_COLOR3_MASK, 0, 0, 0},
237 {0, 0, GROUP_FORCE_NEW_BLOCK, 0, 0, 0},
238 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028050_CB_COLOR4_BASE, 1, 0, 0},
239 {0, 0, GROUP_FORCE_NEW_BLOCK, 0, 0, 0},
240 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_0280B0_CB_COLOR4_INFO, 1, 0, 0xFFFFFFFF},
241 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028070_CB_COLOR4_SIZE, 0, 0, 0},
242 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028090_CB_COLOR4_VIEW, 0, 0, 0},
243 {0, 0, GROUP_FORCE_NEW_BLOCK, 0, 0, 0},
244 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_0280F0_CB_COLOR4_FRAG, 1, 0, 0},
245 {0, 0, GROUP_FORCE_NEW_BLOCK, 0, 0, 0},
246 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_0280D0_CB_COLOR4_TILE, 1, 0, 0},
247 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028110_CB_COLOR4_MASK, 0, 0, 0},
248 {0, 0, GROUP_FORCE_NEW_BLOCK, 0, 0, 0},
249 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028054_CB_COLOR5_BASE, 1, 0, 0},
250 {0, 0, GROUP_FORCE_NEW_BLOCK, 0, 0, 0},
251 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_0280B4_CB_COLOR5_INFO, 1, 0, 0xFFFFFFFF},
252 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028074_CB_COLOR5_SIZE, 0, 0, 0},
253 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028094_CB_COLOR5_VIEW, 0, 0, 0},
254 {0, 0, GROUP_FORCE_NEW_BLOCK, 0, 0, 0},
255 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_0280F4_CB_COLOR5_FRAG, 1, 0, 0},
256 {0, 0, GROUP_FORCE_NEW_BLOCK, 0, 0, 0},
257 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_0280D4_CB_COLOR5_TILE, 1, 0, 0},
258 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028114_CB_COLOR5_MASK, 0, 0, 0},
259 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028058_CB_COLOR6_BASE, 1, 0, 0},
260 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_0280B8_CB_COLOR6_INFO, 1, 0, 0xFFFFFFFF},
261 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028078_CB_COLOR6_SIZE, 0, 0, 0},
262 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028098_CB_COLOR6_VIEW, 0, 0, 0},
263 {0, 0, GROUP_FORCE_NEW_BLOCK, 0, 0, 0},
264 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_0280F8_CB_COLOR6_FRAG, 1, 0, 0},
265 {0, 0, GROUP_FORCE_NEW_BLOCK, 0, 0, 0},
266 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_0280D8_CB_COLOR6_TILE, 1, 0, 0},
267 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028118_CB_COLOR6_MASK, 0, 0, 0},
268 {0, 0, GROUP_FORCE_NEW_BLOCK, 0, 0, 0},
269 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_02805C_CB_COLOR7_BASE, 1, 0, 0},
270 {0, 0, GROUP_FORCE_NEW_BLOCK, 0, 0, 0},
271 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_0280BC_CB_COLOR7_INFO, 1, 0, 0xFFFFFFFF},
272 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_02807C_CB_COLOR7_SIZE, 0, 0, 0},
273 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_02809C_CB_COLOR7_VIEW, 0, 0, 0},
274 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_0280FC_CB_COLOR7_FRAG, 1, 0, 0},
275 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_0280DC_CB_COLOR7_TILE, 1, 0, 0},
276 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_02811C_CB_COLOR7_MASK, 0, 0, 0},
277 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028120_CB_CLEAR_RED, 0, 0, 0},
278 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028124_CB_CLEAR_GREEN, 0, 0, 0},
279 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028128_CB_CLEAR_BLUE, 0, 0, 0},
280 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_02812C_CB_CLEAR_ALPHA, 0, 0, 0},
281 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028140_ALU_CONST_BUFFER_SIZE_PS_0, 0, 0, 0},
282 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028180_ALU_CONST_BUFFER_SIZE_VS_0, 0, 0, 0},
283 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028940_ALU_CONST_CACHE_PS_0, 1, S_0085F0_SH_ACTION_ENA(1), 0xFFFFFFFF},
284 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028980_ALU_CONST_CACHE_VS_0, 1, S_0085F0_SH_ACTION_ENA(1), 0xFFFFFFFF},
285 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_02823C_CB_SHADER_MASK, 0, 0, 0},
286 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028238_CB_TARGET_MASK, 0, 0, 0},
287 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028410_SX_ALPHA_TEST_CONTROL, 0, 0, 0},
288 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028414_CB_BLEND_RED, 0, 0, 0},
289 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028418_CB_BLEND_GREEN, 0, 0, 0},
290 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_02841C_CB_BLEND_BLUE, 0, 0, 0},
291 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028420_CB_BLEND_ALPHA, 0, 0, 0},
292 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028424_CB_FOG_RED, 0, 0, 0},
293 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028428_CB_FOG_GREEN, 0, 0, 0},
294 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_02842C_CB_FOG_BLUE, 0, 0, 0},
295 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028430_DB_STENCILREFMASK, 0, 0, 0},
296 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028434_DB_STENCILREFMASK_BF, 0, 0, 0},
297 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028438_SX_ALPHA_REF, 0, 0, 0},
298 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_0286DC_SPI_FOG_CNTL, 0, 0, 0},
299 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_0286E0_SPI_FOG_FUNC_SCALE, 0, 0, 0},
300 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_0286E4_SPI_FOG_FUNC_BIAS, 0, 0, 0},
301 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028780_CB_BLEND0_CONTROL, 0, 0, 0},
302 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028784_CB_BLEND1_CONTROL, 0, 0, 0},
303 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028788_CB_BLEND2_CONTROL, 0, 0, 0},
304 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_02878C_CB_BLEND3_CONTROL, 0, 0, 0},
305 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028790_CB_BLEND4_CONTROL, 0, 0, 0},
306 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028794_CB_BLEND5_CONTROL, 0, 0, 0},
307 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028798_CB_BLEND6_CONTROL, 0, 0, 0},
308 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_02879C_CB_BLEND7_CONTROL, 0, 0, 0},
309 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_0287A0_CB_SHADER_CONTROL, 0, 0, 0},
310 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028800_DB_DEPTH_CONTROL, 0, 0, 0},
311 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028804_CB_BLEND_CONTROL, 0, 0, 0},
312 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028808_CB_COLOR_CONTROL, 0, 0, 0},
313 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_02880C_DB_SHADER_CONTROL, 0, 0, 0},
314 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028C04_PA_SC_AA_CONFIG, 0, 0, 0},
315 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028C1C_PA_SC_AA_SAMPLE_LOCS_MCTX, 0, 0, 0},
316 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028C20_PA_SC_AA_SAMPLE_LOCS_8S_WD1_MCTX, 0, 0, 0},
317 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028C30_CB_CLRCMP_CONTROL, 0, 0, 0},
318 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028C34_CB_CLRCMP_SRC, 0, 0, 0},
319 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028C38_CB_CLRCMP_DST, 0, 0, 0},
320 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028C3C_CB_CLRCMP_MSK, 0, 0, 0},
321 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028C48_PA_SC_AA_MASK, 0, 0, 0},
322 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028D2C_DB_SRESULTS_COMPARE_STATE1, 0, 0, 0},
323 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028D44_DB_ALPHA_TO_MASK, 0, 0, 0},
324 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_02800C_DB_DEPTH_BASE, 1, 0, 0},
325 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028000_DB_DEPTH_SIZE, 0, 0, 0},
326 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028004_DB_DEPTH_VIEW, 0, 0, 0},
327 {0, 0, GROUP_FORCE_NEW_BLOCK, 0, 0, 0},
328 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028010_DB_DEPTH_INFO, 1, 0, 0},
329 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028D0C_DB_RENDER_CONTROL, 0, 0, 0},
330 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028D10_DB_RENDER_OVERRIDE, 0, 0, 0},
331 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028D24_DB_HTILE_SURFACE, 0, 0, 0},
332 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028D30_DB_PRELOAD_CONTROL, 0, 0, 0},
333 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028D34_DB_PREFETCH_LIMIT, 0, 0, 0},
334 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028030_PA_SC_SCREEN_SCISSOR_TL, 0, 0, 0},
335 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028034_PA_SC_SCREEN_SCISSOR_BR, 0, 0, 0},
336 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028200_PA_SC_WINDOW_OFFSET, 0, 0, 0},
337 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028204_PA_SC_WINDOW_SCISSOR_TL, 0, 0, 0},
338 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028208_PA_SC_WINDOW_SCISSOR_BR, 0, 0, 0},
339 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_02820C_PA_SC_CLIPRECT_RULE, 0, 0, 0},
340 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028210_PA_SC_CLIPRECT_0_TL, 0, 0, 0},
341 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028214_PA_SC_CLIPRECT_0_BR, 0, 0, 0},
342 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028218_PA_SC_CLIPRECT_1_TL, 0, 0, 0},
343 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_02821C_PA_SC_CLIPRECT_1_BR, 0, 0, 0},
344 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028220_PA_SC_CLIPRECT_2_TL, 0, 0, 0},
345 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028224_PA_SC_CLIPRECT_2_BR, 0, 0, 0},
346 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028228_PA_SC_CLIPRECT_3_TL, 0, 0, 0},
347 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_02822C_PA_SC_CLIPRECT_3_BR, 0, 0, 0},
348 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028230_PA_SC_EDGERULE, 0, 0, 0},
349 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028240_PA_SC_GENERIC_SCISSOR_TL, 0, 0, 0},
350 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028244_PA_SC_GENERIC_SCISSOR_BR, 0, 0, 0},
351 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028250_PA_SC_VPORT_SCISSOR_0_TL, 0, 0, 0},
352 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028254_PA_SC_VPORT_SCISSOR_0_BR, 0, 0, 0},
353 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_0282D0_PA_SC_VPORT_ZMIN_0, 0, 0, 0},
354 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_0282D4_PA_SC_VPORT_ZMAX_0, 0, 0, 0},
355 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_02843C_PA_CL_VPORT_XSCALE_0, 0, 0, 0},
356 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028440_PA_CL_VPORT_XOFFSET_0, 0, 0, 0},
357 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028444_PA_CL_VPORT_YSCALE_0, 0, 0, 0},
358 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028448_PA_CL_VPORT_YOFFSET_0, 0, 0, 0},
359 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_02844C_PA_CL_VPORT_ZSCALE_0, 0, 0, 0},
360 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028450_PA_CL_VPORT_ZOFFSET_0, 0, 0, 0},
361 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_0286D4_SPI_INTERP_CONTROL_0, 0, 0, 0},
362 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028810_PA_CL_CLIP_CNTL, 0, 0, 0},
363 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028814_PA_SU_SC_MODE_CNTL, 0, 0, 0},
364 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028818_PA_CL_VTE_CNTL, 0, 0, 0},
365 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_02881C_PA_CL_VS_OUT_CNTL, 0, 0, 0},
366 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028820_PA_CL_NANINF_CNTL, 0, 0, 0},
367 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028A00_PA_SU_POINT_SIZE, 0, 0, 0},
368 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028A04_PA_SU_POINT_MINMAX, 0, 0, 0},
369 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028A08_PA_SU_LINE_CNTL, 0, 0, 0},
370 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028A0C_PA_SC_LINE_STIPPLE, 0, 0, 0},
371 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028A48_PA_SC_MPASS_PS_CNTL, 0, 0, 0},
372 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028C00_PA_SC_LINE_CNTL, 0, 0, 0},
373 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028C08_PA_SU_VTX_CNTL, 0, 0, 0},
374 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028C0C_PA_CL_GB_VERT_CLIP_ADJ, 0, 0, 0},
375 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028C10_PA_CL_GB_VERT_DISC_ADJ, 0, 0, 0},
376 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028C14_PA_CL_GB_HORZ_CLIP_ADJ, 0, 0, 0},
377 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028C18_PA_CL_GB_HORZ_DISC_ADJ, 0, 0, 0},
378 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028DF8_PA_SU_POLY_OFFSET_DB_FMT_CNTL, 0, 0, 0},
379 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028DFC_PA_SU_POLY_OFFSET_CLAMP, 0, 0, 0},
380 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028E00_PA_SU_POLY_OFFSET_FRONT_SCALE, 0, 0, 0},
381 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028E04_PA_SU_POLY_OFFSET_FRONT_OFFSET, 0, 0, 0},
382 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028E08_PA_SU_POLY_OFFSET_BACK_SCALE, 0, 0, 0},
383 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028E0C_PA_SU_POLY_OFFSET_BACK_OFFSET, 0, 0, 0},
384 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028E20_PA_CL_UCP0_X, 0, 0, 0},
385 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028E24_PA_CL_UCP0_Y, 0, 0, 0},
386 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028E28_PA_CL_UCP0_Z, 0, 0, 0},
387 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028E2C_PA_CL_UCP0_W, 0, 0, 0},
388 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028E30_PA_CL_UCP1_X, 0, 0, 0},
389 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028E34_PA_CL_UCP1_Y, 0, 0, 0},
390 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028E38_PA_CL_UCP1_Z, 0, 0, 0},
391 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028E3C_PA_CL_UCP1_W, 0, 0, 0},
392 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028E40_PA_CL_UCP2_X, 0, 0, 0},
393 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028E44_PA_CL_UCP2_Y, 0, 0, 0},
394 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028E48_PA_CL_UCP2_Z, 0, 0, 0},
395 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028E4C_PA_CL_UCP2_W, 0, 0, 0},
396 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028E50_PA_CL_UCP3_X, 0, 0, 0},
397 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028E54_PA_CL_UCP3_Y, 0, 0, 0},
398 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028E58_PA_CL_UCP3_Z, 0, 0, 0},
399 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028E5C_PA_CL_UCP3_W, 0, 0, 0},
400 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028E60_PA_CL_UCP4_X, 0, 0, 0},
401 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028E64_PA_CL_UCP4_Y, 0, 0, 0},
402 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028E68_PA_CL_UCP4_Z, 0, 0, 0},
403 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028E6C_PA_CL_UCP4_W, 0, 0, 0},
404 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028E70_PA_CL_UCP5_X, 0, 0, 0},
405 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028E74_PA_CL_UCP5_Y, 0, 0, 0},
406 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028E78_PA_CL_UCP5_Z, 0, 0, 0},
407 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028E7C_PA_CL_UCP5_W, 0, 0, 0},
408 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028380_SQ_VTX_SEMANTIC_0, 0, 0, 0},
409 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028384_SQ_VTX_SEMANTIC_1, 0, 0, 0},
410 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028388_SQ_VTX_SEMANTIC_2, 0, 0, 0},
411 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_02838C_SQ_VTX_SEMANTIC_3, 0, 0, 0},
412 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028390_SQ_VTX_SEMANTIC_4, 0, 0, 0},
413 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028394_SQ_VTX_SEMANTIC_5, 0, 0, 0},
414 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028398_SQ_VTX_SEMANTIC_6, 0, 0, 0},
415 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_02839C_SQ_VTX_SEMANTIC_7, 0, 0, 0},
416 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_0283A0_SQ_VTX_SEMANTIC_8, 0, 0, 0},
417 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_0283A4_SQ_VTX_SEMANTIC_9, 0, 0, 0},
418 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_0283A8_SQ_VTX_SEMANTIC_10, 0, 0, 0},
419 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_0283AC_SQ_VTX_SEMANTIC_11, 0, 0, 0},
420 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_0283B0_SQ_VTX_SEMANTIC_12, 0, 0, 0},
421 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_0283B4_SQ_VTX_SEMANTIC_13, 0, 0, 0},
422 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_0283B8_SQ_VTX_SEMANTIC_14, 0, 0, 0},
423 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_0283BC_SQ_VTX_SEMANTIC_15, 0, 0, 0},
424 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_0283C0_SQ_VTX_SEMANTIC_16, 0, 0, 0},
425 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_0283C4_SQ_VTX_SEMANTIC_17, 0, 0, 0},
426 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_0283C8_SQ_VTX_SEMANTIC_18, 0, 0, 0},
427 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_0283CC_SQ_VTX_SEMANTIC_19, 0, 0, 0},
428 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_0283D0_SQ_VTX_SEMANTIC_20, 0, 0, 0},
429 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_0283D4_SQ_VTX_SEMANTIC_21, 0, 0, 0},
430 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_0283D8_SQ_VTX_SEMANTIC_22, 0, 0, 0},
431 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_0283DC_SQ_VTX_SEMANTIC_23, 0, 0, 0},
432 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_0283E0_SQ_VTX_SEMANTIC_24, 0, 0, 0},
433 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_0283E4_SQ_VTX_SEMANTIC_25, 0, 0, 0},
434 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_0283E8_SQ_VTX_SEMANTIC_26, 0, 0, 0},
435 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_0283EC_SQ_VTX_SEMANTIC_27, 0, 0, 0},
436 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_0283F0_SQ_VTX_SEMANTIC_28, 0, 0, 0},
437 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_0283F4_SQ_VTX_SEMANTIC_29, 0, 0, 0},
438 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_0283F8_SQ_VTX_SEMANTIC_30, 0, 0, 0},
439 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_0283FC_SQ_VTX_SEMANTIC_31, 0, 0, 0},
440 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028614_SPI_VS_OUT_ID_0, 0, 0, 0},
441 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028618_SPI_VS_OUT_ID_1, 0, 0, 0},
442 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_02861C_SPI_VS_OUT_ID_2, 0, 0, 0},
443 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028620_SPI_VS_OUT_ID_3, 0, 0, 0},
444 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028624_SPI_VS_OUT_ID_4, 0, 0, 0},
445 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028628_SPI_VS_OUT_ID_5, 0, 0, 0},
446 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_02862C_SPI_VS_OUT_ID_6, 0, 0, 0},
447 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028630_SPI_VS_OUT_ID_7, 0, 0, 0},
448 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028634_SPI_VS_OUT_ID_8, 0, 0, 0},
449 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028638_SPI_VS_OUT_ID_9, 0, 0, 0},
450 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_0286C4_SPI_VS_OUT_CONFIG, 0, 0, 0},
451 {0, 0, GROUP_FORCE_NEW_BLOCK, 0, 0, 0},
452 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028858_SQ_PGM_START_VS, 1, S_0085F0_SH_ACTION_ENA(1), 0xFFFFFFFF},
453 {0, 0, GROUP_FORCE_NEW_BLOCK, 0, 0, 0},
454 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028868_SQ_PGM_RESOURCES_VS, 0, 0, 0},
455 {0, 0, GROUP_FORCE_NEW_BLOCK, 0, 0, 0},
456 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028894_SQ_PGM_START_FS, 1, S_0085F0_SH_ACTION_ENA(1), 0xFFFFFFFF},
457 {0, 0, GROUP_FORCE_NEW_BLOCK, 0, 0, 0},
458 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_0288A4_SQ_PGM_RESOURCES_FS, 0, 0, 0},
459 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_0288D0_SQ_PGM_CF_OFFSET_VS, 0, 0, 0},
460 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_0288DC_SQ_PGM_CF_OFFSET_FS, 0, 0, 0},
461 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028644_SPI_PS_INPUT_CNTL_0, 0, 0, 0},
462 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028648_SPI_PS_INPUT_CNTL_1, 0, 0, 0},
463 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_02864C_SPI_PS_INPUT_CNTL_2, 0, 0, 0},
464 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028650_SPI_PS_INPUT_CNTL_3, 0, 0, 0},
465 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028654_SPI_PS_INPUT_CNTL_4, 0, 0, 0},
466 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028658_SPI_PS_INPUT_CNTL_5, 0, 0, 0},
467 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_02865C_SPI_PS_INPUT_CNTL_6, 0, 0, 0},
468 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028660_SPI_PS_INPUT_CNTL_7, 0, 0, 0},
469 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028664_SPI_PS_INPUT_CNTL_8, 0, 0, 0},
470 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028668_SPI_PS_INPUT_CNTL_9, 0, 0, 0},
471 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_02866C_SPI_PS_INPUT_CNTL_10, 0, 0, 0},
472 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028670_SPI_PS_INPUT_CNTL_11, 0, 0, 0},
473 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028674_SPI_PS_INPUT_CNTL_12, 0, 0, 0},
474 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028678_SPI_PS_INPUT_CNTL_13, 0, 0, 0},
475 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_02867C_SPI_PS_INPUT_CNTL_14, 0, 0, 0},
476 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028680_SPI_PS_INPUT_CNTL_15, 0, 0, 0},
477 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028684_SPI_PS_INPUT_CNTL_16, 0, 0, 0},
478 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028688_SPI_PS_INPUT_CNTL_17, 0, 0, 0},
479 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_02868C_SPI_PS_INPUT_CNTL_18, 0, 0, 0},
480 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028690_SPI_PS_INPUT_CNTL_19, 0, 0, 0},
481 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028694_SPI_PS_INPUT_CNTL_20, 0, 0, 0},
482 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028698_SPI_PS_INPUT_CNTL_21, 0, 0, 0},
483 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_02869C_SPI_PS_INPUT_CNTL_22, 0, 0, 0},
484 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_0286A0_SPI_PS_INPUT_CNTL_23, 0, 0, 0},
485 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_0286A4_SPI_PS_INPUT_CNTL_24, 0, 0, 0},
486 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_0286A8_SPI_PS_INPUT_CNTL_25, 0, 0, 0},
487 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_0286AC_SPI_PS_INPUT_CNTL_26, 0, 0, 0},
488 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_0286B0_SPI_PS_INPUT_CNTL_27, 0, 0, 0},
489 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_0286B4_SPI_PS_INPUT_CNTL_28, 0, 0, 0},
490 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_0286B8_SPI_PS_INPUT_CNTL_29, 0, 0, 0},
491 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_0286BC_SPI_PS_INPUT_CNTL_30, 0, 0, 0},
492 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_0286C0_SPI_PS_INPUT_CNTL_31, 0, 0, 0},
493 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_0286CC_SPI_PS_IN_CONTROL_0, 0, 0, 0},
494 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_0286D0_SPI_PS_IN_CONTROL_1, 0, 0, 0},
495 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_0286D8_SPI_INPUT_Z, 0, 0, 0},
496 {0, 0, GROUP_FORCE_NEW_BLOCK, 0, 0, 0},
497 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028840_SQ_PGM_START_PS, 1, S_0085F0_SH_ACTION_ENA(1), 0xFFFFFFFF},
498 {0, 0, GROUP_FORCE_NEW_BLOCK, 0, 0, 0},
499 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028850_SQ_PGM_RESOURCES_PS, 0, 0, 0},
500 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028854_SQ_PGM_EXPORTS_PS, 0, 0, 0},
501 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_0288CC_SQ_PGM_CF_OFFSET_PS, 0, 0, 0},
502 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028400_VGT_MAX_VTX_INDX, 0, 0, 0},
503 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028404_VGT_MIN_VTX_INDX, 0, 0, 0},
504 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028408_VGT_INDX_OFFSET, 0, 0, 0},
505 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_02840C_VGT_MULTI_PRIM_IB_RESET_INDX, 0, 0, 0},
506 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028A84_VGT_PRIMITIVEID_EN, 0, 0, 0},
507 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028A94_VGT_MULTI_PRIM_IB_RESET_EN, 0, 0, 0},
508 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028AA0_VGT_INSTANCE_STEP_RATE_0, 0, 0, 0},
509 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028AA4_VGT_INSTANCE_STEP_RATE_1, 0, 0, 0},
510 };
511
512 /* SHADER RESOURCE R600/R700 */
513 static int r600_state_resource_init(struct r600_context *ctx, u32 offset)
514 {
515 struct r600_reg r600_shader_resource[] = {
516 {PKT3_SET_RESOURCE, R600_RESOURCE_OFFSET, R_038000_RESOURCE0_WORD0, 0, 0, 0},
517 {PKT3_SET_RESOURCE, R600_RESOURCE_OFFSET, R_038004_RESOURCE0_WORD1, 0, 0, 0},
518 {PKT3_SET_RESOURCE, R600_RESOURCE_OFFSET, R_038008_RESOURCE0_WORD2, 1, S_0085F0_TC_ACTION_ENA(1) | S_0085F0_VC_ACTION_ENA(1), 0xFFFFFFFF},
519 {PKT3_SET_RESOURCE, R600_RESOURCE_OFFSET, R_03800C_RESOURCE0_WORD3, 1, S_0085F0_TC_ACTION_ENA(1) | S_0085F0_VC_ACTION_ENA(1), 0xFFFFFFFF},
520 {PKT3_SET_RESOURCE, R600_RESOURCE_OFFSET, R_038010_RESOURCE0_WORD4, 0, 0, 0},
521 {PKT3_SET_RESOURCE, R600_RESOURCE_OFFSET, R_038014_RESOURCE0_WORD5, 0, 0, 0},
522 {PKT3_SET_RESOURCE, R600_RESOURCE_OFFSET, R_038018_RESOURCE0_WORD6, 0, 0, 0},
523 };
524 unsigned nreg = Elements(r600_shader_resource);
525
526 for (int i = 0; i < nreg; i++) {
527 r600_shader_resource[i].offset += offset;
528 }
529 return r600_context_add_block(ctx, r600_shader_resource, nreg);
530 }
531
532 /* SHADER SAMPLER R600/R700 */
533 static int r600_state_sampler_init(struct r600_context *ctx, u32 offset)
534 {
535 struct r600_reg r600_shader_sampler[] = {
536 {PKT3_SET_SAMPLER, R600_SAMPLER_OFFSET, R_03C000_SQ_TEX_SAMPLER_WORD0_0, 0, 0, 0},
537 {PKT3_SET_SAMPLER, R600_SAMPLER_OFFSET, R_03C004_SQ_TEX_SAMPLER_WORD1_0, 0, 0, 0},
538 {PKT3_SET_SAMPLER, R600_SAMPLER_OFFSET, R_03C008_SQ_TEX_SAMPLER_WORD2_0, 0, 0, 0},
539 };
540 unsigned nreg = Elements(r600_shader_sampler);
541
542 for (int i = 0; i < nreg; i++) {
543 r600_shader_sampler[i].offset += offset;
544 }
545 return r600_context_add_block(ctx, r600_shader_sampler, nreg);
546 }
547
548 /* SHADER SAMPLER BORDER R600/R700 */
549 static int r600_state_sampler_border_init(struct r600_context *ctx, u32 offset)
550 {
551 struct r600_reg r600_shader_sampler_border[] = {
552 {PKT3_SET_CONFIG_REG, R600_CONFIG_REG_OFFSET, R_00A400_TD_PS_SAMPLER0_BORDER_RED, 0, 0, 0},
553 {PKT3_SET_CONFIG_REG, R600_CONFIG_REG_OFFSET, R_00A404_TD_PS_SAMPLER0_BORDER_GREEN, 0, 0, 0},
554 {PKT3_SET_CONFIG_REG, R600_CONFIG_REG_OFFSET, R_00A408_TD_PS_SAMPLER0_BORDER_BLUE, 0, 0, 0},
555 {PKT3_SET_CONFIG_REG, R600_CONFIG_REG_OFFSET, R_00A40C_TD_PS_SAMPLER0_BORDER_ALPHA, 0, 0, 0},
556 };
557 unsigned nreg = Elements(r600_shader_sampler_border);
558
559 for (int i = 0; i < nreg; i++) {
560 r600_shader_sampler_border[i].offset += offset;
561 }
562 return r600_context_add_block(ctx, r600_shader_sampler_border, nreg);
563 }
564
565 static int r600_loop_const_init(struct r600_context *ctx, u32 offset)
566 {
567 unsigned nreg = 32;
568 struct r600_reg r600_loop_consts[32];
569 int i;
570
571 for (i = 0; i < nreg; i++) {
572 r600_loop_consts[i].opcode = PKT3_SET_LOOP_CONST;
573 r600_loop_consts[i].offset_base = R600_LOOP_CONST_OFFSET;
574 r600_loop_consts[i].offset = R600_LOOP_CONST_OFFSET + ((offset + i) * 4);
575 r600_loop_consts[i].need_bo = 0;
576 r600_loop_consts[i].flush_flags = 0;
577 r600_loop_consts[i].flush_mask = 0;
578 }
579 return r600_context_add_block(ctx, r600_loop_consts, nreg);
580 }
581
582 static void r600_context_clear_fenced_bo(struct r600_context *ctx)
583 {
584 struct radeon_bo *bo, *tmp;
585
586 LIST_FOR_EACH_ENTRY_SAFE(bo, tmp, &ctx->fenced_bo, fencedlist) {
587 LIST_DELINIT(&bo->fencedlist);
588 bo->fence = 0;
589 bo->ctx = NULL;
590 }
591 }
592
593 /* initialize */
594 void r600_context_fini(struct r600_context *ctx)
595 {
596 struct r600_block *block;
597 struct r600_range *range;
598
599 for (int i = 0; i < 256; i++) {
600 for (int j = 0; j < (1 << ctx->hash_shift); j++) {
601 block = ctx->range[i].blocks[j];
602 if (block) {
603 for (int k = 0, offset = block->start_offset; k < block->nreg; k++, offset += 4) {
604 range = &ctx->range[CTX_RANGE_ID(ctx, offset)];
605 range->blocks[CTX_BLOCK_ID(ctx, offset)] = NULL;
606 }
607 for (int k = 1; k <= block->nbo; k++) {
608 r600_bo_reference(ctx->radeon, &block->reloc[k].bo, NULL);
609 }
610 free(block);
611 }
612 }
613 free(ctx->range[i].blocks);
614 }
615 free(ctx->blocks);
616 free(ctx->reloc);
617 free(ctx->bo);
618 free(ctx->pm4);
619
620 r600_context_clear_fenced_bo(ctx);
621 memset(ctx, 0, sizeof(struct r600_context));
622 }
623
624 int r600_context_init(struct r600_context *ctx, struct radeon *radeon)
625 {
626 int r;
627
628 memset(ctx, 0, sizeof(struct r600_context));
629 ctx->radeon = radeon;
630 LIST_INITHEAD(&ctx->query_list);
631
632 /* initialize hash */
633 ctx->hash_size = 19;
634 ctx->hash_shift = 11;
635 for (int i = 0; i < 256; i++) {
636 ctx->range[i].start_offset = i << ctx->hash_shift;
637 ctx->range[i].end_offset = ((i + 1) << ctx->hash_shift) - 1;
638 ctx->range[i].blocks = calloc(1 << ctx->hash_shift, sizeof(void*));
639 if (ctx->range[i].blocks == NULL) {
640 r = -ENOMEM;
641 goto out_err;
642 }
643 }
644
645 /* add blocks */
646 r = r600_context_add_block(ctx, r600_config_reg_list,
647 Elements(r600_config_reg_list));
648 if (r)
649 goto out_err;
650 r = r600_context_add_block(ctx, r600_context_reg_list,
651 Elements(r600_context_reg_list));
652 if (r)
653 goto out_err;
654 r = r600_context_add_block(ctx, r600_ctl_const_list,
655 Elements(r600_ctl_const_list));
656 if (r)
657 goto out_err;
658
659 /* PS SAMPLER BORDER */
660 for (int j = 0, offset = 0; j < 18; j++, offset += 0x10) {
661 r = r600_state_sampler_border_init(ctx, offset);
662 if (r)
663 goto out_err;
664 }
665
666 /* VS SAMPLER BORDER */
667 for (int j = 0, offset = 0x200; j < 18; j++, offset += 0x10) {
668 r = r600_state_sampler_border_init(ctx, offset);
669 if (r)
670 goto out_err;
671 }
672 /* PS SAMPLER */
673 for (int j = 0, offset = 0; j < 18; j++, offset += 0xC) {
674 r = r600_state_sampler_init(ctx, offset);
675 if (r)
676 goto out_err;
677 }
678 /* VS SAMPLER */
679 for (int j = 0, offset = 0xD8; j < 18; j++, offset += 0xC) {
680 r = r600_state_sampler_init(ctx, offset);
681 if (r)
682 goto out_err;
683 }
684 /* PS RESOURCE */
685 for (int j = 0, offset = 0; j < 160; j++, offset += 0x1C) {
686 r = r600_state_resource_init(ctx, offset);
687 if (r)
688 goto out_err;
689 }
690 /* VS RESOURCE */
691 for (int j = 0, offset = 0x1180; j < 160; j++, offset += 0x1C) {
692 r = r600_state_resource_init(ctx, offset);
693 if (r)
694 goto out_err;
695 }
696 /* FS RESOURCE */
697 for (int j = 0, offset = 0x2300; j < 16; j++, offset += 0x1C) {
698 r = r600_state_resource_init(ctx, offset);
699 if (r)
700 goto out_err;
701 }
702
703 /* PS loop const */
704 r600_loop_const_init(ctx, 0);
705 /* VS loop const */
706 r600_loop_const_init(ctx, 32);
707
708 /* setup block table */
709 ctx->blocks = calloc(ctx->nblocks, sizeof(void*));
710 for (int i = 0, c = 0; i < 256; i++) {
711 for (int j = 0, add; j < (1 << ctx->hash_shift); j++) {
712 if (ctx->range[i].blocks[j]) {
713 add = 1;
714 for (int k = 0; k < c; k++) {
715 if (ctx->blocks[k] == ctx->range[i].blocks[j]) {
716 add = 0;
717 break;
718 }
719 }
720 if (add) {
721 assert(c < ctx->nblocks);
722 ctx->blocks[c++] = ctx->range[i].blocks[j];
723 j += (ctx->range[i].blocks[j]->nreg << 2) - 1;
724 }
725 }
726 }
727 }
728
729 /* allocate cs variables */
730 ctx->nreloc = RADEON_CTX_MAX_PM4;
731 ctx->reloc = calloc(ctx->nreloc, sizeof(struct r600_reloc));
732 if (ctx->reloc == NULL) {
733 r = -ENOMEM;
734 goto out_err;
735 }
736 ctx->bo = calloc(ctx->nreloc, sizeof(void *));
737 if (ctx->bo == NULL) {
738 r = -ENOMEM;
739 goto out_err;
740 }
741 ctx->pm4_ndwords = RADEON_CTX_MAX_PM4;
742 ctx->pm4 = calloc(ctx->pm4_ndwords, 4);
743 if (ctx->pm4 == NULL) {
744 r = -ENOMEM;
745 goto out_err;
746 }
747 /* save 16dwords space for fence mecanism */
748 ctx->pm4_ndwords -= 16;
749
750 LIST_INITHEAD(&ctx->fenced_bo);
751
752 /* init dirty list */
753 LIST_INITHEAD(&ctx->dirty);
754 return 0;
755 out_err:
756 r600_context_fini(ctx);
757 return r;
758 }
759
760 void r600_context_bo_flush(struct r600_context *ctx, unsigned flush_flags,
761 unsigned flush_mask, struct r600_bo *rbo)
762 {
763 struct radeon_bo *bo;
764
765 bo = r600_bo_get_bo(rbo);
766 /* if bo has already been flush */
767 if (!(bo->last_flush ^ flush_flags)) {
768 bo->last_flush &= flush_mask;
769 return;
770 }
771 ctx->pm4[ctx->pm4_cdwords++] = PKT3(PKT3_SURFACE_SYNC, 3);
772 ctx->pm4[ctx->pm4_cdwords++] = flush_flags;
773 ctx->pm4[ctx->pm4_cdwords++] = (bo->size + 255) >> 8;
774 ctx->pm4[ctx->pm4_cdwords++] = 0x00000000;
775 ctx->pm4[ctx->pm4_cdwords++] = 0x0000000A;
776 ctx->pm4[ctx->pm4_cdwords++] = PKT3(PKT3_NOP, 0);
777 ctx->pm4[ctx->pm4_cdwords++] = bo->reloc_id;
778 bo->last_flush = (bo->last_flush | flush_flags) & flush_mask;
779 }
780
781 void r600_context_bo_reloc(struct r600_context *ctx, u32 *pm4, struct r600_bo *rbo)
782 {
783 struct radeon_bo *bo;
784
785 bo = r600_bo_get_bo(rbo);
786 assert(bo != NULL);
787 if (bo->reloc) {
788 *pm4 = bo->reloc_id;
789 return;
790 }
791 bo->reloc = &ctx->reloc[ctx->creloc];
792 bo->reloc_id = ctx->creloc * sizeof(struct r600_reloc) / 4;
793 ctx->reloc[ctx->creloc].handle = bo->handle;
794 ctx->reloc[ctx->creloc].read_domain = rbo->domains & (RADEON_GEM_DOMAIN_GTT | RADEON_GEM_DOMAIN_VRAM);
795 ctx->reloc[ctx->creloc].write_domain = rbo->domains & (RADEON_GEM_DOMAIN_GTT | RADEON_GEM_DOMAIN_VRAM);
796 ctx->reloc[ctx->creloc].flags = 0;
797 radeon_bo_reference(ctx->radeon, &ctx->bo[ctx->creloc], bo);
798 rbo->fence = ctx->radeon->fence;
799 ctx->creloc++;
800 /* set PKT3 to point to proper reloc */
801 *pm4 = bo->reloc_id;
802 }
803
804 void r600_context_pipe_state_set(struct r600_context *ctx, struct r600_pipe_state *state)
805 {
806 struct r600_range *range;
807 struct r600_block *block;
808
809 for (int i = 0; i < state->nregs; i++) {
810 unsigned id;
811
812 range = &ctx->range[CTX_RANGE_ID(ctx, state->regs[i].offset)];
813 block = range->blocks[CTX_BLOCK_ID(ctx, state->regs[i].offset)];
814 id = (state->regs[i].offset - block->start_offset) >> 2;
815 block->reg[id] &= ~state->regs[i].mask;
816 block->reg[id] |= state->regs[i].value;
817 if (block->pm4_bo_index[id]) {
818 /* find relocation */
819 id = block->pm4_bo_index[id];
820 r600_bo_reference(ctx->radeon, &block->reloc[id].bo, state->regs[i].bo);
821 state->regs[i].bo->fence = ctx->radeon->fence;
822 }
823 if (!(block->status & R600_BLOCK_STATUS_DIRTY)) {
824 block->status |= R600_BLOCK_STATUS_ENABLED;
825 block->status |= R600_BLOCK_STATUS_DIRTY;
826 ctx->pm4_dirty_cdwords += block->pm4_ndwords + block->pm4_flush_ndwords;
827 LIST_ADDTAIL(&block->list,&ctx->dirty);
828 }
829 }
830 }
831
832 static inline void r600_context_pipe_state_set_resource(struct r600_context *ctx, struct r600_pipe_state *state, unsigned offset)
833 {
834 struct r600_range *range;
835 struct r600_block *block;
836
837 range = &ctx->range[CTX_RANGE_ID(ctx, offset)];
838 block = range->blocks[CTX_BLOCK_ID(ctx, offset)];
839 if (state == NULL) {
840 block->status &= ~(R600_BLOCK_STATUS_ENABLED | R600_BLOCK_STATUS_DIRTY);
841 r600_bo_reference(ctx->radeon, &block->reloc[1].bo, NULL);
842 r600_bo_reference(ctx->radeon , &block->reloc[2].bo, NULL);
843 LIST_DELINIT(&block->list);
844 return;
845 }
846 block->reg[0] = state->regs[0].value;
847 block->reg[1] = state->regs[1].value;
848 block->reg[2] = state->regs[2].value;
849 block->reg[3] = state->regs[3].value;
850 block->reg[4] = state->regs[4].value;
851 block->reg[5] = state->regs[5].value;
852 block->reg[6] = state->regs[6].value;
853 r600_bo_reference(ctx->radeon, &block->reloc[1].bo, NULL);
854 r600_bo_reference(ctx->radeon , &block->reloc[2].bo, NULL);
855 if (state->regs[0].bo) {
856 /* VERTEX RESOURCE, we preted there is 2 bo to relocate so
857 * we have single case btw VERTEX & TEXTURE resource
858 */
859 r600_bo_reference(ctx->radeon, &block->reloc[1].bo, state->regs[0].bo);
860 r600_bo_reference(ctx->radeon, &block->reloc[2].bo, state->regs[0].bo);
861 state->regs[0].bo->fence = ctx->radeon->fence;
862 } else {
863 /* TEXTURE RESOURCE */
864 r600_bo_reference(ctx->radeon, &block->reloc[1].bo, state->regs[2].bo);
865 r600_bo_reference(ctx->radeon, &block->reloc[2].bo, state->regs[3].bo);
866 state->regs[2].bo->fence = ctx->radeon->fence;
867 state->regs[3].bo->fence = ctx->radeon->fence;
868 }
869 if (!(block->status & R600_BLOCK_STATUS_DIRTY)) {
870 block->status |= R600_BLOCK_STATUS_ENABLED;
871 block->status |= R600_BLOCK_STATUS_DIRTY;
872 ctx->pm4_dirty_cdwords += block->pm4_ndwords + block->pm4_flush_ndwords;
873 LIST_ADDTAIL(&block->list,&ctx->dirty);
874 }
875 }
876
877 void r600_context_pipe_state_set_ps_resource(struct r600_context *ctx, struct r600_pipe_state *state, unsigned rid)
878 {
879 unsigned offset = R_038000_SQ_TEX_RESOURCE_WORD0_0 + 0x1C * rid;
880
881 r600_context_pipe_state_set_resource(ctx, state, offset);
882 }
883
884 void r600_context_pipe_state_set_vs_resource(struct r600_context *ctx, struct r600_pipe_state *state, unsigned rid)
885 {
886 unsigned offset = R_038000_SQ_TEX_RESOURCE_WORD0_0 + 0x1180 + 0x1C * rid;
887
888 r600_context_pipe_state_set_resource(ctx, state, offset);
889 }
890
891 void r600_context_pipe_state_set_fs_resource(struct r600_context *ctx, struct r600_pipe_state *state, unsigned rid)
892 {
893 unsigned offset = R_038000_SQ_TEX_RESOURCE_WORD0_0 + 0x2300 + 0x1C * rid;
894
895 r600_context_pipe_state_set_resource(ctx, state, offset);
896 }
897
898 static inline void r600_context_pipe_state_set_sampler(struct r600_context *ctx, struct r600_pipe_state *state, unsigned offset)
899 {
900 struct r600_range *range;
901 struct r600_block *block;
902
903 range = &ctx->range[CTX_RANGE_ID(ctx, offset)];
904 block = range->blocks[CTX_BLOCK_ID(ctx, offset)];
905 if (state == NULL) {
906 block->status &= ~(R600_BLOCK_STATUS_ENABLED | R600_BLOCK_STATUS_DIRTY);
907 LIST_DELINIT(&block->list);
908 return;
909 }
910 block->reg[0] = state->regs[0].value;
911 block->reg[1] = state->regs[1].value;
912 block->reg[2] = state->regs[2].value;
913 if (!(block->status & R600_BLOCK_STATUS_DIRTY)) {
914 block->status |= R600_BLOCK_STATUS_ENABLED;
915 block->status |= R600_BLOCK_STATUS_DIRTY;
916 ctx->pm4_dirty_cdwords += block->pm4_ndwords + block->pm4_flush_ndwords;
917 LIST_ADDTAIL(&block->list,&ctx->dirty);
918 }
919 }
920
921 static inline void r600_context_pipe_state_set_sampler_border(struct r600_context *ctx, struct r600_pipe_state *state, unsigned offset)
922 {
923 struct r600_range *range;
924 struct r600_block *block;
925
926 range = &ctx->range[CTX_RANGE_ID(ctx, offset)];
927 block = range->blocks[CTX_BLOCK_ID(ctx, offset)];
928 if (state == NULL) {
929 block->status &= ~(R600_BLOCK_STATUS_ENABLED | R600_BLOCK_STATUS_DIRTY);
930 LIST_DELINIT(&block->list);
931 return;
932 }
933 if (state->nregs <= 3) {
934 return;
935 }
936 block->reg[0] = state->regs[3].value;
937 block->reg[1] = state->regs[4].value;
938 block->reg[2] = state->regs[5].value;
939 block->reg[3] = state->regs[6].value;
940 if (!(block->status & R600_BLOCK_STATUS_DIRTY)) {
941 block->status |= R600_BLOCK_STATUS_ENABLED;
942 block->status |= R600_BLOCK_STATUS_DIRTY;
943 ctx->pm4_dirty_cdwords += block->pm4_ndwords + block->pm4_flush_ndwords;
944 LIST_ADDTAIL(&block->list,&ctx->dirty);
945 }
946 }
947
948 void r600_context_pipe_state_set_ps_sampler(struct r600_context *ctx, struct r600_pipe_state *state, unsigned id)
949 {
950 unsigned offset;
951
952 offset = 0x0003C000 + id * 0xc;
953 r600_context_pipe_state_set_sampler(ctx, state, offset);
954 offset = 0x0000A400 + id * 0x10;
955 r600_context_pipe_state_set_sampler_border(ctx, state, offset);
956 }
957
958 void r600_context_pipe_state_set_vs_sampler(struct r600_context *ctx, struct r600_pipe_state *state, unsigned id)
959 {
960 unsigned offset;
961
962 offset = 0x0003C0D8 + id * 0xc;
963 r600_context_pipe_state_set_sampler(ctx, state, offset);
964 offset = 0x0000A600 + id * 0x10;
965 r600_context_pipe_state_set_sampler_border(ctx, state, offset);
966 }
967
968 struct r600_bo *r600_context_reg_bo(struct r600_context *ctx, unsigned offset)
969 {
970 struct r600_range *range;
971 struct r600_block *block;
972 unsigned id;
973
974 range = &ctx->range[CTX_RANGE_ID(ctx, offset)];
975 block = range->blocks[CTX_BLOCK_ID(ctx, offset)];
976 offset -= block->start_offset;
977 id = block->pm4_bo_index[offset >> 2];
978 if (block->reloc[id].bo) {
979 return block->reloc[id].bo;
980 }
981 return NULL;
982 }
983
984 void r600_context_draw(struct r600_context *ctx, const struct r600_draw *draw)
985 {
986 struct r600_bo *cb[8];
987 struct r600_bo *db;
988 unsigned ndwords = 9;
989 struct r600_block *dirty_block = NULL;
990 struct r600_block *next_block;
991
992 if (draw->indices) {
993 ndwords = 13;
994 /* make sure there is enough relocation space before scheduling draw */
995 if (ctx->creloc >= (ctx->nreloc - 1)) {
996 r600_context_flush(ctx);
997 }
998 }
999
1000 /* find number of color buffer */
1001 db = r600_context_reg_bo(ctx, R_02800C_DB_DEPTH_BASE);
1002 cb[0] = r600_context_reg_bo(ctx, R_028040_CB_COLOR0_BASE);
1003 cb[1] = r600_context_reg_bo(ctx, R_028044_CB_COLOR1_BASE);
1004 cb[2] = r600_context_reg_bo(ctx, R_028048_CB_COLOR2_BASE);
1005 cb[3] = r600_context_reg_bo(ctx, R_02804C_CB_COLOR3_BASE);
1006 cb[4] = r600_context_reg_bo(ctx, R_028050_CB_COLOR4_BASE);
1007 cb[5] = r600_context_reg_bo(ctx, R_028054_CB_COLOR5_BASE);
1008 cb[6] = r600_context_reg_bo(ctx, R_028058_CB_COLOR6_BASE);
1009 cb[7] = r600_context_reg_bo(ctx, R_02805C_CB_COLOR7_BASE);
1010 for (int i = 0; i < 8; i++) {
1011 if (cb[i]) {
1012 ndwords += 7;
1013 }
1014 }
1015 if (db)
1016 ndwords += 7;
1017
1018 /* queries need some special values */
1019 if (ctx->num_query_running) {
1020 if (ctx->radeon->family >= CHIP_RV770) {
1021 r600_context_reg(ctx,
1022 R_028D0C_DB_RENDER_CONTROL,
1023 S_028D0C_R700_PERFECT_ZPASS_COUNTS(1),
1024 S_028D0C_R700_PERFECT_ZPASS_COUNTS(1));
1025 }
1026 r600_context_reg(ctx,
1027 R_028D10_DB_RENDER_OVERRIDE,
1028 S_028D10_NOOP_CULL_DISABLE(1),
1029 S_028D10_NOOP_CULL_DISABLE(1));
1030 }
1031
1032 if ((ctx->pm4_dirty_cdwords + ndwords + ctx->pm4_cdwords) > ctx->pm4_ndwords) {
1033 /* need to flush */
1034 r600_context_flush(ctx);
1035 }
1036 /* at that point everythings is flushed and ctx->pm4_cdwords = 0 */
1037 if ((ctx->pm4_dirty_cdwords + ndwords) > ctx->pm4_ndwords) {
1038 R600_ERR("context is too big to be scheduled\n");
1039 return;
1040 }
1041
1042 /* enough room to copy packet */
1043 LIST_FOR_EACH_ENTRY_SAFE(dirty_block, next_block, &ctx->dirty,list) {
1044 r600_context_block_emit_dirty(ctx, dirty_block);
1045 }
1046
1047 /* draw packet */
1048 ctx->pm4[ctx->pm4_cdwords++] = PKT3(PKT3_INDEX_TYPE, 0);
1049 ctx->pm4[ctx->pm4_cdwords++] = draw->vgt_index_type;
1050 ctx->pm4[ctx->pm4_cdwords++] = PKT3(PKT3_NUM_INSTANCES, 0);
1051 ctx->pm4[ctx->pm4_cdwords++] = draw->vgt_num_instances;
1052 if (draw->indices) {
1053 ctx->pm4[ctx->pm4_cdwords++] = PKT3(PKT3_DRAW_INDEX, 3);
1054 ctx->pm4[ctx->pm4_cdwords++] = draw->indices_bo_offset + r600_bo_offset(draw->indices);
1055 ctx->pm4[ctx->pm4_cdwords++] = 0;
1056 ctx->pm4[ctx->pm4_cdwords++] = draw->vgt_num_indices;
1057 ctx->pm4[ctx->pm4_cdwords++] = draw->vgt_draw_initiator;
1058 ctx->pm4[ctx->pm4_cdwords++] = PKT3(PKT3_NOP, 0);
1059 ctx->pm4[ctx->pm4_cdwords++] = 0;
1060 r600_context_bo_reloc(ctx, &ctx->pm4[ctx->pm4_cdwords - 1], draw->indices);
1061 } else {
1062 ctx->pm4[ctx->pm4_cdwords++] = PKT3(PKT3_DRAW_INDEX_AUTO, 1);
1063 ctx->pm4[ctx->pm4_cdwords++] = draw->vgt_num_indices;
1064 ctx->pm4[ctx->pm4_cdwords++] = draw->vgt_draw_initiator;
1065 }
1066 ctx->pm4[ctx->pm4_cdwords++] = PKT3(PKT3_EVENT_WRITE, 0);
1067 ctx->pm4[ctx->pm4_cdwords++] = EVENT_TYPE(EVENT_TYPE_CACHE_FLUSH_AND_INV_EVENT) | EVENT_INDEX(0);
1068
1069 /* flush color buffer */
1070 for (int i = 0; i < 8; i++) {
1071 if (cb[i]) {
1072 r600_context_bo_flush(ctx,
1073 (S_0085F0_CB0_DEST_BASE_ENA(1) << i) |
1074 S_0085F0_CB_ACTION_ENA(1),
1075 0, cb[i]);
1076 }
1077 }
1078 if (db) {
1079 r600_context_bo_flush(ctx, S_0085F0_DB_ACTION_ENA(1), 0, db);
1080 }
1081
1082 /* all dirty state have been scheduled in current cs */
1083 ctx->pm4_dirty_cdwords = 0;
1084 }
1085
1086 void r600_context_flush(struct r600_context *ctx)
1087 {
1088 struct drm_radeon_cs drmib;
1089 struct drm_radeon_cs_chunk chunks[2];
1090 uint64_t chunk_array[2];
1091 unsigned fence;
1092 int r;
1093
1094 if (!ctx->pm4_cdwords)
1095 return;
1096
1097 /* suspend queries */
1098 r600_context_queries_suspend(ctx);
1099
1100 /* emit fence */
1101 ctx->pm4[ctx->pm4_cdwords++] = PKT3(PKT3_EVENT_WRITE, 0);
1102 ctx->pm4[ctx->pm4_cdwords++] = EVENT_TYPE(EVENT_TYPE_PS_PARTIAL_FLUSH) | EVENT_INDEX(4);
1103 ctx->pm4[ctx->pm4_cdwords++] = PKT3(PKT3_EVENT_WRITE_EOP, 4);
1104 ctx->pm4[ctx->pm4_cdwords++] = EVENT_TYPE(EVENT_TYPE_CACHE_FLUSH_AND_INV_TS_EVENT) | EVENT_INDEX(5);
1105 ctx->pm4[ctx->pm4_cdwords++] = 0;
1106 ctx->pm4[ctx->pm4_cdwords++] = (1 << 29) | (0 << 24);
1107 ctx->pm4[ctx->pm4_cdwords++] = ctx->radeon->fence;
1108 ctx->pm4[ctx->pm4_cdwords++] = 0;
1109 ctx->pm4[ctx->pm4_cdwords++] = PKT3(PKT3_NOP, 0);
1110 ctx->pm4[ctx->pm4_cdwords++] = 0;
1111 r600_context_bo_reloc(ctx, &ctx->pm4[ctx->pm4_cdwords - 1], ctx->radeon->fence_bo);
1112
1113 #if 1
1114 /* emit cs */
1115 drmib.num_chunks = 2;
1116 drmib.chunks = (uint64_t)(uintptr_t)chunk_array;
1117 chunks[0].chunk_id = RADEON_CHUNK_ID_IB;
1118 chunks[0].length_dw = ctx->pm4_cdwords;
1119 chunks[0].chunk_data = (uint64_t)(uintptr_t)ctx->pm4;
1120 chunks[1].chunk_id = RADEON_CHUNK_ID_RELOCS;
1121 chunks[1].length_dw = ctx->creloc * sizeof(struct r600_reloc) / 4;
1122 chunks[1].chunk_data = (uint64_t)(uintptr_t)ctx->reloc;
1123 chunk_array[0] = (uint64_t)(uintptr_t)&chunks[0];
1124 chunk_array[1] = (uint64_t)(uintptr_t)&chunks[1];
1125 r = drmCommandWriteRead(ctx->radeon->fd, DRM_RADEON_CS, &drmib,
1126 sizeof(struct drm_radeon_cs));
1127 #else
1128 *ctx->radeon->cfence = ctx->radeon->fence;
1129 #endif
1130
1131 r600_context_update_fenced_list(ctx);
1132
1133 fence = ctx->radeon->fence + 1;
1134 if (fence < ctx->radeon->fence) {
1135 /* wrap around */
1136 fence = 1;
1137 r600_context_fence_wraparound(ctx, fence);
1138 }
1139 ctx->radeon->fence = fence;
1140
1141 /* restart */
1142 for (int i = 0; i < ctx->creloc; i++) {
1143 ctx->bo[i]->reloc = NULL;
1144 ctx->bo[i]->last_flush = 0;
1145 radeon_bo_reference(ctx->radeon, &ctx->bo[i], NULL);
1146 }
1147 ctx->creloc = 0;
1148 ctx->pm4_dirty_cdwords = 0;
1149 ctx->pm4_cdwords = 0;
1150
1151 /* resume queries */
1152 r600_context_queries_resume(ctx);
1153
1154 /* set all valid group as dirty so they get reemited on
1155 * next draw command
1156 */
1157 for (int i = 0; i < ctx->nblocks; i++) {
1158 if (ctx->blocks[i]->status & R600_BLOCK_STATUS_ENABLED) {
1159 if(!(ctx->blocks[i]->status & R600_BLOCK_STATUS_DIRTY)) {
1160 LIST_ADDTAIL(&ctx->blocks[i]->list,&ctx->dirty);
1161 }
1162 ctx->pm4_dirty_cdwords += ctx->blocks[i]->pm4_ndwords + ctx->blocks[i]->pm4_flush_ndwords;
1163 ctx->blocks[i]->status |= R600_BLOCK_STATUS_DIRTY;
1164 }
1165 }
1166 }
1167
1168 void r600_context_dump_bof(struct r600_context *ctx, const char *file)
1169 {
1170 bof_t *bcs, *blob, *array, *bo, *size, *handle, *device_id, *root;
1171 unsigned i;
1172
1173 root = device_id = bcs = blob = array = bo = size = handle = NULL;
1174 root = bof_object();
1175 if (root == NULL)
1176 goto out_err;
1177 device_id = bof_int32(ctx->radeon->device);
1178 if (device_id == NULL)
1179 goto out_err;
1180 if (bof_object_set(root, "device_id", device_id))
1181 goto out_err;
1182 bof_decref(device_id);
1183 device_id = NULL;
1184 /* dump relocs */
1185 blob = bof_blob(ctx->creloc * 16, ctx->reloc);
1186 if (blob == NULL)
1187 goto out_err;
1188 if (bof_object_set(root, "reloc", blob))
1189 goto out_err;
1190 bof_decref(blob);
1191 blob = NULL;
1192 /* dump cs */
1193 blob = bof_blob(ctx->pm4_cdwords * 4, ctx->pm4);
1194 if (blob == NULL)
1195 goto out_err;
1196 if (bof_object_set(root, "pm4", blob))
1197 goto out_err;
1198 bof_decref(blob);
1199 blob = NULL;
1200 /* dump bo */
1201 array = bof_array();
1202 if (array == NULL)
1203 goto out_err;
1204 for (i = 0; i < ctx->creloc; i++) {
1205 struct radeon_bo *rbo = ctx->bo[i];
1206 bo = bof_object();
1207 if (bo == NULL)
1208 goto out_err;
1209 size = bof_int32(rbo->size);
1210 if (size == NULL)
1211 goto out_err;
1212 if (bof_object_set(bo, "size", size))
1213 goto out_err;
1214 bof_decref(size);
1215 size = NULL;
1216 handle = bof_int32(rbo->handle);
1217 if (handle == NULL)
1218 goto out_err;
1219 if (bof_object_set(bo, "handle", handle))
1220 goto out_err;
1221 bof_decref(handle);
1222 handle = NULL;
1223 radeon_bo_map(ctx->radeon, rbo);
1224 blob = bof_blob(rbo->size, rbo->data);
1225 radeon_bo_unmap(ctx->radeon, rbo);
1226 if (blob == NULL)
1227 goto out_err;
1228 if (bof_object_set(bo, "data", blob))
1229 goto out_err;
1230 bof_decref(blob);
1231 blob = NULL;
1232 if (bof_array_append(array, bo))
1233 goto out_err;
1234 bof_decref(bo);
1235 bo = NULL;
1236 }
1237 if (bof_object_set(root, "bo", array))
1238 goto out_err;
1239 bof_dump_file(root, file);
1240 out_err:
1241 bof_decref(blob);
1242 bof_decref(array);
1243 bof_decref(bo);
1244 bof_decref(size);
1245 bof_decref(handle);
1246 bof_decref(device_id);
1247 bof_decref(root);
1248 }
1249
1250 static void r600_query_result(struct r600_context *ctx, struct r600_query *query)
1251 {
1252 u64 start, end;
1253 u32 *results;
1254 int i;
1255
1256 results = r600_bo_map(ctx->radeon, query->buffer, 0, NULL);
1257 for (i = 0; i < query->num_results; i += 4) {
1258 start = (u64)results[i] | (u64)results[i + 1] << 32;
1259 end = (u64)results[i + 2] | (u64)results[i + 3] << 32;
1260 if ((start & 0x8000000000000000UL) && (end & 0x8000000000000000UL)) {
1261 query->result += end - start;
1262 }
1263 }
1264 r600_bo_unmap(ctx->radeon, query->buffer);
1265 query->num_results = 0;
1266 }
1267
1268 void r600_query_begin(struct r600_context *ctx, struct r600_query *query)
1269 {
1270 /* query request needs 6 dwords for begin + 6 dwords for end */
1271 if ((12 + ctx->pm4_cdwords) > ctx->pm4_ndwords) {
1272 /* need to flush */
1273 r600_context_flush(ctx);
1274 }
1275
1276 /* if query buffer is full force a flush */
1277 if (query->num_results*4 >= query->buffer_size - 16) {
1278 r600_context_flush(ctx);
1279 r600_query_result(ctx, query);
1280 }
1281
1282 /* emit begin query */
1283 ctx->pm4[ctx->pm4_cdwords++] = PKT3(PKT3_EVENT_WRITE, 2);
1284 ctx->pm4[ctx->pm4_cdwords++] = EVENT_TYPE(EVENT_TYPE_ZPASS_DONE) | EVENT_INDEX(1);
1285 ctx->pm4[ctx->pm4_cdwords++] = query->num_results*4 + r600_bo_offset(query->buffer);
1286 ctx->pm4[ctx->pm4_cdwords++] = 0;
1287 ctx->pm4[ctx->pm4_cdwords++] = PKT3(PKT3_NOP, 0);
1288 ctx->pm4[ctx->pm4_cdwords++] = 0;
1289 r600_context_bo_reloc(ctx, &ctx->pm4[ctx->pm4_cdwords - 1], query->buffer);
1290
1291 query->state |= R600_QUERY_STATE_STARTED;
1292 query->state ^= R600_QUERY_STATE_ENDED;
1293 ctx->num_query_running++;
1294 }
1295
1296 void r600_query_end(struct r600_context *ctx, struct r600_query *query)
1297 {
1298 /* emit begin query */
1299 ctx->pm4[ctx->pm4_cdwords++] = PKT3(PKT3_EVENT_WRITE, 2);
1300 ctx->pm4[ctx->pm4_cdwords++] = EVENT_TYPE(EVENT_TYPE_ZPASS_DONE) | EVENT_INDEX(1);
1301 ctx->pm4[ctx->pm4_cdwords++] = query->num_results*4 + 8 + r600_bo_offset(query->buffer);
1302 ctx->pm4[ctx->pm4_cdwords++] = 0;
1303 ctx->pm4[ctx->pm4_cdwords++] = PKT3(PKT3_NOP, 0);
1304 ctx->pm4[ctx->pm4_cdwords++] = 0;
1305 r600_context_bo_reloc(ctx, &ctx->pm4[ctx->pm4_cdwords - 1], query->buffer);
1306
1307 query->num_results += 4;
1308 query->state ^= R600_QUERY_STATE_STARTED;
1309 query->state |= R600_QUERY_STATE_ENDED;
1310 ctx->num_query_running--;
1311 }
1312
1313 struct r600_query *r600_context_query_create(struct r600_context *ctx, unsigned query_type)
1314 {
1315 struct r600_query *query;
1316
1317 if (query_type != PIPE_QUERY_OCCLUSION_COUNTER)
1318 return NULL;
1319
1320 query = calloc(1, sizeof(struct r600_query));
1321 if (query == NULL)
1322 return NULL;
1323
1324 query->type = query_type;
1325 query->buffer_size = 4096;
1326
1327 /* As of GL4, query buffers are normally read by the CPU after
1328 * being written by the gpu, hence staging is probably a good
1329 * usage pattern.
1330 */
1331 query->buffer = r600_bo(ctx->radeon, query->buffer_size, 1, 0,
1332 PIPE_USAGE_STAGING);
1333 if (!query->buffer) {
1334 free(query);
1335 return NULL;
1336 }
1337
1338 LIST_ADDTAIL(&query->list, &ctx->query_list);
1339
1340 return query;
1341 }
1342
1343 void r600_context_query_destroy(struct r600_context *ctx, struct r600_query *query)
1344 {
1345 r600_bo_reference(ctx->radeon, &query->buffer, NULL);
1346 LIST_DELINIT(&query->list);
1347 free(query);
1348 }
1349
1350 boolean r600_context_query_result(struct r600_context *ctx,
1351 struct r600_query *query,
1352 boolean wait, void *vresult)
1353 {
1354 uint64_t *result = (uint64_t*)vresult;
1355
1356 if (query->num_results) {
1357 r600_context_flush(ctx);
1358 }
1359 r600_query_result(ctx, query);
1360 *result = query->result;
1361 query->result = 0;
1362 return TRUE;
1363 }
1364
1365 void r600_context_queries_suspend(struct r600_context *ctx)
1366 {
1367 struct r600_query *query;
1368
1369 LIST_FOR_EACH_ENTRY(query, &ctx->query_list, list) {
1370 if (query->state & R600_QUERY_STATE_STARTED) {
1371 r600_query_end(ctx, query);
1372 query->state |= R600_QUERY_STATE_SUSPENDED;
1373 }
1374 }
1375 }
1376
1377 void r600_context_queries_resume(struct r600_context *ctx)
1378 {
1379 struct r600_query *query;
1380
1381 LIST_FOR_EACH_ENTRY(query, &ctx->query_list, list) {
1382 if (query->state & R600_QUERY_STATE_SUSPENDED) {
1383 r600_query_begin(ctx, query);
1384 query->state ^= R600_QUERY_STATE_SUSPENDED;
1385 }
1386 }
1387 }