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r600g: reduce r600_reg footprint
[mesa.git] / src / gallium / winsys / r600 / drm / r600_hw_context.c
1 /*
2 * Copyright 2010 Jerome Glisse <glisse@freedesktop.org>
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * on the rights to use, copy, modify, merge, publish, distribute, sub
8 * license, and/or sell copies of the Software, and to permit persons to whom
9 * the Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
22 *
23 * Authors:
24 * Jerome Glisse
25 */
26 #include <errno.h>
27 #include <stdint.h>
28 #include <string.h>
29 #include <stdlib.h>
30 #include <assert.h>
31 #include <pipe/p_compiler.h>
32 #include <util/u_inlines.h>
33 #include <util/u_memory.h>
34 #include <pipebuffer/pb_bufmgr.h>
35 #include "xf86drm.h"
36 #include "radeon_drm.h"
37 #include "r600_priv.h"
38 #include "bof.h"
39 #include "r600d.h"
40
41 #define GROUP_FORCE_NEW_BLOCK 0
42
43 static void INLINE r600_context_update_fenced_list(struct r600_context *ctx)
44 {
45 for (int i = 0; i < ctx->creloc; i++) {
46 if (!LIST_IS_EMPTY(&ctx->bo[i]->fencedlist))
47 LIST_DELINIT(&ctx->bo[i]->fencedlist);
48 LIST_ADDTAIL(&ctx->bo[i]->fencedlist, &ctx->fenced_bo);
49 ctx->bo[i]->fence = ctx->radeon->fence;
50 ctx->bo[i]->ctx = ctx;
51 }
52 }
53
54 static void INLINE r600_context_fence_wraparound(struct r600_context *ctx, unsigned fence)
55 {
56 struct radeon_bo *bo = NULL;
57 struct radeon_bo *tmp;
58
59 LIST_FOR_EACH_ENTRY_SAFE(bo, tmp, &ctx->fenced_bo, fencedlist) {
60 if (bo->fence <= *ctx->radeon->cfence) {
61 LIST_DELINIT(&bo->fencedlist);
62 bo->fence = 0;
63 } else {
64 bo->fence = fence;
65 }
66 }
67 }
68
69 int r600_context_add_block(struct r600_context *ctx, const struct r600_reg *reg, unsigned nreg,
70 unsigned opcode, unsigned offset_base)
71 {
72 struct r600_block *block;
73 struct r600_range *range;
74 int offset;
75
76 for (unsigned i = 0, n = 0; i < nreg; i += n) {
77 u32 j;
78
79 /* ignore new block balise */
80 if (reg[i].offset == GROUP_FORCE_NEW_BLOCK) {
81 n = 1;
82 continue;
83 }
84
85 /* register that need relocation are in their own group */
86 /* find number of consecutive registers */
87 n = 0;
88 offset = reg[i].offset;
89 while (reg[i + n].offset == offset) {
90 n++;
91 offset += 4;
92 if ((n + i) >= nreg)
93 break;
94 if (n >= (R600_BLOCK_MAX_REG - 2))
95 break;
96 }
97
98 /* allocate new block */
99 block = calloc(1, sizeof(struct r600_block));
100 if (block == NULL) {
101 return -ENOMEM;
102 }
103 ctx->nblocks++;
104 for (int j = 0; j < n; j++) {
105 range = &ctx->range[CTX_RANGE_ID(ctx, reg[i + j].offset)];
106 range->blocks[CTX_BLOCK_ID(ctx, reg[i + j].offset)] = block;
107 }
108
109 /* initialize block */
110 block->status |= R600_BLOCK_STATUS_DIRTY; /* dirty all blocks at start */
111 block->start_offset = reg[i].offset;
112 block->pm4[block->pm4_ndwords++] = PKT3(opcode, n, 0);
113 block->pm4[block->pm4_ndwords++] = (block->start_offset - offset_base) >> 2;
114 block->reg = &block->pm4[block->pm4_ndwords];
115 block->pm4_ndwords += n;
116 block->nreg = n;
117 block->nreg_dirty = n;
118 block->flags = 0;
119 LIST_INITHEAD(&block->list);
120
121 for (j = 0; j < n; j++) {
122 if (reg[i+j].flags & REG_FLAG_DIRTY_ALWAYS) {
123 block->flags |= REG_FLAG_DIRTY_ALWAYS;
124 }
125 if (reg[i+j].flags & REG_FLAG_NEED_BO) {
126 block->nbo++;
127 assert(block->nbo < R600_BLOCK_MAX_BO);
128 block->pm4_bo_index[j] = block->nbo;
129 block->pm4[block->pm4_ndwords++] = PKT3(PKT3_NOP, 0, 0);
130 block->pm4[block->pm4_ndwords++] = 0x00000000;
131 if (reg[i+j].flags & REG_FLAG_RV6XX_SBU) {
132 block->reloc[block->nbo].flush_flags = 0;
133 block->reloc[block->nbo].flush_mask = 0;
134 } else {
135 block->reloc[block->nbo].flush_flags = reg[i+j].flush_flags;
136 block->reloc[block->nbo].flush_mask = reg[i+j].flush_mask;
137 }
138 block->reloc[block->nbo].bo_pm4_index = block->pm4_ndwords - 1;
139 }
140 if ((ctx->radeon->family > CHIP_R600) &&
141 (ctx->radeon->family < CHIP_RV770) && reg[i+j].flags & REG_FLAG_RV6XX_SBU) {
142 block->pm4[block->pm4_ndwords++] = PKT3(PKT3_SURFACE_BASE_UPDATE, 0, 0);
143 block->pm4[block->pm4_ndwords++] = reg[i+j].flush_flags;
144 }
145 }
146 for (j = 0; j < n; j++) {
147 if (reg[i+j].flush_flags) {
148 block->pm4_flush_ndwords += 7;
149 }
150 }
151 /* check that we stay in limit */
152 assert(block->pm4_ndwords < R600_BLOCK_MAX_REG);
153 }
154 return 0;
155 }
156
157 /* R600/R700 configuration */
158 static const struct r600_reg r600_config_reg_list[] = {
159 {R_008958_VGT_PRIMITIVE_TYPE, 0, 0, 0},
160 {R_008C00_SQ_CONFIG, 0, 0, 0},
161 {R_008C04_SQ_GPR_RESOURCE_MGMT_1, 0, 0, 0},
162 {R_008C08_SQ_GPR_RESOURCE_MGMT_2, 0, 0, 0},
163 {R_008C0C_SQ_THREAD_RESOURCE_MGMT, 0, 0, 0},
164 {R_008C10_SQ_STACK_RESOURCE_MGMT_1, 0, 0, 0},
165 {R_008C14_SQ_STACK_RESOURCE_MGMT_2, 0, 0, 0},
166 {R_008D8C_SQ_DYN_GPR_CNTL_PS_FLUSH_REQ, 0, 0, 0},
167 {R_009508_TA_CNTL_AUX, 0, 0, 0},
168 {R_009714_VC_ENHANCE, 0, 0, 0},
169 {R_009830_DB_DEBUG, 0, 0, 0},
170 {R_009838_DB_WATERMARKS, 0, 0, 0},
171 };
172
173 static const struct r600_reg r600_ctl_const_list[] = {
174 {R_03CFF0_SQ_VTX_BASE_VTX_LOC, 0, 0, 0},
175 {R_03CFF4_SQ_VTX_START_INST_LOC, 0, 0, 0},
176 };
177
178 static const struct r600_reg r600_context_reg_list[] = {
179 {R_028350_SX_MISC, 0, 0, 0},
180 {R_0286C8_SPI_THREAD_GROUPING, 0, 0, 0},
181 {R_0288A8_SQ_ESGS_RING_ITEMSIZE, 0, 0, 0},
182 {R_0288AC_SQ_GSVS_RING_ITEMSIZE, 0, 0, 0},
183 {R_0288B0_SQ_ESTMP_RING_ITEMSIZE, 0, 0, 0},
184 {R_0288B4_SQ_GSTMP_RING_ITEMSIZE, 0, 0, 0},
185 {R_0288B8_SQ_VSTMP_RING_ITEMSIZE, 0, 0, 0},
186 {R_0288BC_SQ_PSTMP_RING_ITEMSIZE, 0, 0, 0},
187 {R_0288C0_SQ_FBUF_RING_ITEMSIZE, 0, 0, 0},
188 {R_0288C4_SQ_REDUC_RING_ITEMSIZE, 0, 0, 0},
189 {R_0288C8_SQ_GS_VERT_ITEMSIZE, 0, 0, 0},
190 {R_028A10_VGT_OUTPUT_PATH_CNTL, 0, 0, 0},
191 {R_028A14_VGT_HOS_CNTL, 0, 0, 0},
192 {R_028A18_VGT_HOS_MAX_TESS_LEVEL, 0, 0, 0},
193 {R_028A1C_VGT_HOS_MIN_TESS_LEVEL, 0, 0, 0},
194 {R_028A20_VGT_HOS_REUSE_DEPTH, 0, 0, 0},
195 {R_028A24_VGT_GROUP_PRIM_TYPE, 0, 0, 0},
196 {R_028A28_VGT_GROUP_FIRST_DECR, 0, 0, 0},
197 {R_028A2C_VGT_GROUP_DECR, 0, 0, 0},
198 {R_028A30_VGT_GROUP_VECT_0_CNTL, 0, 0, 0},
199 {R_028A34_VGT_GROUP_VECT_1_CNTL, 0, 0, 0},
200 {R_028A38_VGT_GROUP_VECT_0_FMT_CNTL, 0, 0, 0},
201 {R_028A3C_VGT_GROUP_VECT_1_FMT_CNTL, 0, 0, 0},
202 {R_028A40_VGT_GS_MODE, 0, 0, 0},
203 {R_028A4C_PA_SC_MODE_CNTL, 0, 0, 0},
204 {R_028AB0_VGT_STRMOUT_EN, 0, 0, 0},
205 {R_028AB4_VGT_REUSE_OFF, 0, 0, 0},
206 {R_028AB8_VGT_VTX_CNT_EN, 0, 0, 0},
207 {R_028B20_VGT_STRMOUT_BUFFER_EN, 0, 0, 0},
208 {R_028028_DB_STENCIL_CLEAR, 0, 0, 0},
209 {R_02802C_DB_DEPTH_CLEAR, 0, 0, 0},
210 {GROUP_FORCE_NEW_BLOCK, 0, 0, 0},
211 {R_028040_CB_COLOR0_BASE, REG_FLAG_NEED_BO|REG_FLAG_RV6XX_SBU, SURFACE_BASE_UPDATE_COLOR(0), 0},
212 {GROUP_FORCE_NEW_BLOCK, 0, 0, 0},
213 {R_0280A0_CB_COLOR0_INFO, REG_FLAG_NEED_BO, 0, 0xFFFFFFFF},
214 {R_028060_CB_COLOR0_SIZE, 0, 0, 0},
215 {R_028080_CB_COLOR0_VIEW, 0, 0, 0},
216 {GROUP_FORCE_NEW_BLOCK, 0, 0, 0},
217 {R_0280E0_CB_COLOR0_FRAG, REG_FLAG_NEED_BO, 0, 0},
218 {GROUP_FORCE_NEW_BLOCK, 0, 0, 0},
219 {R_0280C0_CB_COLOR0_TILE, REG_FLAG_NEED_BO, 0, 0},
220 {R_028100_CB_COLOR0_MASK, 0, 0, 0},
221 {GROUP_FORCE_NEW_BLOCK, 0, 0, 0},
222 {R_028044_CB_COLOR1_BASE, REG_FLAG_NEED_BO|REG_FLAG_RV6XX_SBU, SURFACE_BASE_UPDATE_COLOR(1), 0},
223 {GROUP_FORCE_NEW_BLOCK, 0, 0, 0},
224 {R_0280A4_CB_COLOR1_INFO, REG_FLAG_NEED_BO, 0, 0xFFFFFFFF},
225 {R_028064_CB_COLOR1_SIZE, 0, 0, 0},
226 {R_028084_CB_COLOR1_VIEW, 0, 0, 0},
227 {GROUP_FORCE_NEW_BLOCK, 0, 0, 0},
228 {R_0280E4_CB_COLOR1_FRAG, REG_FLAG_NEED_BO, 0, 0},
229 {GROUP_FORCE_NEW_BLOCK, 0, 0, 0},
230 {R_0280C4_CB_COLOR1_TILE, REG_FLAG_NEED_BO, 0, 0},
231 {R_028104_CB_COLOR1_MASK, 0, 0, 0},
232 {GROUP_FORCE_NEW_BLOCK, 0, 0, 0},
233 {R_028048_CB_COLOR2_BASE, REG_FLAG_NEED_BO|REG_FLAG_RV6XX_SBU, SURFACE_BASE_UPDATE_COLOR(2), 0},
234 {GROUP_FORCE_NEW_BLOCK, 0, 0, 0},
235 {R_0280A8_CB_COLOR2_INFO, REG_FLAG_NEED_BO, 0, 0xFFFFFFFF},
236 {R_028068_CB_COLOR2_SIZE, 0, 0, 0},
237 {R_028088_CB_COLOR2_VIEW, 0, 0, 0},
238 {GROUP_FORCE_NEW_BLOCK, 0, 0, 0},
239 {R_0280E8_CB_COLOR2_FRAG, REG_FLAG_NEED_BO, 0, 0},
240 {GROUP_FORCE_NEW_BLOCK, 0, 0, 0},
241 {R_0280C8_CB_COLOR2_TILE, REG_FLAG_NEED_BO, 0, 0},
242 {R_028108_CB_COLOR2_MASK, 0, 0, 0},
243 {GROUP_FORCE_NEW_BLOCK, 0, 0, 0},
244 {R_02804C_CB_COLOR3_BASE, REG_FLAG_NEED_BO|REG_FLAG_RV6XX_SBU, SURFACE_BASE_UPDATE_COLOR(3), 0},
245 {GROUP_FORCE_NEW_BLOCK, 0, 0, 0},
246 {R_0280AC_CB_COLOR3_INFO, REG_FLAG_NEED_BO, 0, 0xFFFFFFFF},
247 {R_02806C_CB_COLOR3_SIZE, 0, 0, 0},
248 {R_02808C_CB_COLOR3_VIEW, 0, 0, 0},
249 {GROUP_FORCE_NEW_BLOCK, 0, 0, 0},
250 {R_0280EC_CB_COLOR3_FRAG, REG_FLAG_NEED_BO, 0, 0},
251 {GROUP_FORCE_NEW_BLOCK, 0, 0, 0},
252 {R_0280CC_CB_COLOR3_TILE, REG_FLAG_NEED_BO, 0, 0},
253 {R_02810C_CB_COLOR3_MASK, 0, 0, 0},
254 {GROUP_FORCE_NEW_BLOCK, 0, 0, 0},
255 {R_028050_CB_COLOR4_BASE, REG_FLAG_NEED_BO|REG_FLAG_RV6XX_SBU, SURFACE_BASE_UPDATE_COLOR(4), 0},
256 {GROUP_FORCE_NEW_BLOCK, 0, 0, 0},
257 {R_0280B0_CB_COLOR4_INFO, REG_FLAG_NEED_BO, 0, 0xFFFFFFFF},
258 {R_028070_CB_COLOR4_SIZE, 0, 0, 0},
259 {R_028090_CB_COLOR4_VIEW, 0, 0, 0},
260 {GROUP_FORCE_NEW_BLOCK, 0, 0, 0},
261 {R_0280F0_CB_COLOR4_FRAG, REG_FLAG_NEED_BO, 0, 0},
262 {GROUP_FORCE_NEW_BLOCK, 0, 0, 0},
263 {R_0280D0_CB_COLOR4_TILE, REG_FLAG_NEED_BO, 0, 0},
264 {R_028110_CB_COLOR4_MASK, 0, 0, 0},
265 {GROUP_FORCE_NEW_BLOCK, 0, 0, 0},
266 {R_028054_CB_COLOR5_BASE, REG_FLAG_NEED_BO|REG_FLAG_RV6XX_SBU, SURFACE_BASE_UPDATE_COLOR(5), 0},
267 {GROUP_FORCE_NEW_BLOCK, 0, 0, 0},
268 {R_0280B4_CB_COLOR5_INFO, REG_FLAG_NEED_BO, 0, 0xFFFFFFFF},
269 {R_028074_CB_COLOR5_SIZE, 0, 0, 0},
270 {R_028094_CB_COLOR5_VIEW, 0, 0, 0},
271 {GROUP_FORCE_NEW_BLOCK, 0, 0, 0},
272 {R_0280F4_CB_COLOR5_FRAG, REG_FLAG_NEED_BO, 0, 0},
273 {GROUP_FORCE_NEW_BLOCK, 0, 0, 0},
274 {R_0280D4_CB_COLOR5_TILE, REG_FLAG_NEED_BO, 0, 0},
275 {R_028114_CB_COLOR5_MASK, 0, 0, 0},
276 {R_028058_CB_COLOR6_BASE, REG_FLAG_NEED_BO|REG_FLAG_RV6XX_SBU, SURFACE_BASE_UPDATE_COLOR(6), 0},
277 {R_0280B8_CB_COLOR6_INFO, REG_FLAG_NEED_BO, 0, 0xFFFFFFFF},
278 {R_028078_CB_COLOR6_SIZE, 0, 0, 0},
279 {R_028098_CB_COLOR6_VIEW, 0, 0, 0},
280 {GROUP_FORCE_NEW_BLOCK, 0, 0, 0},
281 {R_0280F8_CB_COLOR6_FRAG, REG_FLAG_NEED_BO, 0, 0},
282 {GROUP_FORCE_NEW_BLOCK, 0, 0, 0},
283 {R_0280D8_CB_COLOR6_TILE, REG_FLAG_NEED_BO, 0, 0},
284 {R_028118_CB_COLOR6_MASK, 0, 0, 0},
285 {GROUP_FORCE_NEW_BLOCK, 0, 0, 0},
286 {R_02805C_CB_COLOR7_BASE, REG_FLAG_NEED_BO|REG_FLAG_RV6XX_SBU, SURFACE_BASE_UPDATE_COLOR(7), 0},
287 {GROUP_FORCE_NEW_BLOCK, 0, 0, 0},
288 {R_0280BC_CB_COLOR7_INFO, REG_FLAG_NEED_BO, 0, 0xFFFFFFFF},
289 {R_02807C_CB_COLOR7_SIZE, 0, 0, 0},
290 {R_02809C_CB_COLOR7_VIEW, 0, 0, 0},
291 {R_0280FC_CB_COLOR7_FRAG, REG_FLAG_NEED_BO, 0, 0},
292 {R_0280DC_CB_COLOR7_TILE, REG_FLAG_NEED_BO, 0, 0},
293 {R_02811C_CB_COLOR7_MASK, 0, 0, 0},
294 {R_028120_CB_CLEAR_RED, 0, 0, 0},
295 {R_028124_CB_CLEAR_GREEN, 0, 0, 0},
296 {R_028128_CB_CLEAR_BLUE, 0, 0, 0},
297 {R_02812C_CB_CLEAR_ALPHA, 0, 0, 0},
298 {R_028140_ALU_CONST_BUFFER_SIZE_PS_0, REG_FLAG_DIRTY_ALWAYS, 0, 0},
299 {R_028180_ALU_CONST_BUFFER_SIZE_VS_0, REG_FLAG_DIRTY_ALWAYS, 0, 0},
300 {R_028940_ALU_CONST_CACHE_PS_0, REG_FLAG_NEED_BO, S_0085F0_SH_ACTION_ENA(1), 0xFFFFFFFF},
301 {R_028980_ALU_CONST_CACHE_VS_0, REG_FLAG_NEED_BO, S_0085F0_SH_ACTION_ENA(1), 0xFFFFFFFF},
302 {R_02823C_CB_SHADER_MASK, 0, 0, 0},
303 {R_028238_CB_TARGET_MASK, 0, 0, 0},
304 {R_028410_SX_ALPHA_TEST_CONTROL, 0, 0, 0},
305 {R_028414_CB_BLEND_RED, 0, 0, 0},
306 {R_028418_CB_BLEND_GREEN, 0, 0, 0},
307 {R_02841C_CB_BLEND_BLUE, 0, 0, 0},
308 {R_028420_CB_BLEND_ALPHA, 0, 0, 0},
309 {R_028424_CB_FOG_RED, 0, 0, 0},
310 {R_028428_CB_FOG_GREEN, 0, 0, 0},
311 {R_02842C_CB_FOG_BLUE, 0, 0, 0},
312 {R_028430_DB_STENCILREFMASK, 0, 0, 0},
313 {R_028434_DB_STENCILREFMASK_BF, 0, 0, 0},
314 {R_028438_SX_ALPHA_REF, 0, 0, 0},
315 {R_0286DC_SPI_FOG_CNTL, 0, 0, 0},
316 {R_0286E0_SPI_FOG_FUNC_SCALE, 0, 0, 0},
317 {R_0286E4_SPI_FOG_FUNC_BIAS, 0, 0, 0},
318 {R_028780_CB_BLEND0_CONTROL, 0, 0, 0},
319 {R_028784_CB_BLEND1_CONTROL, 0, 0, 0},
320 {R_028788_CB_BLEND2_CONTROL, 0, 0, 0},
321 {R_02878C_CB_BLEND3_CONTROL, 0, 0, 0},
322 {R_028790_CB_BLEND4_CONTROL, 0, 0, 0},
323 {R_028794_CB_BLEND5_CONTROL, 0, 0, 0},
324 {R_028798_CB_BLEND6_CONTROL, 0, 0, 0},
325 {R_02879C_CB_BLEND7_CONTROL, 0, 0, 0},
326 {R_0287A0_CB_SHADER_CONTROL, 0, 0, 0},
327 {R_028800_DB_DEPTH_CONTROL, 0, 0, 0},
328 {R_028804_CB_BLEND_CONTROL, 0, 0, 0},
329 {R_028808_CB_COLOR_CONTROL, 0, 0, 0},
330 {R_02880C_DB_SHADER_CONTROL, 0, 0, 0},
331 {R_028C04_PA_SC_AA_CONFIG, 0, 0, 0},
332 {R_028C1C_PA_SC_AA_SAMPLE_LOCS_MCTX, 0, 0, 0},
333 {R_028C20_PA_SC_AA_SAMPLE_LOCS_8S_WD1_MCTX, 0, 0, 0},
334 {R_028C30_CB_CLRCMP_CONTROL, 0, 0, 0},
335 {R_028C34_CB_CLRCMP_SRC, 0, 0, 0},
336 {R_028C38_CB_CLRCMP_DST, 0, 0, 0},
337 {R_028C3C_CB_CLRCMP_MSK, 0, 0, 0},
338 {R_028C48_PA_SC_AA_MASK, 0, 0, 0},
339 {R_028D2C_DB_SRESULTS_COMPARE_STATE1, 0, 0, 0},
340 {R_028D44_DB_ALPHA_TO_MASK, 0, 0, 0},
341 {R_02800C_DB_DEPTH_BASE, REG_FLAG_NEED_BO|REG_FLAG_RV6XX_SBU, SURFACE_BASE_UPDATE_DEPTH, 0},
342 {R_028000_DB_DEPTH_SIZE, 0, 0, 0},
343 {R_028004_DB_DEPTH_VIEW, 0, 0, 0},
344 {GROUP_FORCE_NEW_BLOCK, 0, 0, 0},
345 {R_028010_DB_DEPTH_INFO, REG_FLAG_NEED_BO, 0, 0},
346 {R_028D0C_DB_RENDER_CONTROL, 0, 0, 0},
347 {R_028D10_DB_RENDER_OVERRIDE, 0, 0, 0},
348 {R_028D24_DB_HTILE_SURFACE, 0, 0, 0},
349 {R_028D30_DB_PRELOAD_CONTROL, 0, 0, 0},
350 {R_028D34_DB_PREFETCH_LIMIT, 0, 0, 0},
351 {R_028030_PA_SC_SCREEN_SCISSOR_TL, 0, 0, 0},
352 {R_028034_PA_SC_SCREEN_SCISSOR_BR, 0, 0, 0},
353 {R_028200_PA_SC_WINDOW_OFFSET, 0, 0, 0},
354 {R_028204_PA_SC_WINDOW_SCISSOR_TL, 0, 0, 0},
355 {R_028208_PA_SC_WINDOW_SCISSOR_BR, 0, 0, 0},
356 {R_02820C_PA_SC_CLIPRECT_RULE, 0, 0, 0},
357 {R_028210_PA_SC_CLIPRECT_0_TL, 0, 0, 0},
358 {R_028214_PA_SC_CLIPRECT_0_BR, 0, 0, 0},
359 {R_028218_PA_SC_CLIPRECT_1_TL, 0, 0, 0},
360 {R_02821C_PA_SC_CLIPRECT_1_BR, 0, 0, 0},
361 {R_028220_PA_SC_CLIPRECT_2_TL, 0, 0, 0},
362 {R_028224_PA_SC_CLIPRECT_2_BR, 0, 0, 0},
363 {R_028228_PA_SC_CLIPRECT_3_TL, 0, 0, 0},
364 {R_02822C_PA_SC_CLIPRECT_3_BR, 0, 0, 0},
365 {R_028230_PA_SC_EDGERULE, 0, 0, 0},
366 {R_028240_PA_SC_GENERIC_SCISSOR_TL, 0, 0, 0},
367 {R_028244_PA_SC_GENERIC_SCISSOR_BR, 0, 0, 0},
368 {R_028250_PA_SC_VPORT_SCISSOR_0_TL, 0, 0, 0},
369 {R_028254_PA_SC_VPORT_SCISSOR_0_BR, 0, 0, 0},
370 {R_0282D0_PA_SC_VPORT_ZMIN_0, 0, 0, 0},
371 {R_0282D4_PA_SC_VPORT_ZMAX_0, 0, 0, 0},
372 {R_02843C_PA_CL_VPORT_XSCALE_0, 0, 0, 0},
373 {R_028440_PA_CL_VPORT_XOFFSET_0, 0, 0, 0},
374 {R_028444_PA_CL_VPORT_YSCALE_0, 0, 0, 0},
375 {R_028448_PA_CL_VPORT_YOFFSET_0, 0, 0, 0},
376 {R_02844C_PA_CL_VPORT_ZSCALE_0, 0, 0, 0},
377 {R_028450_PA_CL_VPORT_ZOFFSET_0, 0, 0, 0},
378 {R_0286D4_SPI_INTERP_CONTROL_0, 0, 0, 0},
379 {R_028810_PA_CL_CLIP_CNTL, 0, 0, 0},
380 {R_028814_PA_SU_SC_MODE_CNTL, 0, 0, 0},
381 {R_028818_PA_CL_VTE_CNTL, 0, 0, 0},
382 {R_02881C_PA_CL_VS_OUT_CNTL, 0, 0, 0},
383 {R_028820_PA_CL_NANINF_CNTL, 0, 0, 0},
384 {R_028A00_PA_SU_POINT_SIZE, 0, 0, 0},
385 {R_028A04_PA_SU_POINT_MINMAX, 0, 0, 0},
386 {R_028A08_PA_SU_LINE_CNTL, 0, 0, 0},
387 {R_028A0C_PA_SC_LINE_STIPPLE, 0, 0, 0},
388 {R_028A48_PA_SC_MPASS_PS_CNTL, 0, 0, 0},
389 {R_028C00_PA_SC_LINE_CNTL, 0, 0, 0},
390 {R_028C08_PA_SU_VTX_CNTL, 0, 0, 0},
391 {R_028C0C_PA_CL_GB_VERT_CLIP_ADJ, 0, 0, 0},
392 {R_028C10_PA_CL_GB_VERT_DISC_ADJ, 0, 0, 0},
393 {R_028C14_PA_CL_GB_HORZ_CLIP_ADJ, 0, 0, 0},
394 {R_028C18_PA_CL_GB_HORZ_DISC_ADJ, 0, 0, 0},
395 {R_028DF8_PA_SU_POLY_OFFSET_DB_FMT_CNTL, 0, 0, 0},
396 {R_028DFC_PA_SU_POLY_OFFSET_CLAMP, 0, 0, 0},
397 {R_028E00_PA_SU_POLY_OFFSET_FRONT_SCALE, 0, 0, 0},
398 {R_028E04_PA_SU_POLY_OFFSET_FRONT_OFFSET, 0, 0, 0},
399 {R_028E08_PA_SU_POLY_OFFSET_BACK_SCALE, 0, 0, 0},
400 {R_028E0C_PA_SU_POLY_OFFSET_BACK_OFFSET, 0, 0, 0},
401 {R_028E20_PA_CL_UCP0_X, 0, 0, 0},
402 {R_028E24_PA_CL_UCP0_Y, 0, 0, 0},
403 {R_028E28_PA_CL_UCP0_Z, 0, 0, 0},
404 {R_028E2C_PA_CL_UCP0_W, 0, 0, 0},
405 {R_028E30_PA_CL_UCP1_X, 0, 0, 0},
406 {R_028E34_PA_CL_UCP1_Y, 0, 0, 0},
407 {R_028E38_PA_CL_UCP1_Z, 0, 0, 0},
408 {R_028E3C_PA_CL_UCP1_W, 0, 0, 0},
409 {R_028E40_PA_CL_UCP2_X, 0, 0, 0},
410 {R_028E44_PA_CL_UCP2_Y, 0, 0, 0},
411 {R_028E48_PA_CL_UCP2_Z, 0, 0, 0},
412 {R_028E4C_PA_CL_UCP2_W, 0, 0, 0},
413 {R_028E50_PA_CL_UCP3_X, 0, 0, 0},
414 {R_028E54_PA_CL_UCP3_Y, 0, 0, 0},
415 {R_028E58_PA_CL_UCP3_Z, 0, 0, 0},
416 {R_028E5C_PA_CL_UCP3_W, 0, 0, 0},
417 {R_028E60_PA_CL_UCP4_X, 0, 0, 0},
418 {R_028E64_PA_CL_UCP4_Y, 0, 0, 0},
419 {R_028E68_PA_CL_UCP4_Z, 0, 0, 0},
420 {R_028E6C_PA_CL_UCP4_W, 0, 0, 0},
421 {R_028E70_PA_CL_UCP5_X, 0, 0, 0},
422 {R_028E74_PA_CL_UCP5_Y, 0, 0, 0},
423 {R_028E78_PA_CL_UCP5_Z, 0, 0, 0},
424 {R_028E7C_PA_CL_UCP5_W, 0, 0, 0},
425 {R_028380_SQ_VTX_SEMANTIC_0, 0, 0, 0},
426 {R_028384_SQ_VTX_SEMANTIC_1, 0, 0, 0},
427 {R_028388_SQ_VTX_SEMANTIC_2, 0, 0, 0},
428 {R_02838C_SQ_VTX_SEMANTIC_3, 0, 0, 0},
429 {R_028390_SQ_VTX_SEMANTIC_4, 0, 0, 0},
430 {R_028394_SQ_VTX_SEMANTIC_5, 0, 0, 0},
431 {R_028398_SQ_VTX_SEMANTIC_6, 0, 0, 0},
432 {R_02839C_SQ_VTX_SEMANTIC_7, 0, 0, 0},
433 {R_0283A0_SQ_VTX_SEMANTIC_8, 0, 0, 0},
434 {R_0283A4_SQ_VTX_SEMANTIC_9, 0, 0, 0},
435 {R_0283A8_SQ_VTX_SEMANTIC_10, 0, 0, 0},
436 {R_0283AC_SQ_VTX_SEMANTIC_11, 0, 0, 0},
437 {R_0283B0_SQ_VTX_SEMANTIC_12, 0, 0, 0},
438 {R_0283B4_SQ_VTX_SEMANTIC_13, 0, 0, 0},
439 {R_0283B8_SQ_VTX_SEMANTIC_14, 0, 0, 0},
440 {R_0283BC_SQ_VTX_SEMANTIC_15, 0, 0, 0},
441 {R_0283C0_SQ_VTX_SEMANTIC_16, 0, 0, 0},
442 {R_0283C4_SQ_VTX_SEMANTIC_17, 0, 0, 0},
443 {R_0283C8_SQ_VTX_SEMANTIC_18, 0, 0, 0},
444 {R_0283CC_SQ_VTX_SEMANTIC_19, 0, 0, 0},
445 {R_0283D0_SQ_VTX_SEMANTIC_20, 0, 0, 0},
446 {R_0283D4_SQ_VTX_SEMANTIC_21, 0, 0, 0},
447 {R_0283D8_SQ_VTX_SEMANTIC_22, 0, 0, 0},
448 {R_0283DC_SQ_VTX_SEMANTIC_23, 0, 0, 0},
449 {R_0283E0_SQ_VTX_SEMANTIC_24, 0, 0, 0},
450 {R_0283E4_SQ_VTX_SEMANTIC_25, 0, 0, 0},
451 {R_0283E8_SQ_VTX_SEMANTIC_26, 0, 0, 0},
452 {R_0283EC_SQ_VTX_SEMANTIC_27, 0, 0, 0},
453 {R_0283F0_SQ_VTX_SEMANTIC_28, 0, 0, 0},
454 {R_0283F4_SQ_VTX_SEMANTIC_29, 0, 0, 0},
455 {R_0283F8_SQ_VTX_SEMANTIC_30, 0, 0, 0},
456 {R_0283FC_SQ_VTX_SEMANTIC_31, 0, 0, 0},
457 {R_028614_SPI_VS_OUT_ID_0, 0, 0, 0},
458 {R_028618_SPI_VS_OUT_ID_1, 0, 0, 0},
459 {R_02861C_SPI_VS_OUT_ID_2, 0, 0, 0},
460 {R_028620_SPI_VS_OUT_ID_3, 0, 0, 0},
461 {R_028624_SPI_VS_OUT_ID_4, 0, 0, 0},
462 {R_028628_SPI_VS_OUT_ID_5, 0, 0, 0},
463 {R_02862C_SPI_VS_OUT_ID_6, 0, 0, 0},
464 {R_028630_SPI_VS_OUT_ID_7, 0, 0, 0},
465 {R_028634_SPI_VS_OUT_ID_8, 0, 0, 0},
466 {R_028638_SPI_VS_OUT_ID_9, 0, 0, 0},
467 {R_0286C4_SPI_VS_OUT_CONFIG, 0, 0, 0},
468 {GROUP_FORCE_NEW_BLOCK, 0, 0, 0},
469 {R_028858_SQ_PGM_START_VS, REG_FLAG_NEED_BO, S_0085F0_SH_ACTION_ENA(1), 0xFFFFFFFF},
470 {GROUP_FORCE_NEW_BLOCK, 0, 0, 0},
471 {R_028868_SQ_PGM_RESOURCES_VS, 0, 0, 0},
472 {GROUP_FORCE_NEW_BLOCK, 0, 0, 0},
473 {R_028894_SQ_PGM_START_FS, REG_FLAG_NEED_BO, S_0085F0_SH_ACTION_ENA(1), 0xFFFFFFFF},
474 {GROUP_FORCE_NEW_BLOCK, 0, 0, 0},
475 {R_0288A4_SQ_PGM_RESOURCES_FS, 0, 0, 0},
476 {R_0288D0_SQ_PGM_CF_OFFSET_VS, 0, 0, 0},
477 {R_0288DC_SQ_PGM_CF_OFFSET_FS, 0, 0, 0},
478 {R_028644_SPI_PS_INPUT_CNTL_0, 0, 0, 0},
479 {R_028648_SPI_PS_INPUT_CNTL_1, 0, 0, 0},
480 {R_02864C_SPI_PS_INPUT_CNTL_2, 0, 0, 0},
481 {R_028650_SPI_PS_INPUT_CNTL_3, 0, 0, 0},
482 {R_028654_SPI_PS_INPUT_CNTL_4, 0, 0, 0},
483 {R_028658_SPI_PS_INPUT_CNTL_5, 0, 0, 0},
484 {R_02865C_SPI_PS_INPUT_CNTL_6, 0, 0, 0},
485 {R_028660_SPI_PS_INPUT_CNTL_7, 0, 0, 0},
486 {R_028664_SPI_PS_INPUT_CNTL_8, 0, 0, 0},
487 {R_028668_SPI_PS_INPUT_CNTL_9, 0, 0, 0},
488 {R_02866C_SPI_PS_INPUT_CNTL_10, 0, 0, 0},
489 {R_028670_SPI_PS_INPUT_CNTL_11, 0, 0, 0},
490 {R_028674_SPI_PS_INPUT_CNTL_12, 0, 0, 0},
491 {R_028678_SPI_PS_INPUT_CNTL_13, 0, 0, 0},
492 {R_02867C_SPI_PS_INPUT_CNTL_14, 0, 0, 0},
493 {R_028680_SPI_PS_INPUT_CNTL_15, 0, 0, 0},
494 {R_028684_SPI_PS_INPUT_CNTL_16, 0, 0, 0},
495 {R_028688_SPI_PS_INPUT_CNTL_17, 0, 0, 0},
496 {R_02868C_SPI_PS_INPUT_CNTL_18, 0, 0, 0},
497 {R_028690_SPI_PS_INPUT_CNTL_19, 0, 0, 0},
498 {R_028694_SPI_PS_INPUT_CNTL_20, 0, 0, 0},
499 {R_028698_SPI_PS_INPUT_CNTL_21, 0, 0, 0},
500 {R_02869C_SPI_PS_INPUT_CNTL_22, 0, 0, 0},
501 {R_0286A0_SPI_PS_INPUT_CNTL_23, 0, 0, 0},
502 {R_0286A4_SPI_PS_INPUT_CNTL_24, 0, 0, 0},
503 {R_0286A8_SPI_PS_INPUT_CNTL_25, 0, 0, 0},
504 {R_0286AC_SPI_PS_INPUT_CNTL_26, 0, 0, 0},
505 {R_0286B0_SPI_PS_INPUT_CNTL_27, 0, 0, 0},
506 {R_0286B4_SPI_PS_INPUT_CNTL_28, 0, 0, 0},
507 {R_0286B8_SPI_PS_INPUT_CNTL_29, 0, 0, 0},
508 {R_0286BC_SPI_PS_INPUT_CNTL_30, 0, 0, 0},
509 {R_0286C0_SPI_PS_INPUT_CNTL_31, 0, 0, 0},
510 {R_0286CC_SPI_PS_IN_CONTROL_0, 0, 0, 0},
511 {R_0286D0_SPI_PS_IN_CONTROL_1, 0, 0, 0},
512 {R_0286D8_SPI_INPUT_Z, 0, 0, 0},
513 {GROUP_FORCE_NEW_BLOCK, 0, 0, 0},
514 {R_028840_SQ_PGM_START_PS, REG_FLAG_NEED_BO, S_0085F0_SH_ACTION_ENA(1), 0xFFFFFFFF},
515 {GROUP_FORCE_NEW_BLOCK, 0, 0, 0},
516 {R_028850_SQ_PGM_RESOURCES_PS, 0, 0, 0},
517 {R_028854_SQ_PGM_EXPORTS_PS, 0, 0, 0},
518 {R_0288CC_SQ_PGM_CF_OFFSET_PS, 0, 0, 0},
519 {R_028400_VGT_MAX_VTX_INDX, 0, 0, 0},
520 {R_028404_VGT_MIN_VTX_INDX, 0, 0, 0},
521 {R_028408_VGT_INDX_OFFSET, 0, 0, 0},
522 {R_02840C_VGT_MULTI_PRIM_IB_RESET_INDX, 0, 0, 0},
523 {R_028A84_VGT_PRIMITIVEID_EN, 0, 0, 0},
524 {R_028A94_VGT_MULTI_PRIM_IB_RESET_EN, 0, 0, 0},
525 {R_028AA0_VGT_INSTANCE_STEP_RATE_0, 0, 0, 0},
526 {R_028AA4_VGT_INSTANCE_STEP_RATE_1, 0, 0, 0},
527 };
528
529 /* SHADER RESOURCE R600/R700 */
530 static int r600_state_resource_init(struct r600_context *ctx, u32 offset)
531 {
532 struct r600_reg r600_shader_resource[] = {
533 {R_038000_RESOURCE0_WORD0, 0, 0, 0},
534 {R_038004_RESOURCE0_WORD1, 0, 0, 0},
535 {R_038008_RESOURCE0_WORD2, REG_FLAG_NEED_BO, S_0085F0_TC_ACTION_ENA(1) | S_0085F0_VC_ACTION_ENA(1), 0xFFFFFFFF},
536 {R_03800C_RESOURCE0_WORD3, REG_FLAG_NEED_BO, S_0085F0_TC_ACTION_ENA(1) | S_0085F0_VC_ACTION_ENA(1), 0xFFFFFFFF},
537 {R_038010_RESOURCE0_WORD4, 0, 0, 0},
538 {R_038014_RESOURCE0_WORD5, 0, 0, 0},
539 {R_038018_RESOURCE0_WORD6, 0, 0, 0},
540 };
541 unsigned nreg = Elements(r600_shader_resource);
542
543 for (int i = 0; i < nreg; i++) {
544 r600_shader_resource[i].offset += offset;
545 }
546 return r600_context_add_block(ctx, r600_shader_resource, nreg, PKT3_SET_RESOURCE, R600_RESOURCE_OFFSET);
547 }
548
549 /* SHADER SAMPLER R600/R700 */
550 static int r600_state_sampler_init(struct r600_context *ctx, u32 offset)
551 {
552 struct r600_reg r600_shader_sampler[] = {
553 {R_03C000_SQ_TEX_SAMPLER_WORD0_0, 0, 0, 0},
554 {R_03C004_SQ_TEX_SAMPLER_WORD1_0, 0, 0, 0},
555 {R_03C008_SQ_TEX_SAMPLER_WORD2_0, 0, 0, 0},
556 };
557 unsigned nreg = Elements(r600_shader_sampler);
558
559 for (int i = 0; i < nreg; i++) {
560 r600_shader_sampler[i].offset += offset;
561 }
562 return r600_context_add_block(ctx, r600_shader_sampler, nreg, PKT3_SET_SAMPLER, R600_SAMPLER_OFFSET);
563 }
564
565 /* SHADER SAMPLER BORDER R600/R700 */
566 static int r600_state_sampler_border_init(struct r600_context *ctx, u32 offset)
567 {
568 struct r600_reg r600_shader_sampler_border[] = {
569 {R_00A400_TD_PS_SAMPLER0_BORDER_RED, 0, 0, 0},
570 {R_00A404_TD_PS_SAMPLER0_BORDER_GREEN, 0, 0, 0},
571 {R_00A408_TD_PS_SAMPLER0_BORDER_BLUE, 0, 0, 0},
572 {R_00A40C_TD_PS_SAMPLER0_BORDER_ALPHA, 0, 0, 0},
573 };
574 unsigned nreg = Elements(r600_shader_sampler_border);
575
576 for (int i = 0; i < nreg; i++) {
577 r600_shader_sampler_border[i].offset += offset;
578 }
579 return r600_context_add_block(ctx, r600_shader_sampler_border, nreg, PKT3_SET_CONFIG_REG, R600_CONFIG_REG_OFFSET);
580 }
581
582 static int r600_loop_const_init(struct r600_context *ctx, u32 offset)
583 {
584 unsigned nreg = 32;
585 struct r600_reg r600_loop_consts[32];
586 int i;
587
588 for (i = 0; i < nreg; i++) {
589 r600_loop_consts[i].offset = R600_LOOP_CONST_OFFSET + ((offset + i) * 4);
590 r600_loop_consts[i].flags = REG_FLAG_DIRTY_ALWAYS;
591 r600_loop_consts[i].flush_flags = 0;
592 r600_loop_consts[i].flush_mask = 0;
593 }
594 return r600_context_add_block(ctx, r600_loop_consts, nreg, PKT3_SET_LOOP_CONST, R600_LOOP_CONST_OFFSET);
595 }
596
597 static void r600_context_clear_fenced_bo(struct r600_context *ctx)
598 {
599 struct radeon_bo *bo, *tmp;
600
601 LIST_FOR_EACH_ENTRY_SAFE(bo, tmp, &ctx->fenced_bo, fencedlist) {
602 LIST_DELINIT(&bo->fencedlist);
603 bo->fence = 0;
604 bo->ctx = NULL;
605 }
606 }
607
608 /* initialize */
609 void r600_context_fini(struct r600_context *ctx)
610 {
611 struct r600_block *block;
612 struct r600_range *range;
613
614 for (int i = 0; i < NUM_RANGES; i++) {
615 for (int j = 0; j < (1 << HASH_SHIFT); j++) {
616 block = ctx->range[i].blocks[j];
617 if (block) {
618 for (int k = 0, offset = block->start_offset; k < block->nreg; k++, offset += 4) {
619 range = &ctx->range[CTX_RANGE_ID(ctx, offset)];
620 range->blocks[CTX_BLOCK_ID(ctx, offset)] = NULL;
621 }
622 for (int k = 1; k <= block->nbo; k++) {
623 r600_bo_reference(ctx->radeon, &block->reloc[k].bo, NULL);
624 }
625 free(block);
626 }
627 }
628 free(ctx->range[i].blocks);
629 }
630 free(ctx->range);
631 free(ctx->blocks);
632 free(ctx->reloc);
633 free(ctx->bo);
634 free(ctx->pm4);
635
636 r600_context_clear_fenced_bo(ctx);
637 memset(ctx, 0, sizeof(struct r600_context));
638 }
639
640 int r600_context_init(struct r600_context *ctx, struct radeon *radeon)
641 {
642 int r;
643
644 memset(ctx, 0, sizeof(struct r600_context));
645 ctx->radeon = radeon;
646 LIST_INITHEAD(&ctx->query_list);
647
648 ctx->range = calloc(NUM_RANGES, sizeof(struct r600_range));
649 if (!ctx->range) {
650 r = -ENOMEM;
651 goto out_err;
652 }
653
654 /* initialize hash */
655 for (int i = 0; i < NUM_RANGES; i++) {
656 ctx->range[i].blocks = calloc(1 << HASH_SHIFT, sizeof(void*));
657 if (ctx->range[i].blocks == NULL) {
658 r = -ENOMEM;
659 goto out_err;
660 }
661 }
662
663 /* add blocks */
664 r = r600_context_add_block(ctx, r600_config_reg_list,
665 Elements(r600_config_reg_list), PKT3_SET_CONFIG_REG, R600_CONFIG_REG_OFFSET);
666 if (r)
667 goto out_err;
668 r = r600_context_add_block(ctx, r600_context_reg_list,
669 Elements(r600_context_reg_list), PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET);
670 if (r)
671 goto out_err;
672 r = r600_context_add_block(ctx, r600_ctl_const_list,
673 Elements(r600_ctl_const_list), PKT3_SET_CTL_CONST, R600_CTL_CONST_OFFSET);
674 if (r)
675 goto out_err;
676
677 /* PS SAMPLER BORDER */
678 for (int j = 0, offset = 0; j < 18; j++, offset += 0x10) {
679 r = r600_state_sampler_border_init(ctx, offset);
680 if (r)
681 goto out_err;
682 }
683
684 /* VS SAMPLER BORDER */
685 for (int j = 0, offset = 0x200; j < 18; j++, offset += 0x10) {
686 r = r600_state_sampler_border_init(ctx, offset);
687 if (r)
688 goto out_err;
689 }
690 /* PS SAMPLER */
691 for (int j = 0, offset = 0; j < 18; j++, offset += 0xC) {
692 r = r600_state_sampler_init(ctx, offset);
693 if (r)
694 goto out_err;
695 }
696 /* VS SAMPLER */
697 for (int j = 0, offset = 0xD8; j < 18; j++, offset += 0xC) {
698 r = r600_state_sampler_init(ctx, offset);
699 if (r)
700 goto out_err;
701 }
702 /* PS RESOURCE */
703 for (int j = 0, offset = 0; j < 160; j++, offset += 0x1C) {
704 r = r600_state_resource_init(ctx, offset);
705 if (r)
706 goto out_err;
707 }
708 /* VS RESOURCE */
709 for (int j = 0, offset = 0x1180; j < 160; j++, offset += 0x1C) {
710 r = r600_state_resource_init(ctx, offset);
711 if (r)
712 goto out_err;
713 }
714 /* FS RESOURCE */
715 for (int j = 0, offset = 0x2300; j < 16; j++, offset += 0x1C) {
716 r = r600_state_resource_init(ctx, offset);
717 if (r)
718 goto out_err;
719 }
720
721 /* PS loop const */
722 r600_loop_const_init(ctx, 0);
723 /* VS loop const */
724 r600_loop_const_init(ctx, 32);
725
726 /* setup block table */
727 ctx->blocks = calloc(ctx->nblocks, sizeof(void*));
728 for (int i = 0, c = 0; i < NUM_RANGES; i++) {
729 for (int j = 0, add; j < (1 << HASH_SHIFT); j++) {
730 if (ctx->range[i].blocks[j]) {
731 add = 1;
732 for (int k = 0; k < c; k++) {
733 if (ctx->blocks[k] == ctx->range[i].blocks[j]) {
734 add = 0;
735 break;
736 }
737 }
738 if (add) {
739 assert(c < ctx->nblocks);
740 ctx->blocks[c++] = ctx->range[i].blocks[j];
741 j += (ctx->range[i].blocks[j]->nreg) - 1;
742 }
743 }
744 }
745 }
746
747 /* allocate cs variables */
748 ctx->nreloc = RADEON_CTX_MAX_PM4;
749 ctx->reloc = calloc(ctx->nreloc, sizeof(struct r600_reloc));
750 if (ctx->reloc == NULL) {
751 r = -ENOMEM;
752 goto out_err;
753 }
754 ctx->bo = calloc(ctx->nreloc, sizeof(void *));
755 if (ctx->bo == NULL) {
756 r = -ENOMEM;
757 goto out_err;
758 }
759 ctx->pm4_ndwords = RADEON_CTX_MAX_PM4;
760 ctx->pm4 = calloc(ctx->pm4_ndwords, 4);
761 if (ctx->pm4 == NULL) {
762 r = -ENOMEM;
763 goto out_err;
764 }
765 /* save 16dwords space for fence mecanism */
766 ctx->pm4_ndwords -= 16;
767
768 LIST_INITHEAD(&ctx->fenced_bo);
769
770 /* init dirty list */
771 LIST_INITHEAD(&ctx->dirty);
772
773 ctx->max_db = 4;
774
775 return 0;
776 out_err:
777 r600_context_fini(ctx);
778 return r;
779 }
780
781 /* Flushes all surfaces */
782 void r600_context_flush_all(struct r600_context *ctx, unsigned flush_flags)
783 {
784 unsigned ndwords = 5;
785
786 if ((ctx->pm4_dirty_cdwords + ndwords + ctx->pm4_cdwords) > ctx->pm4_ndwords) {
787 /* need to flush */
788 r600_context_flush(ctx);
789 }
790
791 ctx->pm4[ctx->pm4_cdwords++] = PKT3(PKT3_SURFACE_SYNC, 3, ctx->predicate_drawing);
792 ctx->pm4[ctx->pm4_cdwords++] = flush_flags; /* CP_COHER_CNTL */
793 ctx->pm4[ctx->pm4_cdwords++] = 0xffffffff; /* CP_COHER_SIZE */
794 ctx->pm4[ctx->pm4_cdwords++] = 0; /* CP_COHER_BASE */
795 ctx->pm4[ctx->pm4_cdwords++] = 0x0000000A; /* POLL_INTERVAL */
796 }
797
798 void r600_context_bo_flush(struct r600_context *ctx, unsigned flush_flags,
799 unsigned flush_mask, struct r600_bo *rbo)
800 {
801 struct radeon_bo *bo;
802
803 bo = rbo->bo;
804 /* if bo has already been flushed */
805 if (!(~bo->last_flush & flush_flags)) {
806 bo->last_flush &= flush_mask;
807 return;
808 }
809
810 if ((ctx->radeon->family < CHIP_RV770) &&
811 (G_0085F0_CB_ACTION_ENA(flush_flags) ||
812 G_0085F0_DB_ACTION_ENA(flush_flags))) {
813 if (ctx->flags & R600_CONTEXT_CHECK_EVENT_FLUSH) {
814 /* the rv670 seems to fail fbo-generatemipmap unless we flush the CB1 dest base ena */
815 if ((ctx->radeon->family == CHIP_RV670) ||
816 (ctx->radeon->family == CHIP_RS780) ||
817 (ctx->radeon->family == CHIP_RS880)) {
818 ctx->pm4[ctx->pm4_cdwords++] = PKT3(PKT3_SURFACE_SYNC, 3, ctx->predicate_drawing);
819 ctx->pm4[ctx->pm4_cdwords++] = S_0085F0_CB1_DEST_BASE_ENA(1); /* CP_COHER_CNTL */
820 ctx->pm4[ctx->pm4_cdwords++] = 0xffffffff; /* CP_COHER_SIZE */
821 ctx->pm4[ctx->pm4_cdwords++] = 0; /* CP_COHER_BASE */
822 ctx->pm4[ctx->pm4_cdwords++] = 0x0000000A; /* POLL_INTERVAL */
823 }
824
825 ctx->pm4[ctx->pm4_cdwords++] = PKT3(PKT3_EVENT_WRITE, 0, ctx->predicate_drawing);
826 ctx->pm4[ctx->pm4_cdwords++] = EVENT_TYPE(EVENT_TYPE_CACHE_FLUSH_AND_INV_EVENT) | EVENT_INDEX(0);
827 ctx->flags &= ~R600_CONTEXT_CHECK_EVENT_FLUSH;
828 }
829 } else {
830 ctx->pm4[ctx->pm4_cdwords++] = PKT3(PKT3_SURFACE_SYNC, 3, ctx->predicate_drawing);
831 ctx->pm4[ctx->pm4_cdwords++] = flush_flags;
832 ctx->pm4[ctx->pm4_cdwords++] = (bo->size + 255) >> 8;
833 ctx->pm4[ctx->pm4_cdwords++] = 0x00000000;
834 ctx->pm4[ctx->pm4_cdwords++] = 0x0000000A;
835 ctx->pm4[ctx->pm4_cdwords++] = PKT3(PKT3_NOP, 0, ctx->predicate_drawing);
836 ctx->pm4[ctx->pm4_cdwords++] = bo->reloc_id;
837 }
838 bo->last_flush = (bo->last_flush | flush_flags) & flush_mask;
839 }
840
841 void r600_context_bo_reloc(struct r600_context *ctx, u32 *pm4, struct r600_bo *rbo)
842 {
843 struct radeon_bo *bo;
844
845 bo = rbo->bo;
846 assert(bo != NULL);
847 if (bo->reloc) {
848 *pm4 = bo->reloc_id;
849 return;
850 }
851 bo->reloc = &ctx->reloc[ctx->creloc];
852 bo->reloc_id = ctx->creloc * sizeof(struct r600_reloc) / 4;
853 ctx->reloc[ctx->creloc].handle = bo->handle;
854 ctx->reloc[ctx->creloc].read_domain = rbo->domains & (RADEON_GEM_DOMAIN_GTT | RADEON_GEM_DOMAIN_VRAM);
855 ctx->reloc[ctx->creloc].write_domain = rbo->domains & (RADEON_GEM_DOMAIN_GTT | RADEON_GEM_DOMAIN_VRAM);
856 ctx->reloc[ctx->creloc].flags = 0;
857 radeon_bo_reference(ctx->radeon, &ctx->bo[ctx->creloc], bo);
858 rbo->fence = ctx->radeon->fence;
859 ctx->creloc++;
860 /* set PKT3 to point to proper reloc */
861 *pm4 = bo->reloc_id;
862 }
863
864 void r600_context_reg(struct r600_context *ctx,
865 unsigned offset, unsigned value,
866 unsigned mask)
867 {
868 struct r600_range *range;
869 struct r600_block *block;
870 unsigned id;
871 unsigned new_val;
872 int dirty;
873
874 range = &ctx->range[CTX_RANGE_ID(ctx, offset)];
875 block = range->blocks[CTX_BLOCK_ID(ctx, offset)];
876 id = (offset - block->start_offset) >> 2;
877
878 dirty = block->status & R600_BLOCK_STATUS_DIRTY;
879
880 new_val = block->reg[id];
881 new_val &= ~mask;
882 new_val |= value;
883 if (new_val != block->reg[id]) {
884 dirty |= R600_BLOCK_STATUS_DIRTY;
885 block->reg[id] = new_val;
886 }
887 r600_context_dirty_block(ctx, block, dirty, id);
888 }
889
890 void r600_context_dirty_block(struct r600_context *ctx, struct r600_block *block,
891 int dirty, int index)
892 {
893 if (dirty && (index + 1) > block->nreg_dirty)
894 block->nreg_dirty = index + 1;
895
896 if ((dirty != (block->status & R600_BLOCK_STATUS_DIRTY)) || !(block->status & R600_BLOCK_STATUS_ENABLED)) {
897
898 block->status |= R600_BLOCK_STATUS_ENABLED;
899 block->status |= R600_BLOCK_STATUS_DIRTY;
900 ctx->pm4_dirty_cdwords += block->pm4_ndwords + block->pm4_flush_ndwords;
901 LIST_ADDTAIL(&block->list,&ctx->dirty);
902 }
903 }
904
905 void r600_context_pipe_state_set(struct r600_context *ctx, struct r600_pipe_state *state)
906 {
907 struct r600_range *range;
908 struct r600_block *block;
909 unsigned new_val;
910 int dirty;
911 for (int i = 0; i < state->nregs; i++) {
912 unsigned id, reloc_id;
913
914 range = &ctx->range[CTX_RANGE_ID(ctx, state->regs[i].offset)];
915 block = range->blocks[CTX_BLOCK_ID(ctx, state->regs[i].offset)];
916 id = (state->regs[i].offset - block->start_offset) >> 2;
917
918 dirty = block->status & R600_BLOCK_STATUS_DIRTY;
919
920 new_val = block->reg[id];
921 new_val &= ~state->regs[i].mask;
922 new_val |= state->regs[i].value;
923 if (new_val != block->reg[id]) {
924 block->reg[id] = new_val;
925 dirty |= R600_BLOCK_STATUS_DIRTY;
926 }
927 if (block->flags & REG_FLAG_DIRTY_ALWAYS)
928 dirty |= R600_BLOCK_STATUS_DIRTY;
929 if (block->pm4_bo_index[id]) {
930 /* find relocation */
931 reloc_id = block->pm4_bo_index[id];
932 r600_bo_reference(ctx->radeon, &block->reloc[reloc_id].bo, state->regs[i].bo);
933 state->regs[i].bo->fence = ctx->radeon->fence;
934 /* always force dirty for relocs for now */
935 dirty |= R600_BLOCK_STATUS_DIRTY;
936 }
937
938 r600_context_dirty_block(ctx, block, dirty, id);
939 }
940 }
941
942 void r600_context_pipe_state_set_resource(struct r600_context *ctx, struct r600_pipe_state *state, unsigned offset)
943 {
944 struct r600_range *range;
945 struct r600_block *block;
946 int i;
947 int dirty;
948 int num_regs = ctx->radeon->chip_class >= EVERGREEN ? 8 : 7;
949
950 range = &ctx->range[CTX_RANGE_ID(ctx, offset)];
951 block = range->blocks[CTX_BLOCK_ID(ctx, offset)];
952 if (state == NULL) {
953 block->status &= ~(R600_BLOCK_STATUS_ENABLED | R600_BLOCK_STATUS_DIRTY);
954 r600_bo_reference(ctx->radeon, &block->reloc[1].bo, NULL);
955 r600_bo_reference(ctx->radeon , &block->reloc[2].bo, NULL);
956 LIST_DELINIT(&block->list);
957 return;
958 }
959
960 dirty = block->status & R600_BLOCK_STATUS_DIRTY;
961
962 for (i = 0; i < num_regs; i++) {
963 if (block->reg[i] != state->regs[i].value) {
964 dirty |= R600_BLOCK_STATUS_DIRTY;
965 block->reg[i] = state->regs[i].value;
966 }
967 }
968
969 /* if no BOs on block, force dirty */
970 if (!block->reloc[1].bo || !block->reloc[2].bo)
971 dirty |= R600_BLOCK_STATUS_DIRTY;
972
973 if (!dirty) {
974 if (state->regs[0].bo) {
975 if ((block->reloc[1].bo->bo->handle != state->regs[0].bo->bo->handle) ||
976 (block->reloc[2].bo->bo->handle != state->regs[0].bo->bo->handle))
977 dirty |= R600_BLOCK_STATUS_DIRTY;
978 } else {
979 if ((block->reloc[1].bo->bo->handle != state->regs[2].bo->bo->handle) ||
980 (block->reloc[2].bo->bo->handle != state->regs[3].bo->bo->handle))
981 dirty |= R600_BLOCK_STATUS_DIRTY;
982 }
983 }
984 if (!dirty) {
985 if (state->regs[0].bo)
986 state->regs[0].bo->fence = ctx->radeon->fence;
987 else {
988 state->regs[2].bo->fence = ctx->radeon->fence;
989 state->regs[3].bo->fence = ctx->radeon->fence;
990 }
991 } else {
992 r600_bo_reference(ctx->radeon, &block->reloc[1].bo, NULL);
993 r600_bo_reference(ctx->radeon, &block->reloc[2].bo, NULL);
994 if (state->regs[0].bo) {
995 /* VERTEX RESOURCE, we preted there is 2 bo to relocate so
996 * we have single case btw VERTEX & TEXTURE resource
997 */
998 r600_bo_reference(ctx->radeon, &block->reloc[1].bo, state->regs[0].bo);
999 r600_bo_reference(ctx->radeon, &block->reloc[2].bo, state->regs[0].bo);
1000 state->regs[0].bo->fence = ctx->radeon->fence;
1001 } else {
1002 /* TEXTURE RESOURCE */
1003 r600_bo_reference(ctx->radeon, &block->reloc[1].bo, state->regs[2].bo);
1004 r600_bo_reference(ctx->radeon, &block->reloc[2].bo, state->regs[3].bo);
1005 state->regs[2].bo->fence = ctx->radeon->fence;
1006 state->regs[3].bo->fence = ctx->radeon->fence;
1007 }
1008 }
1009 r600_context_dirty_block(ctx, block, dirty, num_regs - 1);
1010 }
1011
1012 void r600_context_pipe_state_set_ps_resource(struct r600_context *ctx, struct r600_pipe_state *state, unsigned rid)
1013 {
1014 unsigned offset = R_038000_SQ_TEX_RESOURCE_WORD0_0 + 0x1C * rid;
1015
1016 r600_context_pipe_state_set_resource(ctx, state, offset);
1017 }
1018
1019 void r600_context_pipe_state_set_vs_resource(struct r600_context *ctx, struct r600_pipe_state *state, unsigned rid)
1020 {
1021 unsigned offset = R_038000_SQ_TEX_RESOURCE_WORD0_0 + 0x1180 + 0x1C * rid;
1022
1023 r600_context_pipe_state_set_resource(ctx, state, offset);
1024 }
1025
1026 void r600_context_pipe_state_set_fs_resource(struct r600_context *ctx, struct r600_pipe_state *state, unsigned rid)
1027 {
1028 unsigned offset = R_038000_SQ_TEX_RESOURCE_WORD0_0 + 0x2300 + 0x1C * rid;
1029
1030 r600_context_pipe_state_set_resource(ctx, state, offset);
1031 }
1032
1033 static inline void r600_context_pipe_state_set_sampler(struct r600_context *ctx, struct r600_pipe_state *state, unsigned offset)
1034 {
1035 struct r600_range *range;
1036 struct r600_block *block;
1037 int i;
1038 int dirty;
1039
1040 range = &ctx->range[CTX_RANGE_ID(ctx, offset)];
1041 block = range->blocks[CTX_BLOCK_ID(ctx, offset)];
1042 if (state == NULL) {
1043 block->status &= ~(R600_BLOCK_STATUS_ENABLED | R600_BLOCK_STATUS_DIRTY);
1044 LIST_DELINIT(&block->list);
1045 return;
1046 }
1047 dirty = block->status & R600_BLOCK_STATUS_DIRTY;
1048 for (i = 0; i < 3; i++) {
1049 if (block->reg[i] != state->regs[i].value) {
1050 block->reg[i] = state->regs[i].value;
1051 dirty |= R600_BLOCK_STATUS_DIRTY;
1052 }
1053 }
1054
1055 r600_context_dirty_block(ctx, block, dirty, 2);
1056 }
1057
1058 static inline void r600_context_ps_partial_flush(struct r600_context *ctx)
1059 {
1060 if (!(ctx->flags & R600_CONTEXT_DRAW_PENDING))
1061 return;
1062
1063 ctx->pm4[ctx->pm4_cdwords++] = PKT3(PKT3_EVENT_WRITE, 0, 0);
1064 ctx->pm4[ctx->pm4_cdwords++] = EVENT_TYPE(EVENT_TYPE_PS_PARTIAL_FLUSH) | EVENT_INDEX(4);
1065
1066 ctx->flags &= ~R600_CONTEXT_DRAW_PENDING;
1067 }
1068
1069 static inline void r600_context_pipe_state_set_sampler_border(struct r600_context *ctx, struct r600_pipe_state *state, unsigned offset)
1070 {
1071 struct r600_range *range;
1072 struct r600_block *block;
1073 int i;
1074 int dirty;
1075
1076 range = &ctx->range[CTX_RANGE_ID(ctx, offset)];
1077 block = range->blocks[CTX_BLOCK_ID(ctx, offset)];
1078 if (state == NULL) {
1079 block->status &= ~(R600_BLOCK_STATUS_ENABLED | R600_BLOCK_STATUS_DIRTY);
1080 LIST_DELINIT(&block->list);
1081 return;
1082 }
1083 if (state->nregs <= 3) {
1084 return;
1085 }
1086 dirty = block->status & R600_BLOCK_STATUS_DIRTY;
1087 for (i = 0; i < 4; i++) {
1088 if (block->reg[i] != state->regs[i + 3].value) {
1089 block->reg[i] = state->regs[i + 3].value;
1090 dirty |= R600_BLOCK_STATUS_DIRTY;
1091 }
1092 }
1093
1094 /* We have to flush the shaders before we change the border color
1095 * registers, or previous draw commands that haven't completed yet
1096 * will end up using the new border color. */
1097 if (dirty & R600_BLOCK_STATUS_DIRTY)
1098 r600_context_ps_partial_flush(ctx);
1099
1100 r600_context_dirty_block(ctx, block, dirty, 3);
1101 }
1102
1103 void r600_context_pipe_state_set_ps_sampler(struct r600_context *ctx, struct r600_pipe_state *state, unsigned id)
1104 {
1105 unsigned offset;
1106
1107 offset = 0x0003C000 + id * 0xc;
1108 r600_context_pipe_state_set_sampler(ctx, state, offset);
1109 offset = 0x0000A400 + id * 0x10;
1110 r600_context_pipe_state_set_sampler_border(ctx, state, offset);
1111 }
1112
1113 void r600_context_pipe_state_set_vs_sampler(struct r600_context *ctx, struct r600_pipe_state *state, unsigned id)
1114 {
1115 unsigned offset;
1116
1117 offset = 0x0003C0D8 + id * 0xc;
1118 r600_context_pipe_state_set_sampler(ctx, state, offset);
1119 offset = 0x0000A600 + id * 0x10;
1120 r600_context_pipe_state_set_sampler_border(ctx, state, offset);
1121 }
1122
1123 struct r600_bo *r600_context_reg_bo(struct r600_context *ctx, unsigned offset)
1124 {
1125 struct r600_range *range;
1126 struct r600_block *block;
1127 unsigned id;
1128
1129 range = &ctx->range[CTX_RANGE_ID(ctx, offset)];
1130 block = range->blocks[CTX_BLOCK_ID(ctx, offset)];
1131 offset -= block->start_offset;
1132 id = block->pm4_bo_index[offset >> 2];
1133 if (block->reloc[id].bo) {
1134 return block->reloc[id].bo;
1135 }
1136 return NULL;
1137 }
1138
1139 void r600_context_block_emit_dirty(struct r600_context *ctx, struct r600_block *block)
1140 {
1141 int id;
1142
1143 if (block->nreg_dirty == 0 && block->nbo == 0 && !(block->flags & REG_FLAG_DIRTY_ALWAYS)) {
1144 goto out;
1145 }
1146
1147 ctx->flags |= R600_CONTEXT_CHECK_EVENT_FLUSH;
1148 for (int j = 0; j < block->nreg; j++) {
1149 if (block->pm4_bo_index[j]) {
1150 /* find relocation */
1151 id = block->pm4_bo_index[j];
1152 r600_context_bo_reloc(ctx,
1153 &block->pm4[block->reloc[id].bo_pm4_index],
1154 block->reloc[id].bo);
1155 r600_context_bo_flush(ctx,
1156 block->reloc[id].flush_flags,
1157 block->reloc[id].flush_mask,
1158 block->reloc[id].bo);
1159 }
1160 }
1161 ctx->flags &= ~R600_CONTEXT_CHECK_EVENT_FLUSH;
1162 memcpy(&ctx->pm4[ctx->pm4_cdwords], block->pm4, block->pm4_ndwords * 4);
1163 ctx->pm4_cdwords += block->pm4_ndwords;
1164
1165 if (block->nreg_dirty != block->nreg && block->nbo == 0 && !(block->flags & REG_FLAG_DIRTY_ALWAYS)) {
1166 int new_dwords = block->nreg_dirty;
1167 uint32_t oldword, newword;
1168 ctx->pm4_cdwords -= block->pm4_ndwords;
1169 newword = oldword = ctx->pm4[ctx->pm4_cdwords];
1170 newword &= PKT_COUNT_C;
1171 newword |= PKT_COUNT_S(new_dwords);
1172 ctx->pm4[ctx->pm4_cdwords] = newword;
1173 ctx->pm4_cdwords += new_dwords + 2;
1174 }
1175 out:
1176 block->status ^= R600_BLOCK_STATUS_DIRTY;
1177 block->nreg_dirty = 0;
1178 LIST_DELINIT(&block->list);
1179 }
1180
1181 void r600_context_flush_dest_caches(struct r600_context *ctx)
1182 {
1183 struct r600_bo *cb[8];
1184 struct r600_bo *db;
1185 int i;
1186
1187 if (!(ctx->flags & R600_CONTEXT_DST_CACHES_DIRTY))
1188 return;
1189
1190 db = r600_context_reg_bo(ctx, R_02800C_DB_DEPTH_BASE);
1191 cb[0] = r600_context_reg_bo(ctx, R_028040_CB_COLOR0_BASE);
1192 cb[1] = r600_context_reg_bo(ctx, R_028044_CB_COLOR1_BASE);
1193 cb[2] = r600_context_reg_bo(ctx, R_028048_CB_COLOR2_BASE);
1194 cb[3] = r600_context_reg_bo(ctx, R_02804C_CB_COLOR3_BASE);
1195 cb[4] = r600_context_reg_bo(ctx, R_028050_CB_COLOR4_BASE);
1196 cb[5] = r600_context_reg_bo(ctx, R_028054_CB_COLOR5_BASE);
1197 cb[6] = r600_context_reg_bo(ctx, R_028058_CB_COLOR6_BASE);
1198 cb[7] = r600_context_reg_bo(ctx, R_02805C_CB_COLOR7_BASE);
1199
1200 ctx->flags |= R600_CONTEXT_CHECK_EVENT_FLUSH;
1201 /* flush the color buffers */
1202 for (i = 0; i < 8; i++) {
1203 if (!cb[i])
1204 continue;
1205
1206 r600_context_bo_flush(ctx,
1207 (S_0085F0_CB0_DEST_BASE_ENA(1) << i) |
1208 S_0085F0_CB_ACTION_ENA(1),
1209 0, cb[i]);
1210 }
1211 if (db) {
1212 r600_context_bo_flush(ctx, S_0085F0_DB_ACTION_ENA(1), 0, db);
1213 }
1214 ctx->flags &= ~R600_CONTEXT_CHECK_EVENT_FLUSH;
1215 ctx->flags &= ~R600_CONTEXT_DST_CACHES_DIRTY;
1216 }
1217
1218 void r600_context_draw(struct r600_context *ctx, const struct r600_draw *draw)
1219 {
1220 unsigned ndwords = 7;
1221 struct r600_block *dirty_block = NULL;
1222 struct r600_block *next_block;
1223
1224 if (draw->indices) {
1225 ndwords = 11;
1226 /* make sure there is enough relocation space before scheduling draw */
1227 if (ctx->creloc >= (ctx->nreloc - 1)) {
1228 r600_context_flush(ctx);
1229 }
1230 }
1231
1232 /* queries need some special values */
1233 if (ctx->num_query_running) {
1234 if (ctx->radeon->family >= CHIP_RV770) {
1235 r600_context_reg(ctx,
1236 R_028D0C_DB_RENDER_CONTROL,
1237 S_028D0C_R700_PERFECT_ZPASS_COUNTS(1),
1238 S_028D0C_R700_PERFECT_ZPASS_COUNTS(1));
1239 }
1240 r600_context_reg(ctx,
1241 R_028D10_DB_RENDER_OVERRIDE,
1242 S_028D10_NOOP_CULL_DISABLE(1),
1243 S_028D10_NOOP_CULL_DISABLE(1));
1244 }
1245
1246 /* update the max dword count to make sure we have enough space
1247 * reserved for flushing the destination caches */
1248 ctx->pm4_ndwords = RADEON_CTX_MAX_PM4 - ctx->num_dest_buffers * 7 - 16;
1249
1250 if ((ctx->pm4_dirty_cdwords + ndwords + ctx->pm4_cdwords) > ctx->pm4_ndwords) {
1251 /* need to flush */
1252 r600_context_flush(ctx);
1253 }
1254 /* at that point everythings is flushed and ctx->pm4_cdwords = 0 */
1255 if ((ctx->pm4_dirty_cdwords + ndwords) > ctx->pm4_ndwords) {
1256 R600_ERR("context is too big to be scheduled\n");
1257 return;
1258 }
1259 /* enough room to copy packet */
1260 LIST_FOR_EACH_ENTRY_SAFE(dirty_block, next_block, &ctx->dirty, list) {
1261 r600_context_block_emit_dirty(ctx, dirty_block);
1262 }
1263
1264 /* draw packet */
1265 ctx->pm4[ctx->pm4_cdwords++] = PKT3(PKT3_INDEX_TYPE, 0, ctx->predicate_drawing);
1266 ctx->pm4[ctx->pm4_cdwords++] = draw->vgt_index_type;
1267 ctx->pm4[ctx->pm4_cdwords++] = PKT3(PKT3_NUM_INSTANCES, 0, ctx->predicate_drawing);
1268 ctx->pm4[ctx->pm4_cdwords++] = draw->vgt_num_instances;
1269 if (draw->indices) {
1270 ctx->pm4[ctx->pm4_cdwords++] = PKT3(PKT3_DRAW_INDEX, 3, ctx->predicate_drawing);
1271 ctx->pm4[ctx->pm4_cdwords++] = draw->indices_bo_offset + r600_bo_offset(draw->indices);
1272 ctx->pm4[ctx->pm4_cdwords++] = 0;
1273 ctx->pm4[ctx->pm4_cdwords++] = draw->vgt_num_indices;
1274 ctx->pm4[ctx->pm4_cdwords++] = draw->vgt_draw_initiator;
1275 ctx->pm4[ctx->pm4_cdwords++] = PKT3(PKT3_NOP, 0, ctx->predicate_drawing);
1276 ctx->pm4[ctx->pm4_cdwords++] = 0;
1277 r600_context_bo_reloc(ctx, &ctx->pm4[ctx->pm4_cdwords - 1], draw->indices);
1278 } else {
1279 ctx->pm4[ctx->pm4_cdwords++] = PKT3(PKT3_DRAW_INDEX_AUTO, 1, ctx->predicate_drawing);
1280 ctx->pm4[ctx->pm4_cdwords++] = draw->vgt_num_indices;
1281 ctx->pm4[ctx->pm4_cdwords++] = draw->vgt_draw_initiator;
1282 }
1283
1284 ctx->flags |= (R600_CONTEXT_DST_CACHES_DIRTY | R600_CONTEXT_DRAW_PENDING);
1285
1286 /* all dirty state have been scheduled in current cs */
1287 ctx->pm4_dirty_cdwords = 0;
1288 }
1289
1290 void r600_context_flush(struct r600_context *ctx)
1291 {
1292 struct drm_radeon_cs drmib = {};
1293 struct drm_radeon_cs_chunk chunks[2];
1294 uint64_t chunk_array[2];
1295 unsigned fence;
1296 int r;
1297
1298 if (!ctx->pm4_cdwords)
1299 return;
1300
1301 /* suspend queries */
1302 r600_context_queries_suspend(ctx);
1303
1304 if (ctx->radeon->family >= CHIP_CEDAR)
1305 evergreen_context_flush_dest_caches(ctx);
1306 else
1307 r600_context_flush_dest_caches(ctx);
1308
1309 /* partial flush is needed to avoid lockups on some chips with user fences */
1310 ctx->pm4[ctx->pm4_cdwords++] = PKT3(PKT3_EVENT_WRITE, 0, 0);
1311 ctx->pm4[ctx->pm4_cdwords++] = EVENT_TYPE(EVENT_TYPE_PS_PARTIAL_FLUSH) | EVENT_INDEX(4);
1312 /* emit fence */
1313 ctx->pm4[ctx->pm4_cdwords++] = PKT3(PKT3_EVENT_WRITE_EOP, 4, 0);
1314 ctx->pm4[ctx->pm4_cdwords++] = EVENT_TYPE(EVENT_TYPE_CACHE_FLUSH_AND_INV_TS_EVENT) | EVENT_INDEX(5);
1315 ctx->pm4[ctx->pm4_cdwords++] = 0;
1316 ctx->pm4[ctx->pm4_cdwords++] = (1 << 29) | (0 << 24);
1317 ctx->pm4[ctx->pm4_cdwords++] = ctx->radeon->fence;
1318 ctx->pm4[ctx->pm4_cdwords++] = 0;
1319 ctx->pm4[ctx->pm4_cdwords++] = PKT3(PKT3_NOP, 0, 0);
1320 ctx->pm4[ctx->pm4_cdwords++] = 0;
1321 r600_context_bo_reloc(ctx, &ctx->pm4[ctx->pm4_cdwords - 1], ctx->radeon->fence_bo);
1322
1323 #if 1
1324 /* emit cs */
1325 drmib.num_chunks = 2;
1326 drmib.chunks = (uint64_t)(uintptr_t)chunk_array;
1327 chunks[0].chunk_id = RADEON_CHUNK_ID_IB;
1328 chunks[0].length_dw = ctx->pm4_cdwords;
1329 chunks[0].chunk_data = (uint64_t)(uintptr_t)ctx->pm4;
1330 chunks[1].chunk_id = RADEON_CHUNK_ID_RELOCS;
1331 chunks[1].length_dw = ctx->creloc * sizeof(struct r600_reloc) / 4;
1332 chunks[1].chunk_data = (uint64_t)(uintptr_t)ctx->reloc;
1333 chunk_array[0] = (uint64_t)(uintptr_t)&chunks[0];
1334 chunk_array[1] = (uint64_t)(uintptr_t)&chunks[1];
1335 r = drmCommandWriteRead(ctx->radeon->fd, DRM_RADEON_CS, &drmib,
1336 sizeof(struct drm_radeon_cs));
1337 #else
1338 *ctx->radeon->cfence = ctx->radeon->fence;
1339 #endif
1340
1341 r600_context_update_fenced_list(ctx);
1342
1343 fence = ctx->radeon->fence + 1;
1344 if (fence < ctx->radeon->fence) {
1345 /* wrap around */
1346 fence = 1;
1347 r600_context_fence_wraparound(ctx, fence);
1348 }
1349 ctx->radeon->fence = fence;
1350
1351 /* restart */
1352 for (int i = 0; i < ctx->creloc; i++) {
1353 ctx->bo[i]->reloc = NULL;
1354 ctx->bo[i]->last_flush = 0;
1355 radeon_bo_reference(ctx->radeon, &ctx->bo[i], NULL);
1356 }
1357 ctx->creloc = 0;
1358 ctx->pm4_dirty_cdwords = 0;
1359 ctx->pm4_cdwords = 0;
1360 ctx->flags = 0;
1361
1362 /* resume queries */
1363 r600_context_queries_resume(ctx);
1364
1365 /* set all valid group as dirty so they get reemited on
1366 * next draw command
1367 */
1368 for (int i = 0; i < ctx->nblocks; i++) {
1369 if (ctx->blocks[i]->status & R600_BLOCK_STATUS_ENABLED) {
1370 if(!(ctx->blocks[i]->status & R600_BLOCK_STATUS_DIRTY)) {
1371 LIST_ADDTAIL(&ctx->blocks[i]->list,&ctx->dirty);
1372 }
1373 ctx->pm4_dirty_cdwords += ctx->blocks[i]->pm4_ndwords + ctx->blocks[i]->pm4_flush_ndwords;
1374 ctx->blocks[i]->status |= R600_BLOCK_STATUS_DIRTY;
1375 ctx->blocks[i]->nreg_dirty = ctx->blocks[i]->nreg;
1376 }
1377 }
1378 }
1379
1380 void r600_context_emit_fence(struct r600_context *ctx, struct r600_bo *fence_bo, unsigned offset, unsigned value)
1381 {
1382 unsigned ndwords = 10;
1383
1384 if (((ctx->pm4_dirty_cdwords + ndwords + ctx->pm4_cdwords) > ctx->pm4_ndwords) ||
1385 (ctx->creloc >= (ctx->nreloc - 1))) {
1386 /* need to flush */
1387 r600_context_flush(ctx);
1388 }
1389
1390 ctx->pm4[ctx->pm4_cdwords++] = PKT3(PKT3_EVENT_WRITE, 0, 0);
1391 ctx->pm4[ctx->pm4_cdwords++] = EVENT_TYPE(EVENT_TYPE_PS_PARTIAL_FLUSH) | EVENT_INDEX(4);
1392 ctx->pm4[ctx->pm4_cdwords++] = PKT3(PKT3_EVENT_WRITE_EOP, 4, 0);
1393 ctx->pm4[ctx->pm4_cdwords++] = EVENT_TYPE(EVENT_TYPE_CACHE_FLUSH_AND_INV_TS_EVENT) | EVENT_INDEX(5);
1394 ctx->pm4[ctx->pm4_cdwords++] = offset << 2; /* ADDRESS_LO */
1395 ctx->pm4[ctx->pm4_cdwords++] = (1 << 29) | (0 << 24); /* DATA_SEL | INT_EN | ADDRESS_HI */
1396 ctx->pm4[ctx->pm4_cdwords++] = value; /* DATA_LO */
1397 ctx->pm4[ctx->pm4_cdwords++] = 0; /* DATA_HI */
1398 ctx->pm4[ctx->pm4_cdwords++] = PKT3(PKT3_NOP, 0, 0);
1399 ctx->pm4[ctx->pm4_cdwords++] = 0;
1400 r600_context_bo_reloc(ctx, &ctx->pm4[ctx->pm4_cdwords - 1], fence_bo);
1401 }
1402
1403 void r600_context_dump_bof(struct r600_context *ctx, const char *file)
1404 {
1405 bof_t *bcs, *blob, *array, *bo, *size, *handle, *device_id, *root;
1406 unsigned i;
1407
1408 root = device_id = bcs = blob = array = bo = size = handle = NULL;
1409 root = bof_object();
1410 if (root == NULL)
1411 goto out_err;
1412 device_id = bof_int32(ctx->radeon->device);
1413 if (device_id == NULL)
1414 goto out_err;
1415 if (bof_object_set(root, "device_id", device_id))
1416 goto out_err;
1417 bof_decref(device_id);
1418 device_id = NULL;
1419 /* dump relocs */
1420 blob = bof_blob(ctx->creloc * 16, ctx->reloc);
1421 if (blob == NULL)
1422 goto out_err;
1423 if (bof_object_set(root, "reloc", blob))
1424 goto out_err;
1425 bof_decref(blob);
1426 blob = NULL;
1427 /* dump cs */
1428 blob = bof_blob(ctx->pm4_cdwords * 4, ctx->pm4);
1429 if (blob == NULL)
1430 goto out_err;
1431 if (bof_object_set(root, "pm4", blob))
1432 goto out_err;
1433 bof_decref(blob);
1434 blob = NULL;
1435 /* dump bo */
1436 array = bof_array();
1437 if (array == NULL)
1438 goto out_err;
1439 for (i = 0; i < ctx->creloc; i++) {
1440 struct radeon_bo *rbo = ctx->bo[i];
1441 bo = bof_object();
1442 if (bo == NULL)
1443 goto out_err;
1444 size = bof_int32(rbo->size);
1445 if (size == NULL)
1446 goto out_err;
1447 if (bof_object_set(bo, "size", size))
1448 goto out_err;
1449 bof_decref(size);
1450 size = NULL;
1451 handle = bof_int32(rbo->handle);
1452 if (handle == NULL)
1453 goto out_err;
1454 if (bof_object_set(bo, "handle", handle))
1455 goto out_err;
1456 bof_decref(handle);
1457 handle = NULL;
1458 radeon_bo_map(ctx->radeon, rbo);
1459 blob = bof_blob(rbo->size, rbo->data);
1460 radeon_bo_unmap(ctx->radeon, rbo);
1461 if (blob == NULL)
1462 goto out_err;
1463 if (bof_object_set(bo, "data", blob))
1464 goto out_err;
1465 bof_decref(blob);
1466 blob = NULL;
1467 if (bof_array_append(array, bo))
1468 goto out_err;
1469 bof_decref(bo);
1470 bo = NULL;
1471 }
1472 if (bof_object_set(root, "bo", array))
1473 goto out_err;
1474 bof_dump_file(root, file);
1475 out_err:
1476 bof_decref(blob);
1477 bof_decref(array);
1478 bof_decref(bo);
1479 bof_decref(size);
1480 bof_decref(handle);
1481 bof_decref(device_id);
1482 bof_decref(root);
1483 }
1484
1485 static boolean r600_query_result(struct r600_context *ctx, struct r600_query *query, boolean wait)
1486 {
1487 u64 start, end;
1488 u32 *results;
1489 int i;
1490 int size;
1491
1492 if (wait)
1493 results = r600_bo_map(ctx->radeon, query->buffer, PB_USAGE_CPU_READ, NULL);
1494 else
1495 results = r600_bo_map(ctx->radeon, query->buffer, PB_USAGE_DONTBLOCK | PB_USAGE_CPU_READ, NULL);
1496 if (!results)
1497 return FALSE;
1498
1499 size = query->num_results * (query->type == PIPE_QUERY_OCCLUSION_COUNTER ? ctx->max_db : 1);
1500 for (i = 0; i < size; i += 4) {
1501 start = (u64)results[i] | (u64)results[i + 1] << 32;
1502 end = (u64)results[i + 2] | (u64)results[i + 3] << 32;
1503 if (((start & 0x8000000000000000UL) && (end & 0x8000000000000000UL))
1504 || query->type == PIPE_QUERY_TIME_ELAPSED) {
1505 query->result += end - start;
1506 }
1507 }
1508 r600_bo_unmap(ctx->radeon, query->buffer);
1509 query->num_results = 0;
1510
1511 return TRUE;
1512 }
1513
1514 void r600_query_begin(struct r600_context *ctx, struct r600_query *query)
1515 {
1516 unsigned required_space;
1517 int num_backends = r600_get_num_backends(ctx->radeon);
1518
1519 /* query request needs 6/8 dwords for begin + 6/8 dwords for end */
1520 if (query->type == PIPE_QUERY_TIME_ELAPSED)
1521 required_space = 16;
1522 else
1523 required_space = 12;
1524
1525 if ((required_space + ctx->pm4_cdwords) > ctx->pm4_ndwords) {
1526 /* need to flush */
1527 r600_context_flush(ctx);
1528 }
1529
1530 /* if query buffer is full force a flush */
1531 if (query->num_results*4 >= query->buffer_size - 16) {
1532 r600_context_flush(ctx);
1533 r600_query_result(ctx, query, TRUE);
1534 }
1535
1536 if (query->type == PIPE_QUERY_OCCLUSION_COUNTER &&
1537 num_backends > 0 && num_backends < ctx->max_db) {
1538 /* as per info on ZPASS the driver must set the unusued DB top bits */
1539 u32 *results;
1540 int i;
1541
1542 results = r600_bo_map(ctx->radeon, query->buffer, PB_USAGE_DONTBLOCK | PB_USAGE_CPU_WRITE, NULL);
1543 if (results) {
1544 memset(results + (query->num_results * 4), 0, ctx->max_db * 4 * 4);
1545
1546 for (i = num_backends; i < ctx->max_db; i++) {
1547 results[(i * 4)+1] = 0x80000000;
1548 results[(i * 4)+3] = 0x80000000;
1549 }
1550 r600_bo_unmap(ctx->radeon, query->buffer);
1551 }
1552 }
1553
1554 /* emit begin query */
1555 if (query->type == PIPE_QUERY_TIME_ELAPSED) {
1556 ctx->pm4[ctx->pm4_cdwords++] = PKT3(PKT3_EVENT_WRITE_EOP, 4, 0);
1557 ctx->pm4[ctx->pm4_cdwords++] = EVENT_TYPE(EVENT_TYPE_CACHE_FLUSH_AND_INV_TS_EVENT) | EVENT_INDEX(5);
1558 ctx->pm4[ctx->pm4_cdwords++] = query->num_results*4 + r600_bo_offset(query->buffer);
1559 ctx->pm4[ctx->pm4_cdwords++] = (3 << 29);
1560 ctx->pm4[ctx->pm4_cdwords++] = 0;
1561 ctx->pm4[ctx->pm4_cdwords++] = 0;
1562 } else {
1563 ctx->pm4[ctx->pm4_cdwords++] = PKT3(PKT3_EVENT_WRITE, 2, 0);
1564 ctx->pm4[ctx->pm4_cdwords++] = EVENT_TYPE(EVENT_TYPE_ZPASS_DONE) | EVENT_INDEX(1);
1565 ctx->pm4[ctx->pm4_cdwords++] = query->num_results*4 + r600_bo_offset(query->buffer);
1566 ctx->pm4[ctx->pm4_cdwords++] = 0;
1567 }
1568 ctx->pm4[ctx->pm4_cdwords++] = PKT3(PKT3_NOP, 0, 0);
1569 ctx->pm4[ctx->pm4_cdwords++] = 0;
1570 r600_context_bo_reloc(ctx, &ctx->pm4[ctx->pm4_cdwords - 1], query->buffer);
1571
1572 query->state |= R600_QUERY_STATE_STARTED;
1573 query->state ^= R600_QUERY_STATE_ENDED;
1574 ctx->num_query_running++;
1575 }
1576
1577 void r600_query_end(struct r600_context *ctx, struct r600_query *query)
1578 {
1579 /* emit begin query */
1580 if (query->type == PIPE_QUERY_TIME_ELAPSED) {
1581 ctx->pm4[ctx->pm4_cdwords++] = PKT3(PKT3_EVENT_WRITE_EOP, 4, 0);
1582 ctx->pm4[ctx->pm4_cdwords++] = EVENT_TYPE(EVENT_TYPE_CACHE_FLUSH_AND_INV_TS_EVENT) | EVENT_INDEX(5);
1583 ctx->pm4[ctx->pm4_cdwords++] = query->num_results*4 + 8 + r600_bo_offset(query->buffer);
1584 ctx->pm4[ctx->pm4_cdwords++] = (3 << 29);
1585 ctx->pm4[ctx->pm4_cdwords++] = 0;
1586 ctx->pm4[ctx->pm4_cdwords++] = 0;
1587 } else {
1588 ctx->pm4[ctx->pm4_cdwords++] = PKT3(PKT3_EVENT_WRITE, 2, 0);
1589 ctx->pm4[ctx->pm4_cdwords++] = EVENT_TYPE(EVENT_TYPE_ZPASS_DONE) | EVENT_INDEX(1);
1590 ctx->pm4[ctx->pm4_cdwords++] = query->num_results*4 + 8 + r600_bo_offset(query->buffer);
1591 ctx->pm4[ctx->pm4_cdwords++] = 0;
1592 }
1593 ctx->pm4[ctx->pm4_cdwords++] = PKT3(PKT3_NOP, 0, 0);
1594 ctx->pm4[ctx->pm4_cdwords++] = 0;
1595 r600_context_bo_reloc(ctx, &ctx->pm4[ctx->pm4_cdwords - 1], query->buffer);
1596
1597 query->num_results += 4 * (query->type == PIPE_QUERY_OCCLUSION_COUNTER ? ctx->max_db : 1);
1598 query->state ^= R600_QUERY_STATE_STARTED;
1599 query->state |= R600_QUERY_STATE_ENDED;
1600 ctx->num_query_running--;
1601 }
1602
1603 void r600_query_predication(struct r600_context *ctx, struct r600_query *query, int operation,
1604 int flag_wait)
1605 {
1606 ctx->pm4[ctx->pm4_cdwords++] = PKT3(PKT3_SET_PREDICATION, 1, 0);
1607
1608 if (operation == PREDICATION_OP_CLEAR) {
1609 ctx->pm4[ctx->pm4_cdwords++] = 0;
1610 ctx->pm4[ctx->pm4_cdwords++] = PRED_OP(PREDICATION_OP_CLEAR);
1611 } else {
1612 int results_base = query->num_results - (4 * ctx->max_db);
1613
1614 if (results_base < 0)
1615 results_base = 0;
1616
1617 ctx->pm4[ctx->pm4_cdwords++] = results_base*4 + r600_bo_offset(query->buffer);
1618 ctx->pm4[ctx->pm4_cdwords++] = PRED_OP(operation) | (flag_wait ? PREDICATION_HINT_WAIT : PREDICATION_HINT_NOWAIT_DRAW) | PREDICATION_DRAW_VISIBLE;
1619 ctx->pm4[ctx->pm4_cdwords++] = PKT3(PKT3_NOP, 0, 0);
1620 ctx->pm4[ctx->pm4_cdwords++] = 0;
1621 r600_context_bo_reloc(ctx, &ctx->pm4[ctx->pm4_cdwords - 1], query->buffer);
1622 }
1623 }
1624
1625 struct r600_query *r600_context_query_create(struct r600_context *ctx, unsigned query_type)
1626 {
1627 struct r600_query *query;
1628
1629 if (query_type != PIPE_QUERY_OCCLUSION_COUNTER && query_type != PIPE_QUERY_TIME_ELAPSED)
1630 return NULL;
1631
1632 query = calloc(1, sizeof(struct r600_query));
1633 if (query == NULL)
1634 return NULL;
1635
1636 query->type = query_type;
1637 query->buffer_size = 4096;
1638
1639 /* As of GL4, query buffers are normally read by the CPU after
1640 * being written by the gpu, hence staging is probably a good
1641 * usage pattern.
1642 */
1643 query->buffer = r600_bo(ctx->radeon, query->buffer_size, 1, 0,
1644 PIPE_USAGE_STAGING);
1645 if (!query->buffer) {
1646 free(query);
1647 return NULL;
1648 }
1649
1650 LIST_ADDTAIL(&query->list, &ctx->query_list);
1651
1652 return query;
1653 }
1654
1655 void r600_context_query_destroy(struct r600_context *ctx, struct r600_query *query)
1656 {
1657 r600_bo_reference(ctx->radeon, &query->buffer, NULL);
1658 LIST_DELINIT(&query->list);
1659 free(query);
1660 }
1661
1662 boolean r600_context_query_result(struct r600_context *ctx,
1663 struct r600_query *query,
1664 boolean wait, void *vresult)
1665 {
1666 uint64_t *result = (uint64_t*)vresult;
1667
1668 if (query->num_results) {
1669 r600_context_flush(ctx);
1670 }
1671 if (!r600_query_result(ctx, query, wait))
1672 return FALSE;
1673 if (query->type == PIPE_QUERY_TIME_ELAPSED)
1674 *result = (1000000*query->result)/r600_get_clock_crystal_freq(ctx->radeon);
1675 else
1676 *result = query->result;
1677 query->result = 0;
1678 return TRUE;
1679 }
1680
1681 void r600_context_queries_suspend(struct r600_context *ctx)
1682 {
1683 struct r600_query *query;
1684
1685 LIST_FOR_EACH_ENTRY(query, &ctx->query_list, list) {
1686 if (query->state & R600_QUERY_STATE_STARTED) {
1687 r600_query_end(ctx, query);
1688 query->state |= R600_QUERY_STATE_SUSPENDED;
1689 }
1690 }
1691 }
1692
1693 void r600_context_queries_resume(struct r600_context *ctx)
1694 {
1695 struct r600_query *query;
1696
1697 LIST_FOR_EACH_ENTRY(query, &ctx->query_list, list) {
1698 if (query->state & R600_QUERY_STATE_SUSPENDED) {
1699 r600_query_begin(ctx, query);
1700 query->state ^= R600_QUERY_STATE_SUSPENDED;
1701 }
1702 }
1703 }