src/gallium/winsys/radeon/drm/radeon_drm_bo.c

   1 /*
   2  * Copyright © 2011 Marek Olšák <maraeo@gmail.com>
   3  * All Rights Reserved.
   4  *
   5  * Permission is hereby granted, free of charge, to any person obtaining
   6  * a copy of this software and associated documentation files (the
   7  * "Software"), to deal in the Software without restriction, including
   8  * without limitation the rights to use, copy, modify, merge, publish,
   9  * distribute, sub license, and/or sell copies of the Software, and to
  10  * permit persons to whom the Software is furnished to do so, subject to
  11  * the following conditions:
  12  *
  13  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  14  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
  15  * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  16  * NON-INFRINGEMENT. IN NO EVENT SHALL THE COPYRIGHT HOLDERS, AUTHORS
  17  * AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  18  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
  20  * USE OR OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  * The above copyright notice and this permission notice (including the
  23  * next paragraph) shall be included in all copies or substantial portions
  24  * of the Software.
  25  */
  26
  27 #define _FILE_OFFSET_BITS 64
  28 #include "radeon_drm_cs.h"
  29
  30 #include "util/u_hash_table.h"
  31 #include "util/u_memory.h"
  32 #include "util/u_simple_list.h"
  33 #include "os/os_thread.h"
  34
  35 #include "state_tracker/drm_driver.h"
  36
  37 #include <sys/ioctl.h>
  38 #include <sys/mman.h>
  39 #include <xf86drm.h>
  40 #include <errno.h>
  41
  42 #define RADEON_BO_FLAGS_MACRO_TILE  1
  43 #define RADEON_BO_FLAGS_MICRO_TILE  2
  44 #define RADEON_BO_FLAGS_MICRO_TILE_SQUARE 0x20
  45
  46 extern const struct pb_vtbl radeon_bo_vtbl;
  47
  48
  49 static INLINE struct radeon_bo *radeon_bo(struct pb_buffer *bo)
  50 {
  51     assert(bo->vtbl == &radeon_bo_vtbl);
  52     return (struct radeon_bo *)bo;
  53 }
  54
  55 struct radeon_bomgr {
  56     /* Base class. */
  57     struct pb_manager base;
  58
  59     /* Winsys. */
  60     struct radeon_drm_winsys *rws;
  61
  62     /* List of buffer handles and its mutex. */
  63     struct util_hash_table *bo_handles;
  64     pipe_mutex bo_handles_mutex;
  65 };
  66
  67 static INLINE struct radeon_bomgr *radeon_bomgr(struct pb_manager *mgr)
  68 {
  69     return (struct radeon_bomgr *)mgr;
  70 }
  71
  72 static struct radeon_bo *get_radeon_bo(struct pb_buffer *_buf)
  73 {
  74     struct radeon_bo *bo = NULL;
  75
  76     if (_buf->vtbl == &radeon_bo_vtbl) {
  77         bo = radeon_bo(_buf);
  78     } else {
  79         struct pb_buffer *base_buf;
  80         pb_size offset;
  81         pb_get_base_buffer(_buf, &base_buf, &offset);
  82
  83         if (base_buf->vtbl == &radeon_bo_vtbl)
  84             bo = radeon_bo(base_buf);
  85     }
  86
  87     return bo;
  88 }
  89
  90 static void radeon_bo_wait(struct pb_buffer *_buf)
  91 {
  92     struct radeon_bo *bo = get_radeon_bo(_buf);
  93     struct drm_radeon_gem_wait_idle args = {};
  94
  95     while (p_atomic_read(&bo->num_active_ioctls)) {
  96         sched_yield();
  97     }
  98
  99     args.handle = bo->handle;
 100     while (drmCommandWriteRead(bo->rws->fd, DRM_RADEON_GEM_WAIT_IDLE,
 101                                &args, sizeof(args)) == -EBUSY);
 102 }
 103
 104 static boolean radeon_bo_is_busy(struct pb_buffer *_buf)
 105 {
 106     struct radeon_bo *bo = get_radeon_bo(_buf);
 107     struct drm_radeon_gem_busy args = {};
 108     boolean busy;
 109
 110     if (p_atomic_read(&bo->num_active_ioctls)) {
 111         return TRUE;
 112     }
 113
 114     args.handle = bo->handle;
 115     busy = drmCommandWriteRead(bo->rws->fd, DRM_RADEON_GEM_BUSY,
 116                                &args, sizeof(args)) != 0;
 117
 118     return busy;
 119 }
 120
 121 static void radeon_bo_destroy(struct pb_buffer *_buf)
 122 {
 123     struct radeon_bo *bo = radeon_bo(_buf);
 124     struct drm_gem_close args = {};
 125
 126     if (bo->name) {
 127         pipe_mutex_lock(bo->mgr->bo_handles_mutex);
 128         util_hash_table_remove(bo->mgr->bo_handles,
 129                                (void*)(uintptr_t)bo->name);
 130         pipe_mutex_unlock(bo->mgr->bo_handles_mutex);
 131     }
 132
 133     if (bo->ptr)
 134         munmap(bo->ptr, bo->size);
 135
 136     /* Close object. */
 137     args.handle = bo->handle;
 138     drmIoctl(bo->rws->fd, DRM_IOCTL_GEM_CLOSE, &args);
 139     pipe_mutex_destroy(bo->map_mutex);
 140     FREE(bo);
 141 }
 142
 143 static unsigned get_pb_usage_from_transfer_flags(enum pipe_transfer_usage usage)
 144 {
 145     unsigned res = 0;
 146
 147     if (usage & PIPE_TRANSFER_WRITE)
 148         res |= PB_USAGE_CPU_WRITE;
 149
 150     if (usage & PIPE_TRANSFER_DONTBLOCK)
 151         res |= PB_USAGE_DONTBLOCK;
 152
 153     if (usage & PIPE_TRANSFER_UNSYNCHRONIZED)
 154         res |= PB_USAGE_UNSYNCHRONIZED;
 155
 156     return res;
 157 }
 158
 159 static void *radeon_bo_map_internal(struct pb_buffer *_buf,
 160                                     unsigned flags, void *flush_ctx)
 161 {
 162     struct radeon_bo *bo = radeon_bo(_buf);
 163     struct radeon_drm_cs *cs = flush_ctx;
 164     struct drm_radeon_gem_mmap args = {};
 165     void *ptr;
 166
 167     /* If it's not unsynchronized bo_map, flush CS if needed and then wait. */
 168     if (!(flags & PB_USAGE_UNSYNCHRONIZED)) {
 169         /* DONTBLOCK doesn't make sense with UNSYNCHRONIZED. */
 170         if (flags & PB_USAGE_DONTBLOCK) {
 171             if (radeon_bo_is_referenced_by_cs(cs, bo)) {
 172                 cs->flush_cs(cs->flush_data, RADEON_FLUSH_ASYNC);
 173                 return NULL;
 174             }
 175
 176             if (radeon_bo_is_busy((struct pb_buffer*)bo)) {
 177                 return NULL;
 178             }
 179         } else {
 180             if (!(flags & PB_USAGE_CPU_WRITE)) {
 181                 /* Mapping for read.
 182                  *
 183                  * Since we are mapping for read, we don't need to wait
 184                  * if the GPU is using the buffer for read too
 185                  * (neither one is changing it).
 186                  *
 187                  * Only check whether the buffer is being used for write. */
 188                 if (radeon_bo_is_referenced_by_cs_for_write(cs, bo)) {
 189                     cs->flush_cs(cs->flush_data, 0);
 190                     radeon_bo_wait((struct pb_buffer*)bo);
 191                 } else {
 192                     /* XXX We could check whether the buffer is busy for write here. */
 193                     radeon_bo_wait((struct pb_buffer*)bo);
 194                 }
 195             } else {
 196                 /* Mapping for write. */
 197                 if (radeon_bo_is_referenced_by_cs(cs, bo)) {
 198                     cs->flush_cs(cs->flush_data, 0);
 199                 } else {
 200                     /* Try to avoid busy-waiting in radeon_bo_wait. */
 201                     if (p_atomic_read(&bo->num_active_ioctls))
 202                         radeon_drm_cs_sync_flush(cs);
 203                 }
 204
 205                 radeon_bo_wait((struct pb_buffer*)bo);
 206             }
 207         }
 208     }
 209
 210     /* Return the pointer if it's already mapped. */
 211     if (bo->ptr)
 212         return bo->ptr;
 213
 214     /* Map the buffer. */
 215     pipe_mutex_lock(bo->map_mutex);
 216     /* Return the pointer if it's already mapped (in case of a race). */
 217     if (bo->ptr) {
 218         pipe_mutex_unlock(bo->map_mutex);
 219         return bo->ptr;
 220     }
 221     args.handle = bo->handle;
 222     args.offset = 0;
 223     args.size = (uint64_t)bo->size;
 224     if (drmCommandWriteRead(bo->rws->fd,
 225                             DRM_RADEON_GEM_MMAP,
 226                             &args,
 227                             sizeof(args))) {
 228         pipe_mutex_unlock(bo->map_mutex);
 229         fprintf(stderr, "radeon: gem_mmap failed: %p 0x%08X\n",
 230                 bo, bo->handle);
 231         return NULL;
 232     }
 233
 234     ptr = mmap(0, args.size, PROT_READ|PROT_WRITE, MAP_SHARED,
 235                bo->rws->fd, args.addr_ptr);
 236     if (ptr == MAP_FAILED) {
 237         pipe_mutex_unlock(bo->map_mutex);
 238         fprintf(stderr, "radeon: mmap failed, errno: %i\n", errno);
 239         return NULL;
 240     }
 241     bo->ptr = ptr;
 242     pipe_mutex_unlock(bo->map_mutex);
 243
 244     return bo->ptr;
 245 }
 246
 247 static void radeon_bo_unmap_internal(struct pb_buffer *_buf)
 248 {
 249     /* NOP */
 250 }
 251
 252 static void radeon_bo_get_base_buffer(struct pb_buffer *buf,
 253                                       struct pb_buffer **base_buf,
 254                                       unsigned *offset)
 255 {
 256     *base_buf = buf;
 257     *offset = 0;
 258 }
 259
 260 static enum pipe_error radeon_bo_validate(struct pb_buffer *_buf,
 261                                           struct pb_validate *vl,
 262                                           unsigned flags)
 263 {
 264     /* Always pinned */
 265     return PIPE_OK;
 266 }
 267
 268 static void radeon_bo_fence(struct pb_buffer *buf,
 269                             struct pipe_fence_handle *fence)
 270 {
 271 }
 272
 273 const struct pb_vtbl radeon_bo_vtbl = {
 274     radeon_bo_destroy,
 275     radeon_bo_map_internal,
 276     radeon_bo_unmap_internal,
 277     radeon_bo_validate,
 278     radeon_bo_fence,
 279     radeon_bo_get_base_buffer,
 280 };
 281
 282 static struct pb_buffer *radeon_bomgr_create_bo(struct pb_manager *_mgr,
 283                                                 pb_size size,
 284                                                 const struct pb_desc *desc)
 285 {
 286     struct radeon_bomgr *mgr = radeon_bomgr(_mgr);
 287     struct radeon_drm_winsys *rws = mgr->rws;
 288     struct radeon_bo *bo;
 289     struct drm_radeon_gem_create args = {};
 290
 291     args.size = size;
 292     args.alignment = desc->alignment;
 293     args.initial_domain =
 294         (desc->usage & RADEON_PB_USAGE_DOMAIN_GTT  ?
 295          RADEON_GEM_DOMAIN_GTT  : 0) |
 296         (desc->usage & RADEON_PB_USAGE_DOMAIN_VRAM ?
 297          RADEON_GEM_DOMAIN_VRAM : 0);
 298
 299     if (drmCommandWriteRead(rws->fd, DRM_RADEON_GEM_CREATE,
 300                             &args, sizeof(args))) {
 301         fprintf(stderr, "radeon: Failed to allocate a buffer:\n");
 302         fprintf(stderr, "radeon:    size      : %d bytes\n", size);
 303         fprintf(stderr, "radeon:    alignment : %d bytes\n", desc->alignment);
 304         fprintf(stderr, "radeon:    domains   : %d\n", args.initial_domain);
 305         return NULL;
 306     }
 307
 308     bo = CALLOC_STRUCT(radeon_bo);
 309     if (!bo)
 310         return NULL;
 311
 312     pipe_reference_init(&bo->base.base.reference, 1);
 313     bo->base.base.alignment = desc->alignment;
 314     bo->base.base.usage = desc->usage;
 315     bo->base.base.size = size;
 316     bo->base.vtbl = &radeon_bo_vtbl;
 317     bo->mgr = mgr;
 318     bo->rws = mgr->rws;
 319     bo->handle = args.handle;
 320     bo->size = size;
 321     pipe_mutex_init(bo->map_mutex);
 322
 323     return &bo->base;
 324 }
 325
 326 static void radeon_bomgr_flush(struct pb_manager *mgr)
 327 {
 328     /* NOP */
 329 }
 330
 331 /* This is for the cache bufmgr. */
 332 static boolean radeon_bomgr_is_buffer_busy(struct pb_manager *_mgr,
 333                                            struct pb_buffer *_buf)
 334 {
 335    struct radeon_bo *bo = radeon_bo(_buf);
 336
 337    if (radeon_bo_is_referenced_by_any_cs(bo)) {
 338        return TRUE;
 339    }
 340
 341    if (radeon_bo_is_busy((struct pb_buffer*)bo)) {
 342        return TRUE;
 343    }
 344
 345    return FALSE;
 346 }
 347
 348 static void radeon_bomgr_destroy(struct pb_manager *_mgr)
 349 {
 350     struct radeon_bomgr *mgr = radeon_bomgr(_mgr);
 351     util_hash_table_destroy(mgr->bo_handles);
 352     pipe_mutex_destroy(mgr->bo_handles_mutex);
 353     FREE(mgr);
 354 }
 355
 356 #define PTR_TO_UINT(x) ((unsigned)((intptr_t)(x)))
 357
 358 static unsigned handle_hash(void *key)
 359 {
 360     return PTR_TO_UINT(key);
 361 }
 362
 363 static int handle_compare(void *key1, void *key2)
 364 {
 365     return PTR_TO_UINT(key1) != PTR_TO_UINT(key2);
 366 }
 367
 368 struct pb_manager *radeon_bomgr_create(struct radeon_drm_winsys *rws)
 369 {
 370     struct radeon_bomgr *mgr;
 371
 372     mgr = CALLOC_STRUCT(radeon_bomgr);
 373     if (!mgr)
 374         return NULL;
 375
 376     mgr->base.destroy = radeon_bomgr_destroy;
 377     mgr->base.create_buffer = radeon_bomgr_create_bo;
 378     mgr->base.flush = radeon_bomgr_flush;
 379     mgr->base.is_buffer_busy = radeon_bomgr_is_buffer_busy;
 380
 381     mgr->rws = rws;
 382     mgr->bo_handles = util_hash_table_create(handle_hash, handle_compare);
 383     pipe_mutex_init(mgr->bo_handles_mutex);
 384     return &mgr->base;
 385 }
 386
 387 static void *radeon_bo_map(struct pb_buffer *buf,
 388                            struct radeon_winsys_cs *cs,
 389                            enum pipe_transfer_usage usage)
 390 {
 391     return pb_map(buf, get_pb_usage_from_transfer_flags(usage), cs);
 392 }
 393
 394 static void radeon_bo_get_tiling(struct pb_buffer *_buf,
 395                                  enum radeon_bo_layout *microtiled,
 396                                  enum radeon_bo_layout *macrotiled)
 397 {
 398     struct radeon_bo *bo = get_radeon_bo(_buf);
 399     struct drm_radeon_gem_set_tiling args = {};
 400
 401     args.handle = bo->handle;
 402
 403     drmCommandWriteRead(bo->rws->fd,
 404                         DRM_RADEON_GEM_GET_TILING,
 405                         &args,
 406                         sizeof(args));
 407
 408     *microtiled = RADEON_LAYOUT_LINEAR;
 409     *macrotiled = RADEON_LAYOUT_LINEAR;
 410     if (args.tiling_flags & RADEON_BO_FLAGS_MICRO_TILE)
 411         *microtiled = RADEON_LAYOUT_TILED;
 412
 413     if (args.tiling_flags & RADEON_BO_FLAGS_MACRO_TILE)
 414         *macrotiled = RADEON_LAYOUT_TILED;
 415 }
 416
 417 static void radeon_bo_set_tiling(struct pb_buffer *_buf,
 418                                  struct radeon_winsys_cs *rcs,
 419                                  enum radeon_bo_layout microtiled,
 420                                  enum radeon_bo_layout macrotiled,
 421                                  uint32_t pitch)
 422 {
 423     struct radeon_bo *bo = get_radeon_bo(_buf);
 424     struct radeon_drm_cs *cs = radeon_drm_cs(rcs);
 425     struct drm_radeon_gem_set_tiling args = {};
 426
 427     /* Tiling determines how DRM treats the buffer data.
 428      * We must flush CS when changing it if the buffer is referenced. */
 429     if (cs && radeon_bo_is_referenced_by_cs(cs, bo)) {
 430         cs->flush_cs(cs->flush_data, 0);
 431     }
 432
 433     while (p_atomic_read(&bo->num_active_ioctls)) {
 434         sched_yield();
 435     }
 436
 437     if (microtiled == RADEON_LAYOUT_TILED)
 438         args.tiling_flags |= RADEON_BO_FLAGS_MICRO_TILE;
 439     else if (microtiled == RADEON_LAYOUT_SQUARETILED)
 440         args.tiling_flags |= RADEON_BO_FLAGS_MICRO_TILE_SQUARE;
 441
 442     if (macrotiled == RADEON_LAYOUT_TILED)
 443         args.tiling_flags |= RADEON_BO_FLAGS_MACRO_TILE;
 444
 445     args.handle = bo->handle;
 446     args.pitch = pitch;
 447
 448     drmCommandWriteRead(bo->rws->fd,
 449                         DRM_RADEON_GEM_SET_TILING,
 450                         &args,
 451                         sizeof(args));
 452 }
 453
 454 static struct radeon_winsys_cs_handle *radeon_drm_get_cs_handle(
 455         struct pb_buffer *_buf)
 456 {
 457     /* return radeon_bo. */
 458     return (struct radeon_winsys_cs_handle*)get_radeon_bo(_buf);
 459 }
 460
 461 static unsigned get_pb_usage_from_create_flags(enum radeon_bo_domain domain)
 462 {
 463     unsigned res = 0;
 464
 465     if (domain & RADEON_DOMAIN_GTT)
 466         res |= RADEON_PB_USAGE_DOMAIN_GTT;
 467
 468     if (domain & RADEON_DOMAIN_VRAM)
 469         res |= RADEON_PB_USAGE_DOMAIN_VRAM;
 470
 471     return res;
 472 }
 473
 474 static struct pb_buffer *
 475 radeon_winsys_bo_create(struct radeon_winsys *rws,
 476                         unsigned size,
 477                         unsigned alignment,
 478                         unsigned bind,
 479                         enum radeon_bo_domain domain)
 480 {
 481     struct radeon_drm_winsys *ws = radeon_drm_winsys(rws);
 482     struct pb_desc desc;
 483     struct pb_manager *provider;
 484     struct pb_buffer *buffer;
 485
 486     memset(&desc, 0, sizeof(desc));
 487     desc.alignment = alignment;
 488     desc.usage = get_pb_usage_from_create_flags(domain);
 489
 490     /* Assign a buffer manager. */
 491     if (bind & (PIPE_BIND_VERTEX_BUFFER | PIPE_BIND_INDEX_BUFFER |
 492                 PIPE_BIND_CONSTANT_BUFFER))
 493         provider = ws->cman;
 494     else
 495         provider = ws->kman;
 496
 497     buffer = provider->create_buffer(provider, size, &desc);
 498     if (!buffer)
 499         return NULL;
 500
 501     return (struct pb_buffer*)buffer;
 502 }
 503
 504 static struct pb_buffer *radeon_winsys_bo_from_handle(struct radeon_winsys *rws,
 505                                                            struct winsys_handle *whandle,
 506                                                            unsigned *stride,
 507                                                            unsigned *size)
 508 {
 509     struct radeon_drm_winsys *ws = radeon_drm_winsys(rws);
 510     struct radeon_bo *bo;
 511     struct radeon_bomgr *mgr = radeon_bomgr(ws->kman);
 512     struct drm_gem_open open_arg = {};
 513
 514     /* We must maintain a list of pairs <handle, bo>, so that we always return
 515      * the same BO for one particular handle. If we didn't do that and created
 516      * more than one BO for the same handle and then relocated them in a CS,
 517      * we would hit a deadlock in the kernel.
 518      *
 519      * The list of pairs is guarded by a mutex, of course. */
 520     pipe_mutex_lock(mgr->bo_handles_mutex);
 521
 522     /* First check if there already is an existing bo for the handle. */
 523     bo = util_hash_table_get(mgr->bo_handles, (void*)(uintptr_t)whandle->handle);
 524     if (bo) {
 525         /* Increase the refcount. */
 526         struct pb_buffer *b = NULL;
 527         pb_reference(&b, &bo->base);
 528         goto done;
 529     }
 530
 531     /* There isn't, create a new one. */
 532     bo = CALLOC_STRUCT(radeon_bo);
 533     if (!bo) {
 534         goto fail;
 535     }
 536
 537     /* Open the BO. */
 538     open_arg.name = whandle->handle;
 539     if (drmIoctl(ws->fd, DRM_IOCTL_GEM_OPEN, &open_arg)) {
 540         FREE(bo);
 541         goto fail;
 542     }
 543     bo->handle = open_arg.handle;
 544     bo->size = open_arg.size;
 545     bo->name = whandle->handle;
 546
 547     /* Initialize it. */
 548     pipe_reference_init(&bo->base.base.reference, 1);
 549     bo->base.base.alignment = 0;
 550     bo->base.base.usage = PB_USAGE_GPU_WRITE | PB_USAGE_GPU_READ;
 551     bo->base.base.size = bo->size;
 552     bo->base.vtbl = &radeon_bo_vtbl;
 553     bo->mgr = mgr;
 554     bo->rws = mgr->rws;
 555     pipe_mutex_init(bo->map_mutex);
 556
 557     util_hash_table_set(mgr->bo_handles, (void*)(uintptr_t)whandle->handle, bo);
 558
 559 done:
 560     pipe_mutex_unlock(mgr->bo_handles_mutex);
 561
 562     if (stride)
 563         *stride = whandle->stride;
 564     if (size)
 565         *size = bo->base.base.size;
 566
 567     return (struct pb_buffer*)bo;
 568
 569 fail:
 570     pipe_mutex_unlock(mgr->bo_handles_mutex);
 571     return NULL;
 572 }
 573
 574 static boolean radeon_winsys_bo_get_handle(struct pb_buffer *buffer,
 575                                            unsigned stride,
 576                                            struct winsys_handle *whandle)
 577 {
 578     struct drm_gem_flink flink = {};
 579     struct radeon_bo *bo = get_radeon_bo(buffer);
 580
 581     if (whandle->type == DRM_API_HANDLE_TYPE_SHARED) {
 582         if (!bo->flinked) {
 583             flink.handle = bo->handle;
 584
 585             if (ioctl(bo->rws->fd, DRM_IOCTL_GEM_FLINK, &flink)) {
 586                 return FALSE;
 587             }
 588
 589             bo->flinked = TRUE;
 590             bo->flink = flink.name;
 591         }
 592         whandle->handle = bo->flink;
 593     } else if (whandle->type == DRM_API_HANDLE_TYPE_KMS) {
 594         whandle->handle = bo->handle;
 595     }
 596
 597     whandle->stride = stride;
 598     return TRUE;
 599 }
 600
 601 void radeon_bomgr_init_functions(struct radeon_drm_winsys *ws)
 602 {
 603     ws->base.buffer_get_cs_handle = radeon_drm_get_cs_handle;
 604     ws->base.buffer_set_tiling = radeon_bo_set_tiling;
 605     ws->base.buffer_get_tiling = radeon_bo_get_tiling;
 606     ws->base.buffer_map = radeon_bo_map;
 607     ws->base.buffer_unmap = pb_unmap;
 608     ws->base.buffer_wait = radeon_bo_wait;
 609     ws->base.buffer_is_busy = radeon_bo_is_busy;
 610     ws->base.buffer_create = radeon_winsys_bo_create;
 611     ws->base.buffer_from_handle = radeon_winsys_bo_from_handle;
 612     ws->base.buffer_get_handle = radeon_winsys_bo_get_handle;
 613 }