src/gallium/winsys/radeon/drm/radeon_drm_bo.c

   1 /*
   2  * Copyright © 2011 Marek Olšák <maraeo@gmail.com>
   3  * All Rights Reserved.
   4  *
   5  * Permission is hereby granted, free of charge, to any person obtaining
   6  * a copy of this software and associated documentation files (the
   7  * "Software"), to deal in the Software without restriction, including
   8  * without limitation the rights to use, copy, modify, merge, publish,
   9  * distribute, sub license, and/or sell copies of the Software, and to
  10  * permit persons to whom the Software is furnished to do so, subject to
  11  * the following conditions:
  12  *
  13  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  14  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
  15  * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  16  * NON-INFRINGEMENT. IN NO EVENT SHALL THE COPYRIGHT HOLDERS, AUTHORS
  17  * AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  18  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
  20  * USE OR OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  * The above copyright notice and this permission notice (including the
  23  * next paragraph) shall be included in all copies or substantial portions
  24  * of the Software.
  25  */
  26
  27 #define _FILE_OFFSET_BITS 64
  28 #include "radeon_drm_cs.h"
  29
  30 #include "util/u_hash_table.h"
  31 #include "util/u_memory.h"
  32 #include "util/u_simple_list.h"
  33 #include "os/os_thread.h"
  34
  35 #include "state_tracker/drm_driver.h"
  36
  37 #include <sys/ioctl.h>
  38 #include <sys/mman.h>
  39 #include <xf86drm.h>
  40 #include <errno.h>
  41
  42 #define RADEON_BO_FLAGS_MACRO_TILE  1
  43 #define RADEON_BO_FLAGS_MICRO_TILE  2
  44 #define RADEON_BO_FLAGS_MICRO_TILE_SQUARE 0x20
  45
  46 #ifndef DRM_RADEON_GEM_WAIT
  47 #define DRM_RADEON_GEM_WAIT             0x2b
  48
  49 #define RADEON_GEM_NO_WAIT      0x1
  50 #define RADEON_GEM_USAGE_READ   0x2
  51 #define RADEON_GEM_USAGE_WRITE  0x4
  52
  53 struct drm_radeon_gem_wait {
  54         uint32_t        handle;
  55         uint32_t        flags;  /* one of RADEON_GEM_* */
  56 };
  57
  58 #endif
  59
  60
  61 extern const struct pb_vtbl radeon_bo_vtbl;
  62
  63
  64 static INLINE struct radeon_bo *radeon_bo(struct pb_buffer *bo)
  65 {
  66     assert(bo->vtbl == &radeon_bo_vtbl);
  67     return (struct radeon_bo *)bo;
  68 }
  69
  70 struct radeon_bomgr {
  71     /* Base class. */
  72     struct pb_manager base;
  73
  74     /* Winsys. */
  75     struct radeon_drm_winsys *rws;
  76
  77     /* List of buffer handles and its mutex. */
  78     struct util_hash_table *bo_handles;
  79     pipe_mutex bo_handles_mutex;
  80 };
  81
  82 static INLINE struct radeon_bomgr *radeon_bomgr(struct pb_manager *mgr)
  83 {
  84     return (struct radeon_bomgr *)mgr;
  85 }
  86
  87 static struct radeon_bo *get_radeon_bo(struct pb_buffer *_buf)
  88 {
  89     struct radeon_bo *bo = NULL;
  90
  91     if (_buf->vtbl == &radeon_bo_vtbl) {
  92         bo = radeon_bo(_buf);
  93     } else {
  94         struct pb_buffer *base_buf;
  95         pb_size offset;
  96         pb_get_base_buffer(_buf, &base_buf, &offset);
  97
  98         if (base_buf->vtbl == &radeon_bo_vtbl)
  99             bo = radeon_bo(base_buf);
 100     }
 101
 102     return bo;
 103 }
 104
 105 static void radeon_bo_wait(struct pb_buffer *_buf, enum radeon_bo_usage usage)
 106 {
 107     struct radeon_bo *bo = get_radeon_bo(_buf);
 108
 109     while (p_atomic_read(&bo->num_active_ioctls)) {
 110         sched_yield();
 111     }
 112
 113     if (bo->rws->info.drm_minor >= 12) {
 114         struct drm_radeon_gem_wait args = {};
 115         args.handle = bo->handle;
 116         args.flags = usage;
 117         while (drmCommandWriteRead(bo->rws->fd, DRM_RADEON_GEM_WAIT,
 118                                    &args, sizeof(args)) == -EBUSY);
 119     } else {
 120         struct drm_radeon_gem_wait_idle args = {};
 121         args.handle = bo->handle;
 122         while (drmCommandWriteRead(bo->rws->fd, DRM_RADEON_GEM_WAIT_IDLE,
 123                                    &args, sizeof(args)) == -EBUSY);
 124     }
 125 }
 126
 127 static boolean radeon_bo_is_busy(struct pb_buffer *_buf,
 128                                  enum radeon_bo_usage usage)
 129 {
 130     struct radeon_bo *bo = get_radeon_bo(_buf);
 131
 132     if (p_atomic_read(&bo->num_active_ioctls)) {
 133         return TRUE;
 134     }
 135
 136     if (bo->rws->info.drm_minor >= 12) {
 137         struct drm_radeon_gem_wait args = {};
 138         args.handle = bo->handle;
 139         args.flags = usage | RADEON_GEM_NO_WAIT;
 140         return drmCommandWriteRead(bo->rws->fd, DRM_RADEON_GEM_WAIT,
 141                                    &args, sizeof(args)) != 0;
 142     } else {
 143         struct drm_radeon_gem_busy args = {};
 144         args.handle = bo->handle;
 145         return drmCommandWriteRead(bo->rws->fd, DRM_RADEON_GEM_BUSY,
 146                                    &args, sizeof(args)) != 0;
 147     }
 148 }
 149
 150 static void radeon_bo_destroy(struct pb_buffer *_buf)
 151 {
 152     struct radeon_bo *bo = radeon_bo(_buf);
 153     struct drm_gem_close args = {};
 154
 155     if (bo->name) {
 156         pipe_mutex_lock(bo->mgr->bo_handles_mutex);
 157         util_hash_table_remove(bo->mgr->bo_handles,
 158                                (void*)(uintptr_t)bo->name);
 159         pipe_mutex_unlock(bo->mgr->bo_handles_mutex);
 160     }
 161
 162     if (bo->ptr)
 163         munmap(bo->ptr, bo->size);
 164
 165     /* Close object. */
 166     args.handle = bo->handle;
 167     drmIoctl(bo->rws->fd, DRM_IOCTL_GEM_CLOSE, &args);
 168     pipe_mutex_destroy(bo->map_mutex);
 169     FREE(bo);
 170 }
 171
 172 static unsigned get_pb_usage_from_transfer_flags(enum pipe_transfer_usage usage)
 173 {
 174     unsigned res = 0;
 175
 176     if (usage & PIPE_TRANSFER_WRITE)
 177         res |= PB_USAGE_CPU_WRITE;
 178
 179     if (usage & PIPE_TRANSFER_DONTBLOCK)
 180         res |= PB_USAGE_DONTBLOCK;
 181
 182     if (usage & PIPE_TRANSFER_UNSYNCHRONIZED)
 183         res |= PB_USAGE_UNSYNCHRONIZED;
 184
 185     return res;
 186 }
 187
 188 static void *radeon_bo_map_internal(struct pb_buffer *_buf,
 189                                     unsigned flags, void *flush_ctx)
 190 {
 191     struct radeon_bo *bo = radeon_bo(_buf);
 192     struct radeon_drm_cs *cs = flush_ctx;
 193     struct drm_radeon_gem_mmap args = {};
 194     void *ptr;
 195
 196     /* If it's not unsynchronized bo_map, flush CS if needed and then wait. */
 197     if (!(flags & PB_USAGE_UNSYNCHRONIZED)) {
 198         /* DONTBLOCK doesn't make sense with UNSYNCHRONIZED. */
 199         if (flags & PB_USAGE_DONTBLOCK) {
 200             if (radeon_bo_is_referenced_by_cs(cs, bo)) {
 201                 cs->flush_cs(cs->flush_data, RADEON_FLUSH_ASYNC);
 202                 return NULL;
 203             }
 204
 205             if (radeon_bo_is_busy((struct pb_buffer*)bo, RADEON_USAGE_READWRITE)) {
 206                 return NULL;
 207             }
 208         } else {
 209             if (!(flags & PB_USAGE_CPU_WRITE)) {
 210                 /* Mapping for read.
 211                  *
 212                  * Since we are mapping for read, we don't need to wait
 213                  * if the GPU is using the buffer for read too
 214                  * (neither one is changing it).
 215                  *
 216                  * Only check whether the buffer is being used for write. */
 217                 if (radeon_bo_is_referenced_by_cs_for_write(cs, bo)) {
 218                     cs->flush_cs(cs->flush_data, 0);
 219                     radeon_bo_wait((struct pb_buffer*)bo,
 220                                    RADEON_USAGE_READWRITE);
 221                 } else {
 222                     /* XXX We could check whether the buffer is busy for write here. */
 223                     radeon_bo_wait((struct pb_buffer*)bo,
 224                                    RADEON_USAGE_READWRITE);
 225                 }
 226             } else {
 227                 /* Mapping for write. */
 228                 if (radeon_bo_is_referenced_by_cs(cs, bo)) {
 229                     cs->flush_cs(cs->flush_data, 0);
 230                 } else {
 231                     /* Try to avoid busy-waiting in radeon_bo_wait. */
 232                     if (p_atomic_read(&bo->num_active_ioctls))
 233                         radeon_drm_cs_sync_flush(cs);
 234                 }
 235
 236                 radeon_bo_wait((struct pb_buffer*)bo, RADEON_USAGE_READWRITE);
 237             }
 238         }
 239     }
 240
 241     /* Return the pointer if it's already mapped. */
 242     if (bo->ptr)
 243         return bo->ptr;
 244
 245     /* Map the buffer. */
 246     pipe_mutex_lock(bo->map_mutex);
 247     /* Return the pointer if it's already mapped (in case of a race). */
 248     if (bo->ptr) {
 249         pipe_mutex_unlock(bo->map_mutex);
 250         return bo->ptr;
 251     }
 252     args.handle = bo->handle;
 253     args.offset = 0;
 254     args.size = (uint64_t)bo->size;
 255     if (drmCommandWriteRead(bo->rws->fd,
 256                             DRM_RADEON_GEM_MMAP,
 257                             &args,
 258                             sizeof(args))) {
 259         pipe_mutex_unlock(bo->map_mutex);
 260         fprintf(stderr, "radeon: gem_mmap failed: %p 0x%08X\n",
 261                 bo, bo->handle);
 262         return NULL;
 263     }
 264
 265     ptr = mmap(0, args.size, PROT_READ|PROT_WRITE, MAP_SHARED,
 266                bo->rws->fd, args.addr_ptr);
 267     if (ptr == MAP_FAILED) {
 268         pipe_mutex_unlock(bo->map_mutex);
 269         fprintf(stderr, "radeon: mmap failed, errno: %i\n", errno);
 270         return NULL;
 271     }
 272     bo->ptr = ptr;
 273     pipe_mutex_unlock(bo->map_mutex);
 274
 275     return bo->ptr;
 276 }
 277
 278 static void radeon_bo_unmap_internal(struct pb_buffer *_buf)
 279 {
 280     /* NOP */
 281 }
 282
 283 static void radeon_bo_get_base_buffer(struct pb_buffer *buf,
 284                                       struct pb_buffer **base_buf,
 285                                       unsigned *offset)
 286 {
 287     *base_buf = buf;
 288     *offset = 0;
 289 }
 290
 291 static enum pipe_error radeon_bo_validate(struct pb_buffer *_buf,
 292                                           struct pb_validate *vl,
 293                                           unsigned flags)
 294 {
 295     /* Always pinned */
 296     return PIPE_OK;
 297 }
 298
 299 static void radeon_bo_fence(struct pb_buffer *buf,
 300                             struct pipe_fence_handle *fence)
 301 {
 302 }
 303
 304 const struct pb_vtbl radeon_bo_vtbl = {
 305     radeon_bo_destroy,
 306     radeon_bo_map_internal,
 307     radeon_bo_unmap_internal,
 308     radeon_bo_validate,
 309     radeon_bo_fence,
 310     radeon_bo_get_base_buffer,
 311 };
 312
 313 static struct pb_buffer *radeon_bomgr_create_bo(struct pb_manager *_mgr,
 314                                                 pb_size size,
 315                                                 const struct pb_desc *desc)
 316 {
 317     struct radeon_bomgr *mgr = radeon_bomgr(_mgr);
 318     struct radeon_drm_winsys *rws = mgr->rws;
 319     struct radeon_bo *bo;
 320     struct drm_radeon_gem_create args = {};
 321
 322     args.size = size;
 323     args.alignment = desc->alignment;
 324     args.initial_domain =
 325         (desc->usage & RADEON_PB_USAGE_DOMAIN_GTT  ?
 326          RADEON_GEM_DOMAIN_GTT  : 0) |
 327         (desc->usage & RADEON_PB_USAGE_DOMAIN_VRAM ?
 328          RADEON_GEM_DOMAIN_VRAM : 0);
 329
 330     if (drmCommandWriteRead(rws->fd, DRM_RADEON_GEM_CREATE,
 331                             &args, sizeof(args))) {
 332         fprintf(stderr, "radeon: Failed to allocate a buffer:\n");
 333         fprintf(stderr, "radeon:    size      : %d bytes\n", size);
 334         fprintf(stderr, "radeon:    alignment : %d bytes\n", desc->alignment);
 335         fprintf(stderr, "radeon:    domains   : %d\n", args.initial_domain);
 336         return NULL;
 337     }
 338
 339     bo = CALLOC_STRUCT(radeon_bo);
 340     if (!bo)
 341         return NULL;
 342
 343     pipe_reference_init(&bo->base.base.reference, 1);
 344     bo->base.base.alignment = desc->alignment;
 345     bo->base.base.usage = desc->usage;
 346     bo->base.base.size = size;
 347     bo->base.vtbl = &radeon_bo_vtbl;
 348     bo->mgr = mgr;
 349     bo->rws = mgr->rws;
 350     bo->handle = args.handle;
 351     bo->size = size;
 352     pipe_mutex_init(bo->map_mutex);
 353
 354     return &bo->base;
 355 }
 356
 357 static void radeon_bomgr_flush(struct pb_manager *mgr)
 358 {
 359     /* NOP */
 360 }
 361
 362 /* This is for the cache bufmgr. */
 363 static boolean radeon_bomgr_is_buffer_busy(struct pb_manager *_mgr,
 364                                            struct pb_buffer *_buf)
 365 {
 366    struct radeon_bo *bo = radeon_bo(_buf);
 367
 368    if (radeon_bo_is_referenced_by_any_cs(bo)) {
 369        return TRUE;
 370    }
 371
 372    if (radeon_bo_is_busy((struct pb_buffer*)bo, RADEON_USAGE_READWRITE)) {
 373        return TRUE;
 374    }
 375
 376    return FALSE;
 377 }
 378
 379 static void radeon_bomgr_destroy(struct pb_manager *_mgr)
 380 {
 381     struct radeon_bomgr *mgr = radeon_bomgr(_mgr);
 382     util_hash_table_destroy(mgr->bo_handles);
 383     pipe_mutex_destroy(mgr->bo_handles_mutex);
 384     FREE(mgr);
 385 }
 386
 387 #define PTR_TO_UINT(x) ((unsigned)((intptr_t)(x)))
 388
 389 static unsigned handle_hash(void *key)
 390 {
 391     return PTR_TO_UINT(key);
 392 }
 393
 394 static int handle_compare(void *key1, void *key2)
 395 {
 396     return PTR_TO_UINT(key1) != PTR_TO_UINT(key2);
 397 }
 398
 399 struct pb_manager *radeon_bomgr_create(struct radeon_drm_winsys *rws)
 400 {
 401     struct radeon_bomgr *mgr;
 402
 403     mgr = CALLOC_STRUCT(radeon_bomgr);
 404     if (!mgr)
 405         return NULL;
 406
 407     mgr->base.destroy = radeon_bomgr_destroy;
 408     mgr->base.create_buffer = radeon_bomgr_create_bo;
 409     mgr->base.flush = radeon_bomgr_flush;
 410     mgr->base.is_buffer_busy = radeon_bomgr_is_buffer_busy;
 411
 412     mgr->rws = rws;
 413     mgr->bo_handles = util_hash_table_create(handle_hash, handle_compare);
 414     pipe_mutex_init(mgr->bo_handles_mutex);
 415     return &mgr->base;
 416 }
 417
 418 static void *radeon_bo_map(struct pb_buffer *buf,
 419                            struct radeon_winsys_cs *cs,
 420                            enum pipe_transfer_usage usage)
 421 {
 422     return pb_map(buf, get_pb_usage_from_transfer_flags(usage), cs);
 423 }
 424
 425 static void radeon_bo_get_tiling(struct pb_buffer *_buf,
 426                                  enum radeon_bo_layout *microtiled,
 427                                  enum radeon_bo_layout *macrotiled)
 428 {
 429     struct radeon_bo *bo = get_radeon_bo(_buf);
 430     struct drm_radeon_gem_set_tiling args = {};
 431
 432     args.handle = bo->handle;
 433
 434     drmCommandWriteRead(bo->rws->fd,
 435                         DRM_RADEON_GEM_GET_TILING,
 436                         &args,
 437                         sizeof(args));
 438
 439     *microtiled = RADEON_LAYOUT_LINEAR;
 440     *macrotiled = RADEON_LAYOUT_LINEAR;
 441     if (args.tiling_flags & RADEON_BO_FLAGS_MICRO_TILE)
 442         *microtiled = RADEON_LAYOUT_TILED;
 443
 444     if (args.tiling_flags & RADEON_BO_FLAGS_MACRO_TILE)
 445         *macrotiled = RADEON_LAYOUT_TILED;
 446 }
 447
 448 static void radeon_bo_set_tiling(struct pb_buffer *_buf,
 449                                  struct radeon_winsys_cs *rcs,
 450                                  enum radeon_bo_layout microtiled,
 451                                  enum radeon_bo_layout macrotiled,
 452                                  uint32_t pitch)
 453 {
 454     struct radeon_bo *bo = get_radeon_bo(_buf);
 455     struct radeon_drm_cs *cs = radeon_drm_cs(rcs);
 456     struct drm_radeon_gem_set_tiling args = {};
 457
 458     /* Tiling determines how DRM treats the buffer data.
 459      * We must flush CS when changing it if the buffer is referenced. */
 460     if (cs && radeon_bo_is_referenced_by_cs(cs, bo)) {
 461         cs->flush_cs(cs->flush_data, 0);
 462     }
 463
 464     while (p_atomic_read(&bo->num_active_ioctls)) {
 465         sched_yield();
 466     }
 467
 468     if (microtiled == RADEON_LAYOUT_TILED)
 469         args.tiling_flags |= RADEON_BO_FLAGS_MICRO_TILE;
 470     else if (microtiled == RADEON_LAYOUT_SQUARETILED)
 471         args.tiling_flags |= RADEON_BO_FLAGS_MICRO_TILE_SQUARE;
 472
 473     if (macrotiled == RADEON_LAYOUT_TILED)
 474         args.tiling_flags |= RADEON_BO_FLAGS_MACRO_TILE;
 475
 476     args.handle = bo->handle;
 477     args.pitch = pitch;
 478
 479     drmCommandWriteRead(bo->rws->fd,
 480                         DRM_RADEON_GEM_SET_TILING,
 481                         &args,
 482                         sizeof(args));
 483 }
 484
 485 static struct radeon_winsys_cs_handle *radeon_drm_get_cs_handle(
 486         struct pb_buffer *_buf)
 487 {
 488     /* return radeon_bo. */
 489     return (struct radeon_winsys_cs_handle*)get_radeon_bo(_buf);
 490 }
 491
 492 static unsigned get_pb_usage_from_create_flags(enum radeon_bo_domain domain)
 493 {
 494     unsigned res = 0;
 495
 496     if (domain & RADEON_DOMAIN_GTT)
 497         res |= RADEON_PB_USAGE_DOMAIN_GTT;
 498
 499     if (domain & RADEON_DOMAIN_VRAM)
 500         res |= RADEON_PB_USAGE_DOMAIN_VRAM;
 501
 502     return res;
 503 }
 504
 505 static struct pb_buffer *
 506 radeon_winsys_bo_create(struct radeon_winsys *rws,
 507                         unsigned size,
 508                         unsigned alignment,
 509                         unsigned bind,
 510                         enum radeon_bo_domain domain)
 511 {
 512     struct radeon_drm_winsys *ws = radeon_drm_winsys(rws);
 513     struct pb_desc desc;
 514     struct pb_manager *provider;
 515     struct pb_buffer *buffer;
 516
 517     memset(&desc, 0, sizeof(desc));
 518     desc.alignment = alignment;
 519     desc.usage = get_pb_usage_from_create_flags(domain);
 520
 521     /* Assign a buffer manager. */
 522     if (bind & (PIPE_BIND_VERTEX_BUFFER | PIPE_BIND_INDEX_BUFFER |
 523                 PIPE_BIND_CONSTANT_BUFFER))
 524         provider = ws->cman;
 525     else
 526         provider = ws->kman;
 527
 528     buffer = provider->create_buffer(provider, size, &desc);
 529     if (!buffer)
 530         return NULL;
 531
 532     return (struct pb_buffer*)buffer;
 533 }
 534
 535 static struct pb_buffer *radeon_winsys_bo_from_handle(struct radeon_winsys *rws,
 536                                                            struct winsys_handle *whandle,
 537                                                            unsigned *stride,
 538                                                            unsigned *size)
 539 {
 540     struct radeon_drm_winsys *ws = radeon_drm_winsys(rws);
 541     struct radeon_bo *bo;
 542     struct radeon_bomgr *mgr = radeon_bomgr(ws->kman);
 543     struct drm_gem_open open_arg = {};
 544
 545     /* We must maintain a list of pairs <handle, bo>, so that we always return
 546      * the same BO for one particular handle. If we didn't do that and created
 547      * more than one BO for the same handle and then relocated them in a CS,
 548      * we would hit a deadlock in the kernel.
 549      *
 550      * The list of pairs is guarded by a mutex, of course. */
 551     pipe_mutex_lock(mgr->bo_handles_mutex);
 552
 553     /* First check if there already is an existing bo for the handle. */
 554     bo = util_hash_table_get(mgr->bo_handles, (void*)(uintptr_t)whandle->handle);
 555     if (bo) {
 556         /* Increase the refcount. */
 557         struct pb_buffer *b = NULL;
 558         pb_reference(&b, &bo->base);
 559         goto done;
 560     }
 561
 562     /* There isn't, create a new one. */
 563     bo = CALLOC_STRUCT(radeon_bo);
 564     if (!bo) {
 565         goto fail;
 566     }
 567
 568     /* Open the BO. */
 569     open_arg.name = whandle->handle;
 570     if (drmIoctl(ws->fd, DRM_IOCTL_GEM_OPEN, &open_arg)) {
 571         FREE(bo);
 572         goto fail;
 573     }
 574     bo->handle = open_arg.handle;
 575     bo->size = open_arg.size;
 576     bo->name = whandle->handle;
 577
 578     /* Initialize it. */
 579     pipe_reference_init(&bo->base.base.reference, 1);
 580     bo->base.base.alignment = 0;
 581     bo->base.base.usage = PB_USAGE_GPU_WRITE | PB_USAGE_GPU_READ;
 582     bo->base.base.size = bo->size;
 583     bo->base.vtbl = &radeon_bo_vtbl;
 584     bo->mgr = mgr;
 585     bo->rws = mgr->rws;
 586     pipe_mutex_init(bo->map_mutex);
 587
 588     util_hash_table_set(mgr->bo_handles, (void*)(uintptr_t)whandle->handle, bo);
 589
 590 done:
 591     pipe_mutex_unlock(mgr->bo_handles_mutex);
 592
 593     if (stride)
 594         *stride = whandle->stride;
 595     if (size)
 596         *size = bo->base.base.size;
 597
 598     return (struct pb_buffer*)bo;
 599
 600 fail:
 601     pipe_mutex_unlock(mgr->bo_handles_mutex);
 602     return NULL;
 603 }
 604
 605 static boolean radeon_winsys_bo_get_handle(struct pb_buffer *buffer,
 606                                            unsigned stride,
 607                                            struct winsys_handle *whandle)
 608 {
 609     struct drm_gem_flink flink = {};
 610     struct radeon_bo *bo = get_radeon_bo(buffer);
 611
 612     if (whandle->type == DRM_API_HANDLE_TYPE_SHARED) {
 613         if (!bo->flinked) {
 614             flink.handle = bo->handle;
 615
 616             if (ioctl(bo->rws->fd, DRM_IOCTL_GEM_FLINK, &flink)) {
 617                 return FALSE;
 618             }
 619
 620             bo->flinked = TRUE;
 621             bo->flink = flink.name;
 622         }
 623         whandle->handle = bo->flink;
 624     } else if (whandle->type == DRM_API_HANDLE_TYPE_KMS) {
 625         whandle->handle = bo->handle;
 626     }
 627
 628     whandle->stride = stride;
 629     return TRUE;
 630 }
 631
 632 void radeon_bomgr_init_functions(struct radeon_drm_winsys *ws)
 633 {
 634     ws->base.buffer_get_cs_handle = radeon_drm_get_cs_handle;
 635     ws->base.buffer_set_tiling = radeon_bo_set_tiling;
 636     ws->base.buffer_get_tiling = radeon_bo_get_tiling;
 637     ws->base.buffer_map = radeon_bo_map;
 638     ws->base.buffer_unmap = pb_unmap;
 639     ws->base.buffer_wait = radeon_bo_wait;
 640     ws->base.buffer_is_busy = radeon_bo_is_busy;
 641     ws->base.buffer_create = radeon_winsys_bo_create;
 642     ws->base.buffer_from_handle = radeon_winsys_bo_from_handle;
 643     ws->base.buffer_get_handle = radeon_winsys_bo_get_handle;
 644 }