src/gallium/winsys/radeon/drm/radeon_drm_bo.c

   1 /*
   2  * Copyright © 2011 Marek Olšák <maraeo@gmail.com>
   3  * All Rights Reserved.
   4  *
   5  * Permission is hereby granted, free of charge, to any person obtaining
   6  * a copy of this software and associated documentation files (the
   7  * "Software"), to deal in the Software without restriction, including
   8  * without limitation the rights to use, copy, modify, merge, publish,
   9  * distribute, sub license, and/or sell copies of the Software, and to
  10  * permit persons to whom the Software is furnished to do so, subject to
  11  * the following conditions:
  12  *
  13  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  14  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
  15  * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  16  * NON-INFRINGEMENT. IN NO EVENT SHALL THE COPYRIGHT HOLDERS, AUTHORS
  17  * AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  18  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
  20  * USE OR OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  * The above copyright notice and this permission notice (including the
  23  * next paragraph) shall be included in all copies or substantial portions
  24  * of the Software.
  25  */
  26
  27 #define _FILE_OFFSET_BITS 64
  28 #include "radeon_drm_cs.h"
  29
  30 #include "util/u_hash_table.h"
  31 #include "util/u_memory.h"
  32 #include "util/u_simple_list.h"
  33 #include "os/os_thread.h"
  34
  35 #include "state_tracker/drm_driver.h"
  36
  37 #include <sys/ioctl.h>
  38 #include <sys/mman.h>
  39 #include <xf86drm.h>
  40 #include <errno.h>
  41
  42 #define RADEON_BO_FLAGS_MACRO_TILE  1
  43 #define RADEON_BO_FLAGS_MICRO_TILE  2
  44 #define RADEON_BO_FLAGS_MICRO_TILE_SQUARE 0x20
  45
  46 extern const struct pb_vtbl radeon_bo_vtbl;
  47
  48
  49 static INLINE struct radeon_bo *radeon_bo(struct pb_buffer *bo)
  50 {
  51     assert(bo->vtbl == &radeon_bo_vtbl);
  52     return (struct radeon_bo *)bo;
  53 }
  54
  55 struct radeon_bomgr {
  56     /* Base class. */
  57     struct pb_manager base;
  58
  59     /* Winsys. */
  60     struct radeon_drm_winsys *rws;
  61
  62     /* List of buffer handles and its mutex. */
  63     struct util_hash_table *bo_handles;
  64     pipe_mutex bo_handles_mutex;
  65 };
  66
  67 static INLINE struct radeon_bomgr *radeon_bomgr(struct pb_manager *mgr)
  68 {
  69     return (struct radeon_bomgr *)mgr;
  70 }
  71
  72 static struct radeon_bo *get_radeon_bo(struct pb_buffer *_buf)
  73 {
  74     struct radeon_bo *bo = NULL;
  75
  76     if (_buf->vtbl == &radeon_bo_vtbl) {
  77         bo = radeon_bo(_buf);
  78     } else {
  79         struct pb_buffer *base_buf;
  80         pb_size offset;
  81         pb_get_base_buffer(_buf, &base_buf, &offset);
  82
  83         if (base_buf->vtbl == &radeon_bo_vtbl)
  84             bo = radeon_bo(base_buf);
  85     }
  86
  87     return bo;
  88 }
  89
  90 static void radeon_bo_wait(struct pb_buffer *_buf)
  91 {
  92     struct radeon_bo *bo = get_radeon_bo(_buf);
  93     struct drm_radeon_gem_wait_idle args = {};
  94
  95     while (p_atomic_read(&bo->num_active_ioctls)) {
  96         sched_yield();
  97     }
  98
  99     args.handle = bo->handle;
 100     while (drmCommandWriteRead(bo->rws->fd, DRM_RADEON_GEM_WAIT_IDLE,
 101                                &args, sizeof(args)) == -EBUSY);
 102
 103     bo->busy_for_write = FALSE;
 104 }
 105
 106 static boolean radeon_bo_is_busy(struct pb_buffer *_buf)
 107 {
 108     struct radeon_bo *bo = get_radeon_bo(_buf);
 109     struct drm_radeon_gem_busy args = {};
 110     boolean busy;
 111
 112     if (p_atomic_read(&bo->num_active_ioctls)) {
 113         return TRUE;
 114     }
 115
 116     args.handle = bo->handle;
 117     busy = drmCommandWriteRead(bo->rws->fd, DRM_RADEON_GEM_BUSY,
 118                                &args, sizeof(args)) != 0;
 119
 120     if (!busy)
 121         bo->busy_for_write = FALSE;
 122     return busy;
 123 }
 124
 125 static void radeon_bo_destroy(struct pb_buffer *_buf)
 126 {
 127     struct radeon_bo *bo = radeon_bo(_buf);
 128     struct drm_gem_close args = {};
 129
 130     if (bo->name) {
 131         pipe_mutex_lock(bo->mgr->bo_handles_mutex);
 132         util_hash_table_remove(bo->mgr->bo_handles,
 133                                (void*)(uintptr_t)bo->name);
 134         pipe_mutex_unlock(bo->mgr->bo_handles_mutex);
 135     }
 136
 137     if (bo->ptr)
 138         munmap(bo->ptr, bo->size);
 139
 140     /* Close object. */
 141     args.handle = bo->handle;
 142     drmIoctl(bo->rws->fd, DRM_IOCTL_GEM_CLOSE, &args);
 143     pipe_mutex_destroy(bo->map_mutex);
 144     FREE(bo);
 145 }
 146
 147 static unsigned get_pb_usage_from_transfer_flags(enum pipe_transfer_usage usage)
 148 {
 149     unsigned res = 0;
 150
 151     if (usage & PIPE_TRANSFER_WRITE)
 152         res |= PB_USAGE_CPU_WRITE;
 153
 154     if (usage & PIPE_TRANSFER_DONTBLOCK)
 155         res |= PB_USAGE_DONTBLOCK;
 156
 157     if (usage & PIPE_TRANSFER_UNSYNCHRONIZED)
 158         res |= PB_USAGE_UNSYNCHRONIZED;
 159
 160     return res;
 161 }
 162
 163 static void *radeon_bo_map_internal(struct pb_buffer *_buf,
 164                                     unsigned flags, void *flush_ctx)
 165 {
 166     struct radeon_bo *bo = radeon_bo(_buf);
 167     struct radeon_drm_cs *cs = flush_ctx;
 168     struct drm_radeon_gem_mmap args = {};
 169     void *ptr;
 170
 171     /* If it's not unsynchronized bo_map, flush CS if needed and then wait. */
 172     if (!(flags & PB_USAGE_UNSYNCHRONIZED)) {
 173         /* DONTBLOCK doesn't make sense with UNSYNCHRONIZED. */
 174         if (flags & PB_USAGE_DONTBLOCK) {
 175             if (radeon_bo_is_referenced_by_cs(cs, bo)) {
 176                 cs->flush_cs(cs->flush_data, RADEON_FLUSH_ASYNC);
 177                 return NULL;
 178             }
 179
 180             if (radeon_bo_is_busy((struct pb_buffer*)bo)) {
 181                 return NULL;
 182             }
 183         } else {
 184             if (!(flags & PB_USAGE_CPU_WRITE)) {
 185                 /* Mapping for read.
 186                  *
 187                  * Since we are mapping for read, we don't need to wait
 188                  * if the GPU is using the buffer for read too
 189                  * (neither one is changing it).
 190                  *
 191                  * Only check whether the buffer is being used for write. */
 192                 if (radeon_bo_is_referenced_by_cs_for_write(cs, bo)) {
 193                     cs->flush_cs(cs->flush_data, 0);
 194                     radeon_bo_wait((struct pb_buffer*)bo);
 195                 } else {
 196                     /* XXX We could check whether the buffer is busy for write here. */
 197                     radeon_bo_wait((struct pb_buffer*)bo);
 198                 }
 199 #if 0
 200                 /* XXX This per-winsys busy-for-write tracking sucks.
 201                  * What if some other process wrote something, e.g. using
 202                  * DRI2CopyRegion? We wouldn't get the busy_for_write flag
 203                  * set, skipping bo_wait.
 204                  * We need to move the is-busy-for-write query into the kernel.
 205                  */
 206                 } else if (bo->busy_for_write) {
 207                     /* Update the busy_for_write field (done by radeon_bo_is_busy)
 208                      * and wait if needed. */
 209                     if (radeon_bo_is_busy((struct pb_buffer*)bo)) {
 210                         radeon_bo_wait((struct pb_buffer*)bo);
 211                     }
 212                 }
 213 #endif
 214             } else {
 215                 /* Mapping for write. */
 216                 if (radeon_bo_is_referenced_by_cs(cs, bo)) {
 217                     cs->flush_cs(cs->flush_data, 0);
 218                 } else {
 219                     /* Try to avoid busy-waiting in radeon_bo_wait. */
 220                     if (p_atomic_read(&bo->num_active_ioctls))
 221                         radeon_drm_cs_sync_flush(cs);
 222                 }
 223
 224                 radeon_bo_wait((struct pb_buffer*)bo);
 225             }
 226         }
 227     }
 228
 229     /* Return the pointer if it's already mapped. */
 230     if (bo->ptr)
 231         return bo->ptr;
 232
 233     /* Map the buffer. */
 234     pipe_mutex_lock(bo->map_mutex);
 235     /* Return the pointer if it's already mapped (in case of a race). */
 236     if (bo->ptr) {
 237         pipe_mutex_unlock(bo->map_mutex);
 238         return bo->ptr;
 239     }
 240     args.handle = bo->handle;
 241     args.offset = 0;
 242     args.size = (uint64_t)bo->size;
 243     if (drmCommandWriteRead(bo->rws->fd,
 244                             DRM_RADEON_GEM_MMAP,
 245                             &args,
 246                             sizeof(args))) {
 247         pipe_mutex_unlock(bo->map_mutex);
 248         fprintf(stderr, "radeon: gem_mmap failed: %p 0x%08X\n",
 249                 bo, bo->handle);
 250         return NULL;
 251     }
 252
 253     ptr = mmap(0, args.size, PROT_READ|PROT_WRITE, MAP_SHARED,
 254                bo->rws->fd, args.addr_ptr);
 255     if (ptr == MAP_FAILED) {
 256         pipe_mutex_unlock(bo->map_mutex);
 257         fprintf(stderr, "radeon: mmap failed, errno: %i\n", errno);
 258         return NULL;
 259     }
 260     bo->ptr = ptr;
 261     pipe_mutex_unlock(bo->map_mutex);
 262
 263     return bo->ptr;
 264 }
 265
 266 static void radeon_bo_unmap_internal(struct pb_buffer *_buf)
 267 {
 268     /* NOP */
 269 }
 270
 271 static void radeon_bo_get_base_buffer(struct pb_buffer *buf,
 272                                       struct pb_buffer **base_buf,
 273                                       unsigned *offset)
 274 {
 275     *base_buf = buf;
 276     *offset = 0;
 277 }
 278
 279 static enum pipe_error radeon_bo_validate(struct pb_buffer *_buf,
 280                                           struct pb_validate *vl,
 281                                           unsigned flags)
 282 {
 283     /* Always pinned */
 284     return PIPE_OK;
 285 }
 286
 287 static void radeon_bo_fence(struct pb_buffer *buf,
 288                             struct pipe_fence_handle *fence)
 289 {
 290 }
 291
 292 const struct pb_vtbl radeon_bo_vtbl = {
 293     radeon_bo_destroy,
 294     radeon_bo_map_internal,
 295     radeon_bo_unmap_internal,
 296     radeon_bo_validate,
 297     radeon_bo_fence,
 298     radeon_bo_get_base_buffer,
 299 };
 300
 301 static struct pb_buffer *radeon_bomgr_create_bo(struct pb_manager *_mgr,
 302                                                 pb_size size,
 303                                                 const struct pb_desc *desc)
 304 {
 305     struct radeon_bomgr *mgr = radeon_bomgr(_mgr);
 306     struct radeon_drm_winsys *rws = mgr->rws;
 307     struct radeon_bo *bo;
 308     struct drm_radeon_gem_create args = {};
 309
 310     args.size = size;
 311     args.alignment = desc->alignment;
 312     args.initial_domain =
 313         (desc->usage & RADEON_PB_USAGE_DOMAIN_GTT  ?
 314          RADEON_GEM_DOMAIN_GTT  : 0) |
 315         (desc->usage & RADEON_PB_USAGE_DOMAIN_VRAM ?
 316          RADEON_GEM_DOMAIN_VRAM : 0);
 317
 318     if (drmCommandWriteRead(rws->fd, DRM_RADEON_GEM_CREATE,
 319                             &args, sizeof(args))) {
 320         fprintf(stderr, "radeon: Failed to allocate a buffer:\n");
 321         fprintf(stderr, "radeon:    size      : %d bytes\n", size);
 322         fprintf(stderr, "radeon:    alignment : %d bytes\n", desc->alignment);
 323         fprintf(stderr, "radeon:    domains   : %d\n", args.initial_domain);
 324         return NULL;
 325     }
 326
 327     bo = CALLOC_STRUCT(radeon_bo);
 328     if (!bo)
 329         return NULL;
 330
 331     pipe_reference_init(&bo->base.base.reference, 1);
 332     bo->base.base.alignment = desc->alignment;
 333     bo->base.base.usage = desc->usage;
 334     bo->base.base.size = size;
 335     bo->base.vtbl = &radeon_bo_vtbl;
 336     bo->mgr = mgr;
 337     bo->rws = mgr->rws;
 338     bo->handle = args.handle;
 339     bo->size = size;
 340     pipe_mutex_init(bo->map_mutex);
 341
 342     return &bo->base;
 343 }
 344
 345 static void radeon_bomgr_flush(struct pb_manager *mgr)
 346 {
 347     /* NOP */
 348 }
 349
 350 /* This is for the cache bufmgr. */
 351 static boolean radeon_bomgr_is_buffer_busy(struct pb_manager *_mgr,
 352                                            struct pb_buffer *_buf)
 353 {
 354    struct radeon_bo *bo = radeon_bo(_buf);
 355
 356    if (radeon_bo_is_referenced_by_any_cs(bo)) {
 357        return TRUE;
 358    }
 359
 360    if (radeon_bo_is_busy((struct pb_buffer*)bo)) {
 361        return TRUE;
 362    }
 363
 364    return FALSE;
 365 }
 366
 367 static void radeon_bomgr_destroy(struct pb_manager *_mgr)
 368 {
 369     struct radeon_bomgr *mgr = radeon_bomgr(_mgr);
 370     util_hash_table_destroy(mgr->bo_handles);
 371     pipe_mutex_destroy(mgr->bo_handles_mutex);
 372     FREE(mgr);
 373 }
 374
 375 #define PTR_TO_UINT(x) ((unsigned)((intptr_t)(x)))
 376
 377 static unsigned handle_hash(void *key)
 378 {
 379     return PTR_TO_UINT(key);
 380 }
 381
 382 static int handle_compare(void *key1, void *key2)
 383 {
 384     return PTR_TO_UINT(key1) != PTR_TO_UINT(key2);
 385 }
 386
 387 struct pb_manager *radeon_bomgr_create(struct radeon_drm_winsys *rws)
 388 {
 389     struct radeon_bomgr *mgr;
 390
 391     mgr = CALLOC_STRUCT(radeon_bomgr);
 392     if (!mgr)
 393         return NULL;
 394
 395     mgr->base.destroy = radeon_bomgr_destroy;
 396     mgr->base.create_buffer = radeon_bomgr_create_bo;
 397     mgr->base.flush = radeon_bomgr_flush;
 398     mgr->base.is_buffer_busy = radeon_bomgr_is_buffer_busy;
 399
 400     mgr->rws = rws;
 401     mgr->bo_handles = util_hash_table_create(handle_hash, handle_compare);
 402     pipe_mutex_init(mgr->bo_handles_mutex);
 403     return &mgr->base;
 404 }
 405
 406 static void *radeon_bo_map(struct pb_buffer *buf,
 407                            struct radeon_winsys_cs *cs,
 408                            enum pipe_transfer_usage usage)
 409 {
 410     return pb_map(buf, get_pb_usage_from_transfer_flags(usage), cs);
 411 }
 412
 413 static void radeon_bo_get_tiling(struct pb_buffer *_buf,
 414                                  enum radeon_bo_layout *microtiled,
 415                                  enum radeon_bo_layout *macrotiled)
 416 {
 417     struct radeon_bo *bo = get_radeon_bo(_buf);
 418     struct drm_radeon_gem_set_tiling args = {};
 419
 420     args.handle = bo->handle;
 421
 422     drmCommandWriteRead(bo->rws->fd,
 423                         DRM_RADEON_GEM_GET_TILING,
 424                         &args,
 425                         sizeof(args));
 426
 427     *microtiled = RADEON_LAYOUT_LINEAR;
 428     *macrotiled = RADEON_LAYOUT_LINEAR;
 429     if (args.tiling_flags & RADEON_BO_FLAGS_MICRO_TILE)
 430         *microtiled = RADEON_LAYOUT_TILED;
 431
 432     if (args.tiling_flags & RADEON_BO_FLAGS_MACRO_TILE)
 433         *macrotiled = RADEON_LAYOUT_TILED;
 434 }
 435
 436 static void radeon_bo_set_tiling(struct pb_buffer *_buf,
 437                                  struct radeon_winsys_cs *rcs,
 438                                  enum radeon_bo_layout microtiled,
 439                                  enum radeon_bo_layout macrotiled,
 440                                  uint32_t pitch)
 441 {
 442     struct radeon_bo *bo = get_radeon_bo(_buf);
 443     struct radeon_drm_cs *cs = radeon_drm_cs(rcs);
 444     struct drm_radeon_gem_set_tiling args = {};
 445
 446     /* Tiling determines how DRM treats the buffer data.
 447      * We must flush CS when changing it if the buffer is referenced. */
 448     if (cs && radeon_bo_is_referenced_by_cs(cs, bo)) {
 449         cs->flush_cs(cs->flush_data, 0);
 450     }
 451
 452     while (p_atomic_read(&bo->num_active_ioctls)) {
 453         sched_yield();
 454     }
 455
 456     if (microtiled == RADEON_LAYOUT_TILED)
 457         args.tiling_flags |= RADEON_BO_FLAGS_MICRO_TILE;
 458     else if (microtiled == RADEON_LAYOUT_SQUARETILED)
 459         args.tiling_flags |= RADEON_BO_FLAGS_MICRO_TILE_SQUARE;
 460
 461     if (macrotiled == RADEON_LAYOUT_TILED)
 462         args.tiling_flags |= RADEON_BO_FLAGS_MACRO_TILE;
 463
 464     args.handle = bo->handle;
 465     args.pitch = pitch;
 466
 467     drmCommandWriteRead(bo->rws->fd,
 468                         DRM_RADEON_GEM_SET_TILING,
 469                         &args,
 470                         sizeof(args));
 471 }
 472
 473 static struct radeon_winsys_cs_handle *radeon_drm_get_cs_handle(
 474         struct pb_buffer *_buf)
 475 {
 476     /* return radeon_bo. */
 477     return (struct radeon_winsys_cs_handle*)get_radeon_bo(_buf);
 478 }
 479
 480 static unsigned get_pb_usage_from_create_flags(enum radeon_bo_domain domain)
 481 {
 482     unsigned res = 0;
 483
 484     if (domain & RADEON_DOMAIN_GTT)
 485         res |= RADEON_PB_USAGE_DOMAIN_GTT;
 486
 487     if (domain & RADEON_DOMAIN_VRAM)
 488         res |= RADEON_PB_USAGE_DOMAIN_VRAM;
 489
 490     return res;
 491 }
 492
 493 static struct pb_buffer *
 494 radeon_winsys_bo_create(struct radeon_winsys *rws,
 495                         unsigned size,
 496                         unsigned alignment,
 497                         unsigned bind,
 498                         enum radeon_bo_domain domain)
 499 {
 500     struct radeon_drm_winsys *ws = radeon_drm_winsys(rws);
 501     struct pb_desc desc;
 502     struct pb_manager *provider;
 503     struct pb_buffer *buffer;
 504
 505     memset(&desc, 0, sizeof(desc));
 506     desc.alignment = alignment;
 507     desc.usage = get_pb_usage_from_create_flags(domain);
 508
 509     /* Assign a buffer manager. */
 510     if (bind & (PIPE_BIND_VERTEX_BUFFER | PIPE_BIND_INDEX_BUFFER |
 511                 PIPE_BIND_CONSTANT_BUFFER))
 512         provider = ws->cman;
 513     else
 514         provider = ws->kman;
 515
 516     buffer = provider->create_buffer(provider, size, &desc);
 517     if (!buffer)
 518         return NULL;
 519
 520     return (struct pb_buffer*)buffer;
 521 }
 522
 523 static struct pb_buffer *radeon_winsys_bo_from_handle(struct radeon_winsys *rws,
 524                                                            struct winsys_handle *whandle,
 525                                                            unsigned *stride,
 526                                                            unsigned *size)
 527 {
 528     struct radeon_drm_winsys *ws = radeon_drm_winsys(rws);
 529     struct radeon_bo *bo;
 530     struct radeon_bomgr *mgr = radeon_bomgr(ws->kman);
 531     struct drm_gem_open open_arg = {};
 532
 533     /* We must maintain a list of pairs <handle, bo>, so that we always return
 534      * the same BO for one particular handle. If we didn't do that and created
 535      * more than one BO for the same handle and then relocated them in a CS,
 536      * we would hit a deadlock in the kernel.
 537      *
 538      * The list of pairs is guarded by a mutex, of course. */
 539     pipe_mutex_lock(mgr->bo_handles_mutex);
 540
 541     /* First check if there already is an existing bo for the handle. */
 542     bo = util_hash_table_get(mgr->bo_handles, (void*)(uintptr_t)whandle->handle);
 543     if (bo) {
 544         /* Increase the refcount. */
 545         struct pb_buffer *b = NULL;
 546         pb_reference(&b, &bo->base);
 547         goto done;
 548     }
 549
 550     /* There isn't, create a new one. */
 551     bo = CALLOC_STRUCT(radeon_bo);
 552     if (!bo) {
 553         goto fail;
 554     }
 555
 556     /* Open the BO. */
 557     open_arg.name = whandle->handle;
 558     if (drmIoctl(ws->fd, DRM_IOCTL_GEM_OPEN, &open_arg)) {
 559         FREE(bo);
 560         goto fail;
 561     }
 562     bo->handle = open_arg.handle;
 563     bo->size = open_arg.size;
 564     bo->name = whandle->handle;
 565
 566     /* Initialize it. */
 567     pipe_reference_init(&bo->base.base.reference, 1);
 568     bo->base.base.alignment = 0;
 569     bo->base.base.usage = PB_USAGE_GPU_WRITE | PB_USAGE_GPU_READ;
 570     bo->base.base.size = bo->size;
 571     bo->base.vtbl = &radeon_bo_vtbl;
 572     bo->mgr = mgr;
 573     bo->rws = mgr->rws;
 574     pipe_mutex_init(bo->map_mutex);
 575
 576     util_hash_table_set(mgr->bo_handles, (void*)(uintptr_t)whandle->handle, bo);
 577
 578 done:
 579     pipe_mutex_unlock(mgr->bo_handles_mutex);
 580
 581     if (stride)
 582         *stride = whandle->stride;
 583     if (size)
 584         *size = bo->base.base.size;
 585
 586     return (struct pb_buffer*)bo;
 587
 588 fail:
 589     pipe_mutex_unlock(mgr->bo_handles_mutex);
 590     return NULL;
 591 }
 592
 593 static boolean radeon_winsys_bo_get_handle(struct pb_buffer *buffer,
 594                                            unsigned stride,
 595                                            struct winsys_handle *whandle)
 596 {
 597     struct drm_gem_flink flink = {};
 598     struct radeon_bo *bo = get_radeon_bo(buffer);
 599
 600     if (whandle->type == DRM_API_HANDLE_TYPE_SHARED) {
 601         if (!bo->flinked) {
 602             flink.handle = bo->handle;
 603
 604             if (ioctl(bo->rws->fd, DRM_IOCTL_GEM_FLINK, &flink)) {
 605                 return FALSE;
 606             }
 607
 608             bo->flinked = TRUE;
 609             bo->flink = flink.name;
 610         }
 611         whandle->handle = bo->flink;
 612     } else if (whandle->type == DRM_API_HANDLE_TYPE_KMS) {
 613         whandle->handle = bo->handle;
 614     }
 615
 616     whandle->stride = stride;
 617     return TRUE;
 618 }
 619
 620 void radeon_bomgr_init_functions(struct radeon_drm_winsys *ws)
 621 {
 622     ws->base.buffer_get_cs_handle = radeon_drm_get_cs_handle;
 623     ws->base.buffer_set_tiling = radeon_bo_set_tiling;
 624     ws->base.buffer_get_tiling = radeon_bo_get_tiling;
 625     ws->base.buffer_map = radeon_bo_map;
 626     ws->base.buffer_unmap = pb_unmap;
 627     ws->base.buffer_wait = radeon_bo_wait;
 628     ws->base.buffer_is_busy = radeon_bo_is_busy;
 629     ws->base.buffer_create = radeon_winsys_bo_create;
 630     ws->base.buffer_from_handle = radeon_winsys_bo_from_handle;
 631     ws->base.buffer_get_handle = radeon_winsys_bo_get_handle;
 632 }