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[mesa.git] / src / gallium / winsys / radeon / drm / radeon_drm_bo.c
1 /*
2 * Copyright © 2011 Marek Olšák <maraeo@gmail.com>
3 * All Rights Reserved.
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining
6 * a copy of this software and associated documentation files (the
7 * "Software"), to deal in the Software without restriction, including
8 * without limitation the rights to use, copy, modify, merge, publish,
9 * distribute, sub license, and/or sell copies of the Software, and to
10 * permit persons to whom the Software is furnished to do so, subject to
11 * the following conditions:
12 *
13 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
14 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
15 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
16 * NON-INFRINGEMENT. IN NO EVENT SHALL THE COPYRIGHT HOLDERS, AUTHORS
17 * AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
18 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
20 * USE OR OTHER DEALINGS IN THE SOFTWARE.
21 *
22 * The above copyright notice and this permission notice (including the
23 * next paragraph) shall be included in all copies or substantial portions
24 * of the Software.
25 */
26
27 #define _FILE_OFFSET_BITS 64
28 #include "radeon_drm_cs.h"
29
30 #include "util/u_hash_table.h"
31 #include "util/u_memory.h"
32 #include "util/u_simple_list.h"
33 #include "util/u_double_list.h"
34 #include "os/os_thread.h"
35 #include "os/os_mman.h"
36 #include "os/os_time.h"
37
38 #include "state_tracker/drm_driver.h"
39
40 #include <sys/ioctl.h>
41 #include <xf86drm.h>
42 #include <errno.h>
43
44 /*
45 * this are copy from radeon_drm, once an updated libdrm is released
46 * we should bump configure.ac requirement for it and remove the following
47 * field
48 */
49 #define RADEON_BO_FLAGS_MACRO_TILE 1
50 #define RADEON_BO_FLAGS_MICRO_TILE 2
51 #define RADEON_BO_FLAGS_MICRO_TILE_SQUARE 0x20
52
53 #ifndef DRM_RADEON_GEM_WAIT
54 #define DRM_RADEON_GEM_WAIT 0x2b
55
56 #define RADEON_GEM_NO_WAIT 0x1
57 #define RADEON_GEM_USAGE_READ 0x2
58 #define RADEON_GEM_USAGE_WRITE 0x4
59
60 struct drm_radeon_gem_wait {
61 uint32_t handle;
62 uint32_t flags; /* one of RADEON_GEM_* */
63 };
64
65 #endif
66
67 #ifndef RADEON_VA_MAP
68
69 #define RADEON_VA_MAP 1
70 #define RADEON_VA_UNMAP 2
71
72 #define RADEON_VA_RESULT_OK 0
73 #define RADEON_VA_RESULT_ERROR 1
74 #define RADEON_VA_RESULT_VA_EXIST 2
75
76 #define RADEON_VM_PAGE_VALID (1 << 0)
77 #define RADEON_VM_PAGE_READABLE (1 << 1)
78 #define RADEON_VM_PAGE_WRITEABLE (1 << 2)
79 #define RADEON_VM_PAGE_SYSTEM (1 << 3)
80 #define RADEON_VM_PAGE_SNOOPED (1 << 4)
81
82 struct drm_radeon_gem_va {
83 uint32_t handle;
84 uint32_t operation;
85 uint32_t vm_id;
86 uint32_t flags;
87 uint64_t offset;
88 };
89
90 #define DRM_RADEON_GEM_VA 0x2b
91 #endif
92
93
94
95 extern const struct pb_vtbl radeon_bo_vtbl;
96
97
98 static INLINE struct radeon_bo *radeon_bo(struct pb_buffer *bo)
99 {
100 assert(bo->vtbl == &radeon_bo_vtbl);
101 return (struct radeon_bo *)bo;
102 }
103
104 struct radeon_bo_va_hole {
105 struct list_head list;
106 uint64_t offset;
107 uint64_t size;
108 };
109
110 struct radeon_bomgr {
111 /* Base class. */
112 struct pb_manager base;
113
114 /* Winsys. */
115 struct radeon_drm_winsys *rws;
116
117 /* List of buffer handles and its mutex. */
118 struct util_hash_table *bo_handles;
119 pipe_mutex bo_handles_mutex;
120 pipe_mutex bo_va_mutex;
121
122 /* is virtual address supported */
123 bool va;
124 uint64_t va_offset;
125 struct list_head va_holes;
126 };
127
128 static INLINE struct radeon_bomgr *radeon_bomgr(struct pb_manager *mgr)
129 {
130 return (struct radeon_bomgr *)mgr;
131 }
132
133 static struct radeon_bo *get_radeon_bo(struct pb_buffer *_buf)
134 {
135 struct radeon_bo *bo = NULL;
136
137 if (_buf->vtbl == &radeon_bo_vtbl) {
138 bo = radeon_bo(_buf);
139 } else {
140 struct pb_buffer *base_buf;
141 pb_size offset;
142 pb_get_base_buffer(_buf, &base_buf, &offset);
143
144 if (base_buf->vtbl == &radeon_bo_vtbl)
145 bo = radeon_bo(base_buf);
146 }
147
148 return bo;
149 }
150
151 static void radeon_bo_wait(struct pb_buffer *_buf, enum radeon_bo_usage usage)
152 {
153 struct radeon_bo *bo = get_radeon_bo(_buf);
154
155 while (p_atomic_read(&bo->num_active_ioctls)) {
156 sched_yield();
157 }
158
159 /* XXX use this when it's ready */
160 /*if (bo->rws->info.drm_minor >= 12) {
161 struct drm_radeon_gem_wait args = {};
162 args.handle = bo->handle;
163 args.flags = usage;
164 while (drmCommandWriteRead(bo->rws->fd, DRM_RADEON_GEM_WAIT,
165 &args, sizeof(args)) == -EBUSY);
166 } else*/ {
167 struct drm_radeon_gem_wait_idle args;
168 memset(&args, 0, sizeof(args));
169 args.handle = bo->handle;
170 while (drmCommandWrite(bo->rws->fd, DRM_RADEON_GEM_WAIT_IDLE,
171 &args, sizeof(args)) == -EBUSY);
172 }
173 }
174
175 static boolean radeon_bo_is_busy(struct pb_buffer *_buf,
176 enum radeon_bo_usage usage)
177 {
178 struct radeon_bo *bo = get_radeon_bo(_buf);
179
180 if (p_atomic_read(&bo->num_active_ioctls)) {
181 return TRUE;
182 }
183
184 /* XXX use this when it's ready */
185 /*if (bo->rws->info.drm_minor >= 12) {
186 struct drm_radeon_gem_wait args = {};
187 args.handle = bo->handle;
188 args.flags = usage | RADEON_GEM_NO_WAIT;
189 return drmCommandWriteRead(bo->rws->fd, DRM_RADEON_GEM_WAIT,
190 &args, sizeof(args)) != 0;
191 } else*/ {
192 struct drm_radeon_gem_busy args;
193 memset(&args, 0, sizeof(args));
194 args.handle = bo->handle;
195 return drmCommandWriteRead(bo->rws->fd, DRM_RADEON_GEM_BUSY,
196 &args, sizeof(args)) != 0;
197 }
198 }
199
200 static uint64_t radeon_bomgr_find_va(struct radeon_bomgr *mgr, uint64_t size, uint64_t alignment)
201 {
202 struct radeon_bo_va_hole *hole, *n;
203 uint64_t offset = 0, waste = 0;
204
205 alignment = MAX2(alignment, 4096);
206 size = align(size, 4096);
207
208 pipe_mutex_lock(mgr->bo_va_mutex);
209 /* first look for a hole */
210 LIST_FOR_EACH_ENTRY_SAFE(hole, n, &mgr->va_holes, list) {
211 offset = hole->offset;
212 waste = offset % alignment;
213 waste = waste ? alignment - waste : 0;
214 offset += waste;
215 if (offset >= (hole->offset + hole->size)) {
216 continue;
217 }
218 if (!waste && hole->size == size) {
219 offset = hole->offset;
220 list_del(&hole->list);
221 FREE(hole);
222 pipe_mutex_unlock(mgr->bo_va_mutex);
223 return offset;
224 }
225 if ((hole->size - waste) > size) {
226 if (waste) {
227 n = CALLOC_STRUCT(radeon_bo_va_hole);
228 n->size = waste;
229 n->offset = hole->offset;
230 list_add(&n->list, &hole->list);
231 }
232 hole->size -= (size + waste);
233 hole->offset += size + waste;
234 pipe_mutex_unlock(mgr->bo_va_mutex);
235 return offset;
236 }
237 if ((hole->size - waste) == size) {
238 hole->size = waste;
239 pipe_mutex_unlock(mgr->bo_va_mutex);
240 return offset;
241 }
242 }
243
244 offset = mgr->va_offset;
245 waste = offset % alignment;
246 waste = waste ? alignment - waste : 0;
247 if (waste) {
248 n = CALLOC_STRUCT(radeon_bo_va_hole);
249 n->size = waste;
250 n->offset = offset;
251 list_add(&n->list, &mgr->va_holes);
252 }
253 offset += waste;
254 mgr->va_offset += size + waste;
255 pipe_mutex_unlock(mgr->bo_va_mutex);
256 return offset;
257 }
258
259 static void radeon_bomgr_force_va(struct radeon_bomgr *mgr, uint64_t va, uint64_t size)
260 {
261 size = align(size, 4096);
262
263 pipe_mutex_lock(mgr->bo_va_mutex);
264 if (va >= mgr->va_offset) {
265 if (va > mgr->va_offset) {
266 struct radeon_bo_va_hole *hole;
267 hole = CALLOC_STRUCT(radeon_bo_va_hole);
268 if (hole) {
269 hole->size = va - mgr->va_offset;
270 hole->offset = mgr->va_offset;
271 list_add(&hole->list, &mgr->va_holes);
272 }
273 }
274 mgr->va_offset = va + size;
275 } else {
276 struct radeon_bo_va_hole *hole, *n;
277 uint64_t hole_end, va_end;
278
279 /* Prune/free all holes that fall into the range
280 */
281 LIST_FOR_EACH_ENTRY_SAFE(hole, n, &mgr->va_holes, list) {
282 hole_end = hole->offset + hole->size;
283 va_end = va + size;
284 if (hole->offset >= va_end || hole_end <= va)
285 continue;
286 if (hole->offset >= va && hole_end <= va_end) {
287 list_del(&hole->list);
288 FREE(hole);
289 continue;
290 }
291 if (hole->offset >= va)
292 hole->offset = va_end;
293 else
294 hole_end = va;
295 hole->size = hole_end - hole->offset;
296 }
297 }
298 pipe_mutex_unlock(mgr->bo_va_mutex);
299 }
300
301 static void radeon_bomgr_free_va(struct radeon_bomgr *mgr, uint64_t va, uint64_t size)
302 {
303 struct radeon_bo_va_hole *hole;
304
305 size = align(size, 4096);
306
307 pipe_mutex_lock(mgr->bo_va_mutex);
308 if ((va + size) == mgr->va_offset) {
309 mgr->va_offset = va;
310 /* Delete uppermost hole if it reaches the new top */
311 if (!LIST_IS_EMPTY(&mgr->va_holes)) {
312 hole = container_of(mgr->va_holes.next, hole, list);
313 if ((hole->offset + hole->size) == va) {
314 mgr->va_offset = hole->offset;
315 list_del(&hole->list);
316 FREE(hole);
317 }
318 }
319 } else {
320 struct radeon_bo_va_hole *next;
321
322 hole = container_of(&mgr->va_holes, hole, list);
323 LIST_FOR_EACH_ENTRY(next, &mgr->va_holes, list) {
324 if (next->offset < va)
325 break;
326 hole = next;
327 }
328
329 if (&hole->list != &mgr->va_holes) {
330 /* Grow upper hole if it's adjacent */
331 if (hole->offset == (va + size)) {
332 hole->offset = va;
333 hole->size += size;
334 /* Merge lower hole if it's adjacent */
335 if (next != hole && &next->list != &mgr->va_holes &&
336 (next->offset + next->size) == va) {
337 next->size += hole->size;
338 list_del(&hole->list);
339 FREE(hole);
340 }
341 goto out;
342 }
343 }
344
345 /* Grow lower hole if it's adjacent */
346 if (next != hole && &next->list != &mgr->va_holes &&
347 (next->offset + next->size) == va) {
348 next->size += size;
349 goto out;
350 }
351
352 /* FIXME on allocation failure we just lose virtual address space
353 * maybe print a warning
354 */
355 next = CALLOC_STRUCT(radeon_bo_va_hole);
356 if (next) {
357 next->size = size;
358 next->offset = va;
359 list_add(&next->list, &hole->list);
360 }
361 }
362 out:
363 pipe_mutex_unlock(mgr->bo_va_mutex);
364 }
365
366 static void radeon_bo_destroy(struct pb_buffer *_buf)
367 {
368 struct radeon_bo *bo = radeon_bo(_buf);
369 struct radeon_bomgr *mgr = bo->mgr;
370 struct drm_gem_close args;
371
372 memset(&args, 0, sizeof(args));
373
374 if (bo->name) {
375 pipe_mutex_lock(bo->mgr->bo_handles_mutex);
376 util_hash_table_remove(bo->mgr->bo_handles,
377 (void*)(uintptr_t)bo->name);
378 pipe_mutex_unlock(bo->mgr->bo_handles_mutex);
379 }
380
381 if (bo->ptr)
382 os_munmap(bo->ptr, bo->base.size);
383
384 /* Close object. */
385 args.handle = bo->handle;
386 drmIoctl(bo->rws->fd, DRM_IOCTL_GEM_CLOSE, &args);
387
388 if (mgr->va) {
389 radeon_bomgr_free_va(mgr, bo->va, bo->base.size);
390 }
391
392 pipe_mutex_destroy(bo->map_mutex);
393
394 if (bo->initial_domain & RADEON_DOMAIN_VRAM)
395 bo->rws->allocated_vram -= align(bo->base.size, 4096);
396 else if (bo->initial_domain & RADEON_DOMAIN_GTT)
397 bo->rws->allocated_gtt -= align(bo->base.size, 4096);
398 FREE(bo);
399 }
400
401 void *radeon_bo_do_map(struct radeon_bo *bo)
402 {
403 struct drm_radeon_gem_mmap args = {0};
404 void *ptr;
405
406 /* Return the pointer if it's already mapped. */
407 if (bo->ptr)
408 return bo->ptr;
409
410 /* Map the buffer. */
411 pipe_mutex_lock(bo->map_mutex);
412 /* Return the pointer if it's already mapped (in case of a race). */
413 if (bo->ptr) {
414 pipe_mutex_unlock(bo->map_mutex);
415 return bo->ptr;
416 }
417 args.handle = bo->handle;
418 args.offset = 0;
419 args.size = (uint64_t)bo->base.size;
420 if (drmCommandWriteRead(bo->rws->fd,
421 DRM_RADEON_GEM_MMAP,
422 &args,
423 sizeof(args))) {
424 pipe_mutex_unlock(bo->map_mutex);
425 fprintf(stderr, "radeon: gem_mmap failed: %p 0x%08X\n",
426 bo, bo->handle);
427 return NULL;
428 }
429
430 ptr = os_mmap(0, args.size, PROT_READ|PROT_WRITE, MAP_SHARED,
431 bo->rws->fd, args.addr_ptr);
432 if (ptr == MAP_FAILED) {
433 pipe_mutex_unlock(bo->map_mutex);
434 fprintf(stderr, "radeon: mmap failed, errno: %i\n", errno);
435 return NULL;
436 }
437 bo->ptr = ptr;
438 pipe_mutex_unlock(bo->map_mutex);
439
440 return bo->ptr;
441 }
442
443 static void *radeon_bo_map(struct radeon_winsys_cs_handle *buf,
444 struct radeon_winsys_cs *rcs,
445 enum pipe_transfer_usage usage)
446 {
447 struct radeon_bo *bo = (struct radeon_bo*)buf;
448 struct radeon_drm_cs *cs = (struct radeon_drm_cs*)rcs;
449
450 /* If it's not unsynchronized bo_map, flush CS if needed and then wait. */
451 if (!(usage & PIPE_TRANSFER_UNSYNCHRONIZED)) {
452 /* DONTBLOCK doesn't make sense with UNSYNCHRONIZED. */
453 if (usage & PIPE_TRANSFER_DONTBLOCK) {
454 if (!(usage & PIPE_TRANSFER_WRITE)) {
455 /* Mapping for read.
456 *
457 * Since we are mapping for read, we don't need to wait
458 * if the GPU is using the buffer for read too
459 * (neither one is changing it).
460 *
461 * Only check whether the buffer is being used for write. */
462 if (cs && radeon_bo_is_referenced_by_cs_for_write(cs, bo)) {
463 cs->flush_cs(cs->flush_data, RADEON_FLUSH_ASYNC);
464 return NULL;
465 }
466
467 if (radeon_bo_is_busy((struct pb_buffer*)bo,
468 RADEON_USAGE_WRITE)) {
469 return NULL;
470 }
471 } else {
472 if (cs && radeon_bo_is_referenced_by_cs(cs, bo)) {
473 cs->flush_cs(cs->flush_data, RADEON_FLUSH_ASYNC);
474 return NULL;
475 }
476
477 if (radeon_bo_is_busy((struct pb_buffer*)bo,
478 RADEON_USAGE_READWRITE)) {
479 return NULL;
480 }
481 }
482 } else {
483 uint64_t time = os_time_get_nano();
484
485 if (!(usage & PIPE_TRANSFER_WRITE)) {
486 /* Mapping for read.
487 *
488 * Since we are mapping for read, we don't need to wait
489 * if the GPU is using the buffer for read too
490 * (neither one is changing it).
491 *
492 * Only check whether the buffer is being used for write. */
493 if (cs && radeon_bo_is_referenced_by_cs_for_write(cs, bo)) {
494 cs->flush_cs(cs->flush_data, 0);
495 }
496 radeon_bo_wait((struct pb_buffer*)bo,
497 RADEON_USAGE_WRITE);
498 } else {
499 /* Mapping for write. */
500 if (cs) {
501 if (radeon_bo_is_referenced_by_cs(cs, bo)) {
502 cs->flush_cs(cs->flush_data, 0);
503 } else {
504 /* Try to avoid busy-waiting in radeon_bo_wait. */
505 if (p_atomic_read(&bo->num_active_ioctls))
506 radeon_drm_cs_sync_flush(rcs);
507 }
508 }
509
510 radeon_bo_wait((struct pb_buffer*)bo, RADEON_USAGE_READWRITE);
511 }
512
513 bo->mgr->rws->buffer_wait_time += os_time_get_nano() - time;
514 }
515 }
516
517 return radeon_bo_do_map(bo);
518 }
519
520 static void radeon_bo_unmap(struct radeon_winsys_cs_handle *_buf)
521 {
522 /* NOP */
523 }
524
525 static void radeon_bo_get_base_buffer(struct pb_buffer *buf,
526 struct pb_buffer **base_buf,
527 unsigned *offset)
528 {
529 *base_buf = buf;
530 *offset = 0;
531 }
532
533 static enum pipe_error radeon_bo_validate(struct pb_buffer *_buf,
534 struct pb_validate *vl,
535 unsigned flags)
536 {
537 /* Always pinned */
538 return PIPE_OK;
539 }
540
541 static void radeon_bo_fence(struct pb_buffer *buf,
542 struct pipe_fence_handle *fence)
543 {
544 }
545
546 const struct pb_vtbl radeon_bo_vtbl = {
547 radeon_bo_destroy,
548 NULL, /* never called */
549 NULL, /* never called */
550 radeon_bo_validate,
551 radeon_bo_fence,
552 radeon_bo_get_base_buffer,
553 };
554
555 static struct pb_buffer *radeon_bomgr_create_bo(struct pb_manager *_mgr,
556 pb_size size,
557 const struct pb_desc *desc)
558 {
559 struct radeon_bomgr *mgr = radeon_bomgr(_mgr);
560 struct radeon_drm_winsys *rws = mgr->rws;
561 struct radeon_bo *bo;
562 struct drm_radeon_gem_create args;
563 struct radeon_bo_desc *rdesc = (struct radeon_bo_desc*)desc;
564 int r;
565
566 memset(&args, 0, sizeof(args));
567
568 assert(rdesc->initial_domains);
569 assert((rdesc->initial_domains &
570 ~(RADEON_GEM_DOMAIN_GTT | RADEON_GEM_DOMAIN_VRAM)) == 0);
571
572 args.size = size;
573 args.alignment = desc->alignment;
574 args.initial_domain = rdesc->initial_domains;
575
576 if (drmCommandWriteRead(rws->fd, DRM_RADEON_GEM_CREATE,
577 &args, sizeof(args))) {
578 fprintf(stderr, "radeon: Failed to allocate a buffer:\n");
579 fprintf(stderr, "radeon: size : %d bytes\n", size);
580 fprintf(stderr, "radeon: alignment : %d bytes\n", desc->alignment);
581 fprintf(stderr, "radeon: domains : %d\n", args.initial_domain);
582 return NULL;
583 }
584
585 bo = CALLOC_STRUCT(radeon_bo);
586 if (!bo)
587 return NULL;
588
589 pipe_reference_init(&bo->base.reference, 1);
590 bo->base.alignment = desc->alignment;
591 bo->base.usage = desc->usage;
592 bo->base.size = size;
593 bo->base.vtbl = &radeon_bo_vtbl;
594 bo->mgr = mgr;
595 bo->rws = mgr->rws;
596 bo->handle = args.handle;
597 bo->va = 0;
598 bo->initial_domain = rdesc->initial_domains;
599 pipe_mutex_init(bo->map_mutex);
600
601 if (mgr->va) {
602 struct drm_radeon_gem_va va;
603
604 bo->va = radeon_bomgr_find_va(mgr, size, desc->alignment);
605
606 va.handle = bo->handle;
607 va.vm_id = 0;
608 va.operation = RADEON_VA_MAP;
609 va.flags = RADEON_VM_PAGE_READABLE |
610 RADEON_VM_PAGE_WRITEABLE |
611 RADEON_VM_PAGE_SNOOPED;
612 va.offset = bo->va;
613 r = drmCommandWriteRead(rws->fd, DRM_RADEON_GEM_VA, &va, sizeof(va));
614 if (r && va.operation == RADEON_VA_RESULT_ERROR) {
615 fprintf(stderr, "radeon: Failed to allocate virtual address for buffer:\n");
616 fprintf(stderr, "radeon: size : %d bytes\n", size);
617 fprintf(stderr, "radeon: alignment : %d bytes\n", desc->alignment);
618 fprintf(stderr, "radeon: domains : %d\n", args.initial_domain);
619 fprintf(stderr, "radeon: va : 0x%016llx\n", (unsigned long long)bo->va);
620 radeon_bo_destroy(&bo->base);
621 return NULL;
622 }
623 if (va.operation == RADEON_VA_RESULT_VA_EXIST) {
624 radeon_bomgr_free_va(mgr, bo->va, size);
625 bo->va = va.offset;
626 radeon_bomgr_force_va(mgr, bo->va, size);
627 }
628 }
629
630 if (rdesc->initial_domains & RADEON_DOMAIN_VRAM)
631 rws->allocated_vram += align(size, 4096);
632 else if (rdesc->initial_domains & RADEON_DOMAIN_GTT)
633 rws->allocated_gtt += align(size, 4096);
634
635 return &bo->base;
636 }
637
638 static void radeon_bomgr_flush(struct pb_manager *mgr)
639 {
640 /* NOP */
641 }
642
643 /* This is for the cache bufmgr. */
644 static boolean radeon_bomgr_is_buffer_busy(struct pb_manager *_mgr,
645 struct pb_buffer *_buf)
646 {
647 struct radeon_bo *bo = radeon_bo(_buf);
648
649 if (radeon_bo_is_referenced_by_any_cs(bo)) {
650 return TRUE;
651 }
652
653 if (radeon_bo_is_busy((struct pb_buffer*)bo, RADEON_USAGE_READWRITE)) {
654 return TRUE;
655 }
656
657 return FALSE;
658 }
659
660 static void radeon_bomgr_destroy(struct pb_manager *_mgr)
661 {
662 struct radeon_bomgr *mgr = radeon_bomgr(_mgr);
663 util_hash_table_destroy(mgr->bo_handles);
664 pipe_mutex_destroy(mgr->bo_handles_mutex);
665 pipe_mutex_destroy(mgr->bo_va_mutex);
666 FREE(mgr);
667 }
668
669 #define PTR_TO_UINT(x) ((unsigned)((intptr_t)(x)))
670
671 static unsigned handle_hash(void *key)
672 {
673 return PTR_TO_UINT(key);
674 }
675
676 static int handle_compare(void *key1, void *key2)
677 {
678 return PTR_TO_UINT(key1) != PTR_TO_UINT(key2);
679 }
680
681 struct pb_manager *radeon_bomgr_create(struct radeon_drm_winsys *rws)
682 {
683 struct radeon_bomgr *mgr;
684
685 mgr = CALLOC_STRUCT(radeon_bomgr);
686 if (!mgr)
687 return NULL;
688
689 mgr->base.destroy = radeon_bomgr_destroy;
690 mgr->base.create_buffer = radeon_bomgr_create_bo;
691 mgr->base.flush = radeon_bomgr_flush;
692 mgr->base.is_buffer_busy = radeon_bomgr_is_buffer_busy;
693
694 mgr->rws = rws;
695 mgr->bo_handles = util_hash_table_create(handle_hash, handle_compare);
696 pipe_mutex_init(mgr->bo_handles_mutex);
697 pipe_mutex_init(mgr->bo_va_mutex);
698
699 mgr->va = rws->info.r600_virtual_address;
700 mgr->va_offset = rws->info.r600_va_start;
701 list_inithead(&mgr->va_holes);
702
703 return &mgr->base;
704 }
705
706 static unsigned eg_tile_split(unsigned tile_split)
707 {
708 switch (tile_split) {
709 case 0: tile_split = 64; break;
710 case 1: tile_split = 128; break;
711 case 2: tile_split = 256; break;
712 case 3: tile_split = 512; break;
713 default:
714 case 4: tile_split = 1024; break;
715 case 5: tile_split = 2048; break;
716 case 6: tile_split = 4096; break;
717 }
718 return tile_split;
719 }
720
721 static unsigned eg_tile_split_rev(unsigned eg_tile_split)
722 {
723 switch (eg_tile_split) {
724 case 64: return 0;
725 case 128: return 1;
726 case 256: return 2;
727 case 512: return 3;
728 default:
729 case 1024: return 4;
730 case 2048: return 5;
731 case 4096: return 6;
732 }
733 }
734
735 static void radeon_bo_get_tiling(struct pb_buffer *_buf,
736 enum radeon_bo_layout *microtiled,
737 enum radeon_bo_layout *macrotiled,
738 unsigned *bankw, unsigned *bankh,
739 unsigned *tile_split,
740 unsigned *stencil_tile_split,
741 unsigned *mtilea)
742 {
743 struct radeon_bo *bo = get_radeon_bo(_buf);
744 struct drm_radeon_gem_set_tiling args;
745
746 memset(&args, 0, sizeof(args));
747
748 args.handle = bo->handle;
749
750 drmCommandWriteRead(bo->rws->fd,
751 DRM_RADEON_GEM_GET_TILING,
752 &args,
753 sizeof(args));
754
755 *microtiled = RADEON_LAYOUT_LINEAR;
756 *macrotiled = RADEON_LAYOUT_LINEAR;
757 if (args.tiling_flags & RADEON_BO_FLAGS_MICRO_TILE)
758 *microtiled = RADEON_LAYOUT_TILED;
759
760 if (args.tiling_flags & RADEON_BO_FLAGS_MACRO_TILE)
761 *macrotiled = RADEON_LAYOUT_TILED;
762 if (bankw && tile_split && stencil_tile_split && mtilea && tile_split) {
763 *bankw = (args.tiling_flags >> RADEON_TILING_EG_BANKW_SHIFT) & RADEON_TILING_EG_BANKW_MASK;
764 *bankh = (args.tiling_flags >> RADEON_TILING_EG_BANKH_SHIFT) & RADEON_TILING_EG_BANKH_MASK;
765 *tile_split = (args.tiling_flags >> RADEON_TILING_EG_TILE_SPLIT_SHIFT) & RADEON_TILING_EG_TILE_SPLIT_MASK;
766 *stencil_tile_split = (args.tiling_flags >> RADEON_TILING_EG_STENCIL_TILE_SPLIT_SHIFT) & RADEON_TILING_EG_STENCIL_TILE_SPLIT_MASK;
767 *mtilea = (args.tiling_flags >> RADEON_TILING_EG_MACRO_TILE_ASPECT_SHIFT) & RADEON_TILING_EG_MACRO_TILE_ASPECT_MASK;
768 *tile_split = eg_tile_split(*tile_split);
769 }
770 }
771
772 static void radeon_bo_set_tiling(struct pb_buffer *_buf,
773 struct radeon_winsys_cs *rcs,
774 enum radeon_bo_layout microtiled,
775 enum radeon_bo_layout macrotiled,
776 unsigned bankw, unsigned bankh,
777 unsigned tile_split,
778 unsigned stencil_tile_split,
779 unsigned mtilea,
780 uint32_t pitch)
781 {
782 struct radeon_bo *bo = get_radeon_bo(_buf);
783 struct radeon_drm_cs *cs = radeon_drm_cs(rcs);
784 struct drm_radeon_gem_set_tiling args;
785
786 memset(&args, 0, sizeof(args));
787
788 /* Tiling determines how DRM treats the buffer data.
789 * We must flush CS when changing it if the buffer is referenced. */
790 if (cs && radeon_bo_is_referenced_by_cs(cs, bo)) {
791 cs->flush_cs(cs->flush_data, 0);
792 }
793
794 while (p_atomic_read(&bo->num_active_ioctls)) {
795 sched_yield();
796 }
797
798 if (microtiled == RADEON_LAYOUT_TILED)
799 args.tiling_flags |= RADEON_BO_FLAGS_MICRO_TILE;
800 else if (microtiled == RADEON_LAYOUT_SQUARETILED)
801 args.tiling_flags |= RADEON_BO_FLAGS_MICRO_TILE_SQUARE;
802
803 if (macrotiled == RADEON_LAYOUT_TILED)
804 args.tiling_flags |= RADEON_BO_FLAGS_MACRO_TILE;
805
806 args.tiling_flags |= (bankw & RADEON_TILING_EG_BANKW_MASK) <<
807 RADEON_TILING_EG_BANKW_SHIFT;
808 args.tiling_flags |= (bankh & RADEON_TILING_EG_BANKH_MASK) <<
809 RADEON_TILING_EG_BANKH_SHIFT;
810 if (tile_split) {
811 args.tiling_flags |= (eg_tile_split_rev(tile_split) &
812 RADEON_TILING_EG_TILE_SPLIT_MASK) <<
813 RADEON_TILING_EG_TILE_SPLIT_SHIFT;
814 }
815 args.tiling_flags |= (stencil_tile_split &
816 RADEON_TILING_EG_STENCIL_TILE_SPLIT_MASK) <<
817 RADEON_TILING_EG_STENCIL_TILE_SPLIT_SHIFT;
818 args.tiling_flags |= (mtilea & RADEON_TILING_EG_MACRO_TILE_ASPECT_MASK) <<
819 RADEON_TILING_EG_MACRO_TILE_ASPECT_SHIFT;
820
821 args.handle = bo->handle;
822 args.pitch = pitch;
823
824 drmCommandWriteRead(bo->rws->fd,
825 DRM_RADEON_GEM_SET_TILING,
826 &args,
827 sizeof(args));
828 }
829
830 static struct radeon_winsys_cs_handle *radeon_drm_get_cs_handle(struct pb_buffer *_buf)
831 {
832 /* return radeon_bo. */
833 return (struct radeon_winsys_cs_handle*)get_radeon_bo(_buf);
834 }
835
836 static struct pb_buffer *
837 radeon_winsys_bo_create(struct radeon_winsys *rws,
838 unsigned size,
839 unsigned alignment,
840 boolean use_reusable_pool,
841 enum radeon_bo_domain domain)
842 {
843 struct radeon_drm_winsys *ws = radeon_drm_winsys(rws);
844 struct radeon_bo_desc desc;
845 struct pb_manager *provider;
846 struct pb_buffer *buffer;
847
848 memset(&desc, 0, sizeof(desc));
849 desc.base.alignment = alignment;
850
851 /* Additional criteria for the cache manager. */
852 desc.base.usage = domain;
853 desc.initial_domains = domain;
854
855 /* Assign a buffer manager. */
856 if (use_reusable_pool)
857 provider = ws->cman;
858 else
859 provider = ws->kman;
860
861 buffer = provider->create_buffer(provider, size, &desc.base);
862 if (!buffer)
863 return NULL;
864
865 return (struct pb_buffer*)buffer;
866 }
867
868 static struct pb_buffer *radeon_winsys_bo_from_handle(struct radeon_winsys *rws,
869 struct winsys_handle *whandle,
870 unsigned *stride)
871 {
872 struct radeon_drm_winsys *ws = radeon_drm_winsys(rws);
873 struct radeon_bo *bo;
874 struct radeon_bomgr *mgr = radeon_bomgr(ws->kman);
875 struct drm_gem_open open_arg = {};
876 int r;
877
878 memset(&open_arg, 0, sizeof(open_arg));
879
880 if (whandle->type != DRM_API_HANDLE_TYPE_SHARED)
881 return NULL;
882
883 /* We must maintain a list of pairs <handle, bo>, so that we always return
884 * the same BO for one particular handle. If we didn't do that and created
885 * more than one BO for the same handle and then relocated them in a CS,
886 * we would hit a deadlock in the kernel.
887 *
888 * The list of pairs is guarded by a mutex, of course. */
889 pipe_mutex_lock(mgr->bo_handles_mutex);
890
891 /* First check if there already is an existing bo for the handle. */
892 bo = util_hash_table_get(mgr->bo_handles, (void*)(uintptr_t)whandle->handle);
893 if (bo) {
894 /* Increase the refcount. */
895 struct pb_buffer *b = NULL;
896 pb_reference(&b, &bo->base);
897 goto done;
898 }
899
900 /* There isn't, create a new one. */
901 bo = CALLOC_STRUCT(radeon_bo);
902 if (!bo) {
903 goto fail;
904 }
905
906 /* Open the BO. */
907 open_arg.name = whandle->handle;
908 if (drmIoctl(ws->fd, DRM_IOCTL_GEM_OPEN, &open_arg)) {
909 FREE(bo);
910 goto fail;
911 }
912 bo->handle = open_arg.handle;
913 bo->name = whandle->handle;
914
915 /* Initialize it. */
916 pipe_reference_init(&bo->base.reference, 1);
917 bo->base.alignment = 0;
918 bo->base.usage = PB_USAGE_GPU_WRITE | PB_USAGE_GPU_READ;
919 bo->base.size = open_arg.size;
920 bo->base.vtbl = &radeon_bo_vtbl;
921 bo->mgr = mgr;
922 bo->rws = mgr->rws;
923 bo->va = 0;
924 pipe_mutex_init(bo->map_mutex);
925
926 util_hash_table_set(mgr->bo_handles, (void*)(uintptr_t)whandle->handle, bo);
927
928 done:
929 pipe_mutex_unlock(mgr->bo_handles_mutex);
930
931 if (stride)
932 *stride = whandle->stride;
933
934 if (mgr->va && !bo->va) {
935 struct drm_radeon_gem_va va;
936
937 bo->va = radeon_bomgr_find_va(mgr, bo->base.size, 1 << 20);
938
939 va.handle = bo->handle;
940 va.operation = RADEON_VA_MAP;
941 va.vm_id = 0;
942 va.offset = bo->va;
943 va.flags = RADEON_VM_PAGE_READABLE |
944 RADEON_VM_PAGE_WRITEABLE |
945 RADEON_VM_PAGE_SNOOPED;
946 va.offset = bo->va;
947 r = drmCommandWriteRead(ws->fd, DRM_RADEON_GEM_VA, &va, sizeof(va));
948 if (r && va.operation == RADEON_VA_RESULT_ERROR) {
949 fprintf(stderr, "radeon: Failed to assign virtual address space\n");
950 radeon_bo_destroy(&bo->base);
951 return NULL;
952 }
953 if (va.operation == RADEON_VA_RESULT_VA_EXIST) {
954 radeon_bomgr_free_va(mgr, bo->va, bo->base.size);
955 bo->va = va.offset;
956 radeon_bomgr_force_va(mgr, bo->va, bo->base.size);
957 }
958 }
959
960 ws->allocated_vram += align(open_arg.size, 4096);
961 bo->initial_domain = RADEON_DOMAIN_VRAM;
962
963 return (struct pb_buffer*)bo;
964
965 fail:
966 pipe_mutex_unlock(mgr->bo_handles_mutex);
967 return NULL;
968 }
969
970 static boolean radeon_winsys_bo_get_handle(struct pb_buffer *buffer,
971 unsigned stride,
972 struct winsys_handle *whandle)
973 {
974 struct drm_gem_flink flink;
975 struct radeon_bo *bo = get_radeon_bo(buffer);
976
977 memset(&flink, 0, sizeof(flink));
978
979 if (whandle->type == DRM_API_HANDLE_TYPE_SHARED) {
980 if (!bo->flinked) {
981 flink.handle = bo->handle;
982
983 if (ioctl(bo->rws->fd, DRM_IOCTL_GEM_FLINK, &flink)) {
984 return FALSE;
985 }
986
987 bo->flinked = TRUE;
988 bo->flink = flink.name;
989
990 pipe_mutex_lock(bo->mgr->bo_handles_mutex);
991 util_hash_table_set(bo->mgr->bo_handles, (void*)(uintptr_t)bo->flink, bo);
992 pipe_mutex_unlock(bo->mgr->bo_handles_mutex);
993 }
994 whandle->handle = bo->flink;
995 } else if (whandle->type == DRM_API_HANDLE_TYPE_KMS) {
996 whandle->handle = bo->handle;
997 } else if (whandle->type == DRM_API_HANDLE_TYPE_FD) {
998 /* TODO: Implement */
999 return FALSE;
1000 }
1001
1002 whandle->stride = stride;
1003 return TRUE;
1004 }
1005
1006 static uint64_t radeon_winsys_bo_va(struct radeon_winsys_cs_handle *buf)
1007 {
1008 return ((struct radeon_bo*)buf)->va;
1009 }
1010
1011 void radeon_bomgr_init_functions(struct radeon_drm_winsys *ws)
1012 {
1013 ws->base.buffer_get_cs_handle = radeon_drm_get_cs_handle;
1014 ws->base.buffer_set_tiling = radeon_bo_set_tiling;
1015 ws->base.buffer_get_tiling = radeon_bo_get_tiling;
1016 ws->base.buffer_map = radeon_bo_map;
1017 ws->base.buffer_unmap = radeon_bo_unmap;
1018 ws->base.buffer_wait = radeon_bo_wait;
1019 ws->base.buffer_is_busy = radeon_bo_is_busy;
1020 ws->base.buffer_create = radeon_winsys_bo_create;
1021 ws->base.buffer_from_handle = radeon_winsys_bo_from_handle;
1022 ws->base.buffer_get_handle = radeon_winsys_bo_get_handle;
1023 ws->base.buffer_get_virtual_address = radeon_winsys_bo_va;
1024 }