2 * Copyright © 2011 Marek Olšák <maraeo@gmail.com>
5 * Permission is hereby granted, free of charge, to any person obtaining
6 * a copy of this software and associated documentation files (the
7 * "Software"), to deal in the Software without restriction, including
8 * without limitation the rights to use, copy, modify, merge, publish,
9 * distribute, sub license, and/or sell copies of the Software, and to
10 * permit persons to whom the Software is furnished to do so, subject to
11 * the following conditions:
13 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
14 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
15 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
16 * NON-INFRINGEMENT. IN NO EVENT SHALL THE COPYRIGHT HOLDERS, AUTHORS
17 * AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
18 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
20 * USE OR OTHER DEALINGS IN THE SOFTWARE.
22 * The above copyright notice and this permission notice (including the
23 * next paragraph) shall be included in all copies or substantial portions
27 #define _FILE_OFFSET_BITS 64
28 #include "radeon_drm_cs.h"
30 #include "util/u_hash_table.h"
31 #include "util/u_memory.h"
32 #include "util/u_simple_list.h"
33 #include "os/os_thread.h"
34 #include "os/os_mman.h"
36 #include "state_tracker/drm_driver.h"
38 #include <sys/ioctl.h>
42 #define RADEON_BO_FLAGS_MACRO_TILE 1
43 #define RADEON_BO_FLAGS_MICRO_TILE 2
44 #define RADEON_BO_FLAGS_MICRO_TILE_SQUARE 0x20
46 #ifndef DRM_RADEON_GEM_WAIT
47 #define DRM_RADEON_GEM_WAIT 0x2b
49 #define RADEON_GEM_NO_WAIT 0x1
50 #define RADEON_GEM_USAGE_READ 0x2
51 #define RADEON_GEM_USAGE_WRITE 0x4
53 struct drm_radeon_gem_wait
{
55 uint32_t flags
; /* one of RADEON_GEM_* */
61 extern const struct pb_vtbl radeon_bo_vtbl
;
64 static INLINE
struct radeon_bo
*radeon_bo(struct pb_buffer
*bo
)
66 assert(bo
->vtbl
== &radeon_bo_vtbl
);
67 return (struct radeon_bo
*)bo
;
72 struct pb_manager base
;
75 struct radeon_drm_winsys
*rws
;
77 /* List of buffer handles and its mutex. */
78 struct util_hash_table
*bo_handles
;
79 pipe_mutex bo_handles_mutex
;
82 static INLINE
struct radeon_bomgr
*radeon_bomgr(struct pb_manager
*mgr
)
84 return (struct radeon_bomgr
*)mgr
;
87 static struct radeon_bo
*get_radeon_bo(struct pb_buffer
*_buf
)
89 struct radeon_bo
*bo
= NULL
;
91 if (_buf
->vtbl
== &radeon_bo_vtbl
) {
94 struct pb_buffer
*base_buf
;
96 pb_get_base_buffer(_buf
, &base_buf
, &offset
);
98 if (base_buf
->vtbl
== &radeon_bo_vtbl
)
99 bo
= radeon_bo(base_buf
);
105 static void radeon_bo_wait(struct pb_buffer
*_buf
, enum radeon_bo_usage usage
)
107 struct radeon_bo
*bo
= get_radeon_bo(_buf
);
109 while (p_atomic_read(&bo
->num_active_ioctls
)) {
113 if (bo
->rws
->info
.drm_minor
>= 12) {
114 struct drm_radeon_gem_wait args
= {};
115 args
.handle
= bo
->handle
;
117 while (drmCommandWriteRead(bo
->rws
->fd
, DRM_RADEON_GEM_WAIT
,
118 &args
, sizeof(args
)) == -EBUSY
);
120 struct drm_radeon_gem_wait_idle args
= {};
121 args
.handle
= bo
->handle
;
122 while (drmCommandWriteRead(bo
->rws
->fd
, DRM_RADEON_GEM_WAIT_IDLE
,
123 &args
, sizeof(args
)) == -EBUSY
);
127 static boolean
radeon_bo_is_busy(struct pb_buffer
*_buf
,
128 enum radeon_bo_usage usage
)
130 struct radeon_bo
*bo
= get_radeon_bo(_buf
);
132 if (p_atomic_read(&bo
->num_active_ioctls
)) {
136 if (bo
->rws
->info
.drm_minor
>= 12) {
137 struct drm_radeon_gem_wait args
= {};
138 args
.handle
= bo
->handle
;
139 args
.flags
= usage
| RADEON_GEM_NO_WAIT
;
140 return drmCommandWriteRead(bo
->rws
->fd
, DRM_RADEON_GEM_WAIT
,
141 &args
, sizeof(args
)) != 0;
143 struct drm_radeon_gem_busy args
= {};
144 args
.handle
= bo
->handle
;
145 return drmCommandWriteRead(bo
->rws
->fd
, DRM_RADEON_GEM_BUSY
,
146 &args
, sizeof(args
)) != 0;
150 static void radeon_bo_destroy(struct pb_buffer
*_buf
)
152 struct radeon_bo
*bo
= radeon_bo(_buf
);
153 struct drm_gem_close args
= {};
156 pipe_mutex_lock(bo
->mgr
->bo_handles_mutex
);
157 util_hash_table_remove(bo
->mgr
->bo_handles
,
158 (void*)(uintptr_t)bo
->name
);
159 pipe_mutex_unlock(bo
->mgr
->bo_handles_mutex
);
163 os_munmap(bo
->ptr
, bo
->size
);
166 args
.handle
= bo
->handle
;
167 drmIoctl(bo
->rws
->fd
, DRM_IOCTL_GEM_CLOSE
, &args
);
168 pipe_mutex_destroy(bo
->map_mutex
);
172 static unsigned get_pb_usage_from_transfer_flags(enum pipe_transfer_usage usage
)
176 if (usage
& PIPE_TRANSFER_WRITE
)
177 res
|= PB_USAGE_CPU_WRITE
;
179 if (usage
& PIPE_TRANSFER_DONTBLOCK
)
180 res
|= PB_USAGE_DONTBLOCK
;
182 if (usage
& PIPE_TRANSFER_UNSYNCHRONIZED
)
183 res
|= PB_USAGE_UNSYNCHRONIZED
;
188 static void *radeon_bo_map_internal(struct pb_buffer
*_buf
,
189 unsigned flags
, void *flush_ctx
)
191 struct radeon_bo
*bo
= radeon_bo(_buf
);
192 struct radeon_drm_cs
*cs
= flush_ctx
;
193 struct drm_radeon_gem_mmap args
= {};
196 /* If it's not unsynchronized bo_map, flush CS if needed and then wait. */
197 if (!(flags
& PB_USAGE_UNSYNCHRONIZED
)) {
198 /* DONTBLOCK doesn't make sense with UNSYNCHRONIZED. */
199 if (flags
& PB_USAGE_DONTBLOCK
) {
200 if (!(flags
& PB_USAGE_CPU_WRITE
)) {
203 * Since we are mapping for read, we don't need to wait
204 * if the GPU is using the buffer for read too
205 * (neither one is changing it).
207 * Only check whether the buffer is being used for write. */
208 if (radeon_bo_is_referenced_by_cs_for_write(cs
, bo
)) {
209 cs
->flush_cs(cs
->flush_data
, RADEON_FLUSH_ASYNC
);
213 if (radeon_bo_is_busy((struct pb_buffer
*)bo
,
214 RADEON_USAGE_WRITE
)) {
218 if (radeon_bo_is_referenced_by_cs(cs
, bo
)) {
219 cs
->flush_cs(cs
->flush_data
, RADEON_FLUSH_ASYNC
);
223 if (radeon_bo_is_busy((struct pb_buffer
*)bo
,
224 RADEON_USAGE_READWRITE
)) {
229 if (!(flags
& PB_USAGE_CPU_WRITE
)) {
232 * Since we are mapping for read, we don't need to wait
233 * if the GPU is using the buffer for read too
234 * (neither one is changing it).
236 * Only check whether the buffer is being used for write. */
237 if (radeon_bo_is_referenced_by_cs_for_write(cs
, bo
)) {
238 cs
->flush_cs(cs
->flush_data
, 0);
240 radeon_bo_wait((struct pb_buffer
*)bo
,
243 /* Mapping for write. */
244 if (radeon_bo_is_referenced_by_cs(cs
, bo
)) {
245 cs
->flush_cs(cs
->flush_data
, 0);
247 /* Try to avoid busy-waiting in radeon_bo_wait. */
248 if (p_atomic_read(&bo
->num_active_ioctls
))
249 radeon_drm_cs_sync_flush(cs
);
252 radeon_bo_wait((struct pb_buffer
*)bo
, RADEON_USAGE_READWRITE
);
257 /* Return the pointer if it's already mapped. */
261 /* Map the buffer. */
262 pipe_mutex_lock(bo
->map_mutex
);
263 /* Return the pointer if it's already mapped (in case of a race). */
265 pipe_mutex_unlock(bo
->map_mutex
);
268 args
.handle
= bo
->handle
;
270 args
.size
= (uint64_t)bo
->size
;
271 if (drmCommandWriteRead(bo
->rws
->fd
,
275 pipe_mutex_unlock(bo
->map_mutex
);
276 fprintf(stderr
, "radeon: gem_mmap failed: %p 0x%08X\n",
281 ptr
= os_mmap(0, args
.size
, PROT_READ
|PROT_WRITE
, MAP_SHARED
,
282 bo
->rws
->fd
, args
.addr_ptr
);
283 if (ptr
== MAP_FAILED
) {
284 pipe_mutex_unlock(bo
->map_mutex
);
285 fprintf(stderr
, "radeon: mmap failed, errno: %i\n", errno
);
289 pipe_mutex_unlock(bo
->map_mutex
);
294 static void radeon_bo_unmap_internal(struct pb_buffer
*_buf
)
299 static void radeon_bo_get_base_buffer(struct pb_buffer
*buf
,
300 struct pb_buffer
**base_buf
,
307 static enum pipe_error
radeon_bo_validate(struct pb_buffer
*_buf
,
308 struct pb_validate
*vl
,
315 static void radeon_bo_fence(struct pb_buffer
*buf
,
316 struct pipe_fence_handle
*fence
)
320 const struct pb_vtbl radeon_bo_vtbl
= {
322 radeon_bo_map_internal
,
323 radeon_bo_unmap_internal
,
326 radeon_bo_get_base_buffer
,
329 static struct pb_buffer
*radeon_bomgr_create_bo(struct pb_manager
*_mgr
,
331 const struct pb_desc
*desc
)
333 struct radeon_bomgr
*mgr
= radeon_bomgr(_mgr
);
334 struct radeon_drm_winsys
*rws
= mgr
->rws
;
335 struct radeon_bo
*bo
;
336 struct drm_radeon_gem_create args
= {};
339 args
.alignment
= desc
->alignment
;
340 args
.initial_domain
=
341 (desc
->usage
& RADEON_PB_USAGE_DOMAIN_GTT
?
342 RADEON_GEM_DOMAIN_GTT
: 0) |
343 (desc
->usage
& RADEON_PB_USAGE_DOMAIN_VRAM
?
344 RADEON_GEM_DOMAIN_VRAM
: 0);
346 if (drmCommandWriteRead(rws
->fd
, DRM_RADEON_GEM_CREATE
,
347 &args
, sizeof(args
))) {
348 fprintf(stderr
, "radeon: Failed to allocate a buffer:\n");
349 fprintf(stderr
, "radeon: size : %d bytes\n", size
);
350 fprintf(stderr
, "radeon: alignment : %d bytes\n", desc
->alignment
);
351 fprintf(stderr
, "radeon: domains : %d\n", args
.initial_domain
);
355 bo
= CALLOC_STRUCT(radeon_bo
);
359 pipe_reference_init(&bo
->base
.base
.reference
, 1);
360 bo
->base
.base
.alignment
= desc
->alignment
;
361 bo
->base
.base
.usage
= desc
->usage
;
362 bo
->base
.base
.size
= size
;
363 bo
->base
.vtbl
= &radeon_bo_vtbl
;
366 bo
->handle
= args
.handle
;
368 pipe_mutex_init(bo
->map_mutex
);
373 static void radeon_bomgr_flush(struct pb_manager
*mgr
)
378 /* This is for the cache bufmgr. */
379 static boolean
radeon_bomgr_is_buffer_busy(struct pb_manager
*_mgr
,
380 struct pb_buffer
*_buf
)
382 struct radeon_bo
*bo
= radeon_bo(_buf
);
384 if (radeon_bo_is_referenced_by_any_cs(bo
)) {
388 if (radeon_bo_is_busy((struct pb_buffer
*)bo
, RADEON_USAGE_READWRITE
)) {
395 static void radeon_bomgr_destroy(struct pb_manager
*_mgr
)
397 struct radeon_bomgr
*mgr
= radeon_bomgr(_mgr
);
398 util_hash_table_destroy(mgr
->bo_handles
);
399 pipe_mutex_destroy(mgr
->bo_handles_mutex
);
403 #define PTR_TO_UINT(x) ((unsigned)((intptr_t)(x)))
405 static unsigned handle_hash(void *key
)
407 return PTR_TO_UINT(key
);
410 static int handle_compare(void *key1
, void *key2
)
412 return PTR_TO_UINT(key1
) != PTR_TO_UINT(key2
);
415 struct pb_manager
*radeon_bomgr_create(struct radeon_drm_winsys
*rws
)
417 struct radeon_bomgr
*mgr
;
419 mgr
= CALLOC_STRUCT(radeon_bomgr
);
423 mgr
->base
.destroy
= radeon_bomgr_destroy
;
424 mgr
->base
.create_buffer
= radeon_bomgr_create_bo
;
425 mgr
->base
.flush
= radeon_bomgr_flush
;
426 mgr
->base
.is_buffer_busy
= radeon_bomgr_is_buffer_busy
;
429 mgr
->bo_handles
= util_hash_table_create(handle_hash
, handle_compare
);
430 pipe_mutex_init(mgr
->bo_handles_mutex
);
434 static void *radeon_bo_map(struct pb_buffer
*buf
,
435 struct radeon_winsys_cs
*cs
,
436 enum pipe_transfer_usage usage
)
438 return pb_map(buf
, get_pb_usage_from_transfer_flags(usage
), cs
);
441 static void radeon_bo_get_tiling(struct pb_buffer
*_buf
,
442 enum radeon_bo_layout
*microtiled
,
443 enum radeon_bo_layout
*macrotiled
)
445 struct radeon_bo
*bo
= get_radeon_bo(_buf
);
446 struct drm_radeon_gem_set_tiling args
= {};
448 args
.handle
= bo
->handle
;
450 drmCommandWriteRead(bo
->rws
->fd
,
451 DRM_RADEON_GEM_GET_TILING
,
455 *microtiled
= RADEON_LAYOUT_LINEAR
;
456 *macrotiled
= RADEON_LAYOUT_LINEAR
;
457 if (args
.tiling_flags
& RADEON_BO_FLAGS_MICRO_TILE
)
458 *microtiled
= RADEON_LAYOUT_TILED
;
460 if (args
.tiling_flags
& RADEON_BO_FLAGS_MACRO_TILE
)
461 *macrotiled
= RADEON_LAYOUT_TILED
;
464 static void radeon_bo_set_tiling(struct pb_buffer
*_buf
,
465 struct radeon_winsys_cs
*rcs
,
466 enum radeon_bo_layout microtiled
,
467 enum radeon_bo_layout macrotiled
,
470 struct radeon_bo
*bo
= get_radeon_bo(_buf
);
471 struct radeon_drm_cs
*cs
= radeon_drm_cs(rcs
);
472 struct drm_radeon_gem_set_tiling args
= {};
474 /* Tiling determines how DRM treats the buffer data.
475 * We must flush CS when changing it if the buffer is referenced. */
476 if (cs
&& radeon_bo_is_referenced_by_cs(cs
, bo
)) {
477 cs
->flush_cs(cs
->flush_data
, 0);
480 while (p_atomic_read(&bo
->num_active_ioctls
)) {
484 if (microtiled
== RADEON_LAYOUT_TILED
)
485 args
.tiling_flags
|= RADEON_BO_FLAGS_MICRO_TILE
;
486 else if (microtiled
== RADEON_LAYOUT_SQUARETILED
)
487 args
.tiling_flags
|= RADEON_BO_FLAGS_MICRO_TILE_SQUARE
;
489 if (macrotiled
== RADEON_LAYOUT_TILED
)
490 args
.tiling_flags
|= RADEON_BO_FLAGS_MACRO_TILE
;
492 args
.handle
= bo
->handle
;
495 drmCommandWriteRead(bo
->rws
->fd
,
496 DRM_RADEON_GEM_SET_TILING
,
501 static struct radeon_winsys_cs_handle
*radeon_drm_get_cs_handle(
502 struct pb_buffer
*_buf
)
504 /* return radeon_bo. */
505 return (struct radeon_winsys_cs_handle
*)get_radeon_bo(_buf
);
508 static unsigned get_pb_usage_from_create_flags(enum radeon_bo_domain domain
)
512 if (domain
& RADEON_DOMAIN_GTT
)
513 res
|= RADEON_PB_USAGE_DOMAIN_GTT
;
515 if (domain
& RADEON_DOMAIN_VRAM
)
516 res
|= RADEON_PB_USAGE_DOMAIN_VRAM
;
521 static struct pb_buffer
*
522 radeon_winsys_bo_create(struct radeon_winsys
*rws
,
526 enum radeon_bo_domain domain
)
528 struct radeon_drm_winsys
*ws
= radeon_drm_winsys(rws
);
530 struct pb_manager
*provider
;
531 struct pb_buffer
*buffer
;
533 memset(&desc
, 0, sizeof(desc
));
534 desc
.alignment
= alignment
;
535 desc
.usage
= get_pb_usage_from_create_flags(domain
);
537 /* Assign a buffer manager. */
538 if (bind
& (PIPE_BIND_VERTEX_BUFFER
| PIPE_BIND_INDEX_BUFFER
|
539 PIPE_BIND_CONSTANT_BUFFER
))
544 buffer
= provider
->create_buffer(provider
, size
, &desc
);
548 return (struct pb_buffer
*)buffer
;
551 static struct pb_buffer
*radeon_winsys_bo_from_handle(struct radeon_winsys
*rws
,
552 struct winsys_handle
*whandle
,
556 struct radeon_drm_winsys
*ws
= radeon_drm_winsys(rws
);
557 struct radeon_bo
*bo
;
558 struct radeon_bomgr
*mgr
= radeon_bomgr(ws
->kman
);
559 struct drm_gem_open open_arg
= {};
561 /* We must maintain a list of pairs <handle, bo>, so that we always return
562 * the same BO for one particular handle. If we didn't do that and created
563 * more than one BO for the same handle and then relocated them in a CS,
564 * we would hit a deadlock in the kernel.
566 * The list of pairs is guarded by a mutex, of course. */
567 pipe_mutex_lock(mgr
->bo_handles_mutex
);
569 /* First check if there already is an existing bo for the handle. */
570 bo
= util_hash_table_get(mgr
->bo_handles
, (void*)(uintptr_t)whandle
->handle
);
572 /* Increase the refcount. */
573 struct pb_buffer
*b
= NULL
;
574 pb_reference(&b
, &bo
->base
);
578 /* There isn't, create a new one. */
579 bo
= CALLOC_STRUCT(radeon_bo
);
585 open_arg
.name
= whandle
->handle
;
586 if (drmIoctl(ws
->fd
, DRM_IOCTL_GEM_OPEN
, &open_arg
)) {
590 bo
->handle
= open_arg
.handle
;
591 bo
->size
= open_arg
.size
;
592 bo
->name
= whandle
->handle
;
595 pipe_reference_init(&bo
->base
.base
.reference
, 1);
596 bo
->base
.base
.alignment
= 0;
597 bo
->base
.base
.usage
= PB_USAGE_GPU_WRITE
| PB_USAGE_GPU_READ
;
598 bo
->base
.base
.size
= bo
->size
;
599 bo
->base
.vtbl
= &radeon_bo_vtbl
;
602 pipe_mutex_init(bo
->map_mutex
);
604 util_hash_table_set(mgr
->bo_handles
, (void*)(uintptr_t)whandle
->handle
, bo
);
607 pipe_mutex_unlock(mgr
->bo_handles_mutex
);
610 *stride
= whandle
->stride
;
612 *size
= bo
->base
.base
.size
;
614 return (struct pb_buffer
*)bo
;
617 pipe_mutex_unlock(mgr
->bo_handles_mutex
);
621 static boolean
radeon_winsys_bo_get_handle(struct pb_buffer
*buffer
,
623 struct winsys_handle
*whandle
)
625 struct drm_gem_flink flink
= {};
626 struct radeon_bo
*bo
= get_radeon_bo(buffer
);
628 if (whandle
->type
== DRM_API_HANDLE_TYPE_SHARED
) {
630 flink
.handle
= bo
->handle
;
632 if (ioctl(bo
->rws
->fd
, DRM_IOCTL_GEM_FLINK
, &flink
)) {
637 bo
->flink
= flink
.name
;
639 whandle
->handle
= bo
->flink
;
640 } else if (whandle
->type
== DRM_API_HANDLE_TYPE_KMS
) {
641 whandle
->handle
= bo
->handle
;
644 whandle
->stride
= stride
;
648 void radeon_bomgr_init_functions(struct radeon_drm_winsys
*ws
)
650 ws
->base
.buffer_get_cs_handle
= radeon_drm_get_cs_handle
;
651 ws
->base
.buffer_set_tiling
= radeon_bo_set_tiling
;
652 ws
->base
.buffer_get_tiling
= radeon_bo_get_tiling
;
653 ws
->base
.buffer_map
= radeon_bo_map
;
654 ws
->base
.buffer_unmap
= pb_unmap
;
655 ws
->base
.buffer_wait
= radeon_bo_wait
;
656 ws
->base
.buffer_is_busy
= radeon_bo_is_busy
;
657 ws
->base
.buffer_create
= radeon_winsys_bo_create
;
658 ws
->base
.buffer_from_handle
= radeon_winsys_bo_from_handle
;
659 ws
->base
.buffer_get_handle
= radeon_winsys_bo_get_handle
;