src/gallium/winsys/radeon/drm/radeon_drm_bo.c

   1 /*
   2  * Copyright © 2011 Marek Olšák <maraeo@gmail.com>
   3  * All Rights Reserved.
   4  *
   5  * Permission is hereby granted, free of charge, to any person obtaining
   6  * a copy of this software and associated documentation files (the
   7  * "Software"), to deal in the Software without restriction, including
   8  * without limitation the rights to use, copy, modify, merge, publish,
   9  * distribute, sub license, and/or sell copies of the Software, and to
  10  * permit persons to whom the Software is furnished to do so, subject to
  11  * the following conditions:
  12  *
  13  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  14  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
  15  * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  16  * NON-INFRINGEMENT. IN NO EVENT SHALL THE COPYRIGHT HOLDERS, AUTHORS
  17  * AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  18  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
  20  * USE OR OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  * The above copyright notice and this permission notice (including the
  23  * next paragraph) shall be included in all copies or substantial portions
  24  * of the Software.
  25  */
  26
  27 #define _FILE_OFFSET_BITS 64
  28 #include "radeon_drm_cs.h"
  29
  30 #include "util/u_hash_table.h"
  31 #include "util/u_memory.h"
  32 #include "util/u_simple_list.h"
  33 #include "os/os_thread.h"
  34 #include "os/os_mman.h"
  35
  36 #include "state_tracker/drm_driver.h"
  37
  38 #include <sys/ioctl.h>
  39 #include <xf86drm.h>
  40 #include <errno.h>
  41
  42 #define RADEON_BO_FLAGS_MACRO_TILE  1
  43 #define RADEON_BO_FLAGS_MICRO_TILE  2
  44 #define RADEON_BO_FLAGS_MICRO_TILE_SQUARE 0x20
  45
  46 #ifndef DRM_RADEON_GEM_WAIT
  47 #define DRM_RADEON_GEM_WAIT             0x2b
  48
  49 #define RADEON_GEM_NO_WAIT      0x1
  50 #define RADEON_GEM_USAGE_READ   0x2
  51 #define RADEON_GEM_USAGE_WRITE  0x4
  52
  53 struct drm_radeon_gem_wait {
  54         uint32_t        handle;
  55         uint32_t        flags;  /* one of RADEON_GEM_* */
  56 };
  57
  58 #endif
  59
  60
  61 extern const struct pb_vtbl radeon_bo_vtbl;
  62
  63
  64 static INLINE struct radeon_bo *radeon_bo(struct pb_buffer *bo)
  65 {
  66     assert(bo->vtbl == &radeon_bo_vtbl);
  67     return (struct radeon_bo *)bo;
  68 }
  69
  70 struct radeon_bomgr {
  71     /* Base class. */
  72     struct pb_manager base;
  73
  74     /* Winsys. */
  75     struct radeon_drm_winsys *rws;
  76
  77     /* List of buffer handles and its mutex. */
  78     struct util_hash_table *bo_handles;
  79     pipe_mutex bo_handles_mutex;
  80 };
  81
  82 static INLINE struct radeon_bomgr *radeon_bomgr(struct pb_manager *mgr)
  83 {
  84     return (struct radeon_bomgr *)mgr;
  85 }
  86
  87 static struct radeon_bo *get_radeon_bo(struct pb_buffer *_buf)
  88 {
  89     struct radeon_bo *bo = NULL;
  90
  91     if (_buf->vtbl == &radeon_bo_vtbl) {
  92         bo = radeon_bo(_buf);
  93     } else {
  94         struct pb_buffer *base_buf;
  95         pb_size offset;
  96         pb_get_base_buffer(_buf, &base_buf, &offset);
  97
  98         if (base_buf->vtbl == &radeon_bo_vtbl)
  99             bo = radeon_bo(base_buf);
 100     }
 101
 102     return bo;
 103 }
 104
 105 static void radeon_bo_wait(struct pb_buffer *_buf, enum radeon_bo_usage usage)
 106 {
 107     struct radeon_bo *bo = get_radeon_bo(_buf);
 108
 109     while (p_atomic_read(&bo->num_active_ioctls)) {
 110         sched_yield();
 111     }
 112
 113     if (bo->rws->info.drm_minor >= 12) {
 114         struct drm_radeon_gem_wait args = {};
 115         args.handle = bo->handle;
 116         args.flags = usage;
 117         while (drmCommandWriteRead(bo->rws->fd, DRM_RADEON_GEM_WAIT,
 118                                    &args, sizeof(args)) == -EBUSY);
 119     } else {
 120         struct drm_radeon_gem_wait_idle args = {};
 121         args.handle = bo->handle;
 122         while (drmCommandWriteRead(bo->rws->fd, DRM_RADEON_GEM_WAIT_IDLE,
 123                                    &args, sizeof(args)) == -EBUSY);
 124     }
 125 }
 126
 127 static boolean radeon_bo_is_busy(struct pb_buffer *_buf,
 128                                  enum radeon_bo_usage usage)
 129 {
 130     struct radeon_bo *bo = get_radeon_bo(_buf);
 131
 132     if (p_atomic_read(&bo->num_active_ioctls)) {
 133         return TRUE;
 134     }
 135
 136     if (bo->rws->info.drm_minor >= 12) {
 137         struct drm_radeon_gem_wait args = {};
 138         args.handle = bo->handle;
 139         args.flags = usage | RADEON_GEM_NO_WAIT;
 140         return drmCommandWriteRead(bo->rws->fd, DRM_RADEON_GEM_WAIT,
 141                                    &args, sizeof(args)) != 0;
 142     } else {
 143         struct drm_radeon_gem_busy args = {};
 144         args.handle = bo->handle;
 145         return drmCommandWriteRead(bo->rws->fd, DRM_RADEON_GEM_BUSY,
 146                                    &args, sizeof(args)) != 0;
 147     }
 148 }
 149
 150 static void radeon_bo_destroy(struct pb_buffer *_buf)
 151 {
 152     struct radeon_bo *bo = radeon_bo(_buf);
 153     struct drm_gem_close args = {};
 154
 155     if (bo->name) {
 156         pipe_mutex_lock(bo->mgr->bo_handles_mutex);
 157         util_hash_table_remove(bo->mgr->bo_handles,
 158                                (void*)(uintptr_t)bo->name);
 159         pipe_mutex_unlock(bo->mgr->bo_handles_mutex);
 160     }
 161
 162     if (bo->ptr)
 163         os_munmap(bo->ptr, bo->size);
 164
 165     /* Close object. */
 166     args.handle = bo->handle;
 167     drmIoctl(bo->rws->fd, DRM_IOCTL_GEM_CLOSE, &args);
 168     pipe_mutex_destroy(bo->map_mutex);
 169     FREE(bo);
 170 }
 171
 172 static unsigned get_pb_usage_from_transfer_flags(enum pipe_transfer_usage usage)
 173 {
 174     unsigned res = 0;
 175
 176     if (usage & PIPE_TRANSFER_WRITE)
 177         res |= PB_USAGE_CPU_WRITE;
 178
 179     if (usage & PIPE_TRANSFER_DONTBLOCK)
 180         res |= PB_USAGE_DONTBLOCK;
 181
 182     if (usage & PIPE_TRANSFER_UNSYNCHRONIZED)
 183         res |= PB_USAGE_UNSYNCHRONIZED;
 184
 185     return res;
 186 }
 187
 188 static void *radeon_bo_map_internal(struct pb_buffer *_buf,
 189                                     unsigned flags, void *flush_ctx)
 190 {
 191     struct radeon_bo *bo = radeon_bo(_buf);
 192     struct radeon_drm_cs *cs = flush_ctx;
 193     struct drm_radeon_gem_mmap args = {};
 194     void *ptr;
 195
 196     /* If it's not unsynchronized bo_map, flush CS if needed and then wait. */
 197     if (!(flags & PB_USAGE_UNSYNCHRONIZED)) {
 198         /* DONTBLOCK doesn't make sense with UNSYNCHRONIZED. */
 199         if (flags & PB_USAGE_DONTBLOCK) {
 200             if (!(flags & PB_USAGE_CPU_WRITE)) {
 201                 /* Mapping for read.
 202                  *
 203                  * Since we are mapping for read, we don't need to wait
 204                  * if the GPU is using the buffer for read too
 205                  * (neither one is changing it).
 206                  *
 207                  * Only check whether the buffer is being used for write. */
 208                 if (radeon_bo_is_referenced_by_cs_for_write(cs, bo)) {
 209                     cs->flush_cs(cs->flush_data, RADEON_FLUSH_ASYNC);
 210                     return NULL;
 211                 }
 212
 213                 if (radeon_bo_is_busy((struct pb_buffer*)bo,
 214                                       RADEON_USAGE_WRITE)) {
 215                     return NULL;
 216                 }
 217             } else {
 218                 if (radeon_bo_is_referenced_by_cs(cs, bo)) {
 219                     cs->flush_cs(cs->flush_data, RADEON_FLUSH_ASYNC);
 220                     return NULL;
 221                 }
 222
 223                 if (radeon_bo_is_busy((struct pb_buffer*)bo,
 224                                       RADEON_USAGE_READWRITE)) {
 225                     return NULL;
 226                 }
 227             }
 228         } else {
 229             if (!(flags & PB_USAGE_CPU_WRITE)) {
 230                 /* Mapping for read.
 231                  *
 232                  * Since we are mapping for read, we don't need to wait
 233                  * if the GPU is using the buffer for read too
 234                  * (neither one is changing it).
 235                  *
 236                  * Only check whether the buffer is being used for write. */
 237                 if (radeon_bo_is_referenced_by_cs_for_write(cs, bo)) {
 238                     cs->flush_cs(cs->flush_data, 0);
 239                 }
 240                 radeon_bo_wait((struct pb_buffer*)bo,
 241                                RADEON_USAGE_WRITE);
 242             } else {
 243                 /* Mapping for write. */
 244                 if (radeon_bo_is_referenced_by_cs(cs, bo)) {
 245                     cs->flush_cs(cs->flush_data, 0);
 246                 } else {
 247                     /* Try to avoid busy-waiting in radeon_bo_wait. */
 248                     if (p_atomic_read(&bo->num_active_ioctls))
 249                         radeon_drm_cs_sync_flush(cs);
 250                 }
 251
 252                 radeon_bo_wait((struct pb_buffer*)bo, RADEON_USAGE_READWRITE);
 253             }
 254         }
 255     }
 256
 257     /* Return the pointer if it's already mapped. */
 258     if (bo->ptr)
 259         return bo->ptr;
 260
 261     /* Map the buffer. */
 262     pipe_mutex_lock(bo->map_mutex);
 263     /* Return the pointer if it's already mapped (in case of a race). */
 264     if (bo->ptr) {
 265         pipe_mutex_unlock(bo->map_mutex);
 266         return bo->ptr;
 267     }
 268     args.handle = bo->handle;
 269     args.offset = 0;
 270     args.size = (uint64_t)bo->size;
 271     if (drmCommandWriteRead(bo->rws->fd,
 272                             DRM_RADEON_GEM_MMAP,
 273                             &args,
 274                             sizeof(args))) {
 275         pipe_mutex_unlock(bo->map_mutex);
 276         fprintf(stderr, "radeon: gem_mmap failed: %p 0x%08X\n",
 277                 bo, bo->handle);
 278         return NULL;
 279     }
 280
 281     ptr = os_mmap(0, args.size, PROT_READ|PROT_WRITE, MAP_SHARED,
 282                bo->rws->fd, args.addr_ptr);
 283     if (ptr == MAP_FAILED) {
 284         pipe_mutex_unlock(bo->map_mutex);
 285         fprintf(stderr, "radeon: mmap failed, errno: %i\n", errno);
 286         return NULL;
 287     }
 288     bo->ptr = ptr;
 289     pipe_mutex_unlock(bo->map_mutex);
 290
 291     return bo->ptr;
 292 }
 293
 294 static void radeon_bo_unmap_internal(struct pb_buffer *_buf)
 295 {
 296     /* NOP */
 297 }
 298
 299 static void radeon_bo_get_base_buffer(struct pb_buffer *buf,
 300                                       struct pb_buffer **base_buf,
 301                                       unsigned *offset)
 302 {
 303     *base_buf = buf;
 304     *offset = 0;
 305 }
 306
 307 static enum pipe_error radeon_bo_validate(struct pb_buffer *_buf,
 308                                           struct pb_validate *vl,
 309                                           unsigned flags)
 310 {
 311     /* Always pinned */
 312     return PIPE_OK;
 313 }
 314
 315 static void radeon_bo_fence(struct pb_buffer *buf,
 316                             struct pipe_fence_handle *fence)
 317 {
 318 }
 319
 320 const struct pb_vtbl radeon_bo_vtbl = {
 321     radeon_bo_destroy,
 322     radeon_bo_map_internal,
 323     radeon_bo_unmap_internal,
 324     radeon_bo_validate,
 325     radeon_bo_fence,
 326     radeon_bo_get_base_buffer,
 327 };
 328
 329 static struct pb_buffer *radeon_bomgr_create_bo(struct pb_manager *_mgr,
 330                                                 pb_size size,
 331                                                 const struct pb_desc *desc)
 332 {
 333     struct radeon_bomgr *mgr = radeon_bomgr(_mgr);
 334     struct radeon_drm_winsys *rws = mgr->rws;
 335     struct radeon_bo *bo;
 336     struct drm_radeon_gem_create args = {};
 337
 338     args.size = size;
 339     args.alignment = desc->alignment;
 340     args.initial_domain =
 341         (desc->usage & RADEON_PB_USAGE_DOMAIN_GTT  ?
 342          RADEON_GEM_DOMAIN_GTT  : 0) |
 343         (desc->usage & RADEON_PB_USAGE_DOMAIN_VRAM ?
 344          RADEON_GEM_DOMAIN_VRAM : 0);
 345
 346     if (drmCommandWriteRead(rws->fd, DRM_RADEON_GEM_CREATE,
 347                             &args, sizeof(args))) {
 348         fprintf(stderr, "radeon: Failed to allocate a buffer:\n");
 349         fprintf(stderr, "radeon:    size      : %d bytes\n", size);
 350         fprintf(stderr, "radeon:    alignment : %d bytes\n", desc->alignment);
 351         fprintf(stderr, "radeon:    domains   : %d\n", args.initial_domain);
 352         return NULL;
 353     }
 354
 355     bo = CALLOC_STRUCT(radeon_bo);
 356     if (!bo)
 357         return NULL;
 358
 359     pipe_reference_init(&bo->base.base.reference, 1);
 360     bo->base.base.alignment = desc->alignment;
 361     bo->base.base.usage = desc->usage;
 362     bo->base.base.size = size;
 363     bo->base.vtbl = &radeon_bo_vtbl;
 364     bo->mgr = mgr;
 365     bo->rws = mgr->rws;
 366     bo->handle = args.handle;
 367     bo->size = size;
 368     pipe_mutex_init(bo->map_mutex);
 369
 370     return &bo->base;
 371 }
 372
 373 static void radeon_bomgr_flush(struct pb_manager *mgr)
 374 {
 375     /* NOP */
 376 }
 377
 378 /* This is for the cache bufmgr. */
 379 static boolean radeon_bomgr_is_buffer_busy(struct pb_manager *_mgr,
 380                                            struct pb_buffer *_buf)
 381 {
 382    struct radeon_bo *bo = radeon_bo(_buf);
 383
 384    if (radeon_bo_is_referenced_by_any_cs(bo)) {
 385        return TRUE;
 386    }
 387
 388    if (radeon_bo_is_busy((struct pb_buffer*)bo, RADEON_USAGE_READWRITE)) {
 389        return TRUE;
 390    }
 391
 392    return FALSE;
 393 }
 394
 395 static void radeon_bomgr_destroy(struct pb_manager *_mgr)
 396 {
 397     struct radeon_bomgr *mgr = radeon_bomgr(_mgr);
 398     util_hash_table_destroy(mgr->bo_handles);
 399     pipe_mutex_destroy(mgr->bo_handles_mutex);
 400     FREE(mgr);
 401 }
 402
 403 #define PTR_TO_UINT(x) ((unsigned)((intptr_t)(x)))
 404
 405 static unsigned handle_hash(void *key)
 406 {
 407     return PTR_TO_UINT(key);
 408 }
 409
 410 static int handle_compare(void *key1, void *key2)
 411 {
 412     return PTR_TO_UINT(key1) != PTR_TO_UINT(key2);
 413 }
 414
 415 struct pb_manager *radeon_bomgr_create(struct radeon_drm_winsys *rws)
 416 {
 417     struct radeon_bomgr *mgr;
 418
 419     mgr = CALLOC_STRUCT(radeon_bomgr);
 420     if (!mgr)
 421         return NULL;
 422
 423     mgr->base.destroy = radeon_bomgr_destroy;
 424     mgr->base.create_buffer = radeon_bomgr_create_bo;
 425     mgr->base.flush = radeon_bomgr_flush;
 426     mgr->base.is_buffer_busy = radeon_bomgr_is_buffer_busy;
 427
 428     mgr->rws = rws;
 429     mgr->bo_handles = util_hash_table_create(handle_hash, handle_compare);
 430     pipe_mutex_init(mgr->bo_handles_mutex);
 431     return &mgr->base;
 432 }
 433
 434 static void *radeon_bo_map(struct pb_buffer *buf,
 435                            struct radeon_winsys_cs *cs,
 436                            enum pipe_transfer_usage usage)
 437 {
 438     return pb_map(buf, get_pb_usage_from_transfer_flags(usage), cs);
 439 }
 440
 441 static void radeon_bo_get_tiling(struct pb_buffer *_buf,
 442                                  enum radeon_bo_layout *microtiled,
 443                                  enum radeon_bo_layout *macrotiled)
 444 {
 445     struct radeon_bo *bo = get_radeon_bo(_buf);
 446     struct drm_radeon_gem_set_tiling args = {};
 447
 448     args.handle = bo->handle;
 449
 450     drmCommandWriteRead(bo->rws->fd,
 451                         DRM_RADEON_GEM_GET_TILING,
 452                         &args,
 453                         sizeof(args));
 454
 455     *microtiled = RADEON_LAYOUT_LINEAR;
 456     *macrotiled = RADEON_LAYOUT_LINEAR;
 457     if (args.tiling_flags & RADEON_BO_FLAGS_MICRO_TILE)
 458         *microtiled = RADEON_LAYOUT_TILED;
 459
 460     if (args.tiling_flags & RADEON_BO_FLAGS_MACRO_TILE)
 461         *macrotiled = RADEON_LAYOUT_TILED;
 462 }
 463
 464 static void radeon_bo_set_tiling(struct pb_buffer *_buf,
 465                                  struct radeon_winsys_cs *rcs,
 466                                  enum radeon_bo_layout microtiled,
 467                                  enum radeon_bo_layout macrotiled,
 468                                  uint32_t pitch)
 469 {
 470     struct radeon_bo *bo = get_radeon_bo(_buf);
 471     struct radeon_drm_cs *cs = radeon_drm_cs(rcs);
 472     struct drm_radeon_gem_set_tiling args = {};
 473
 474     /* Tiling determines how DRM treats the buffer data.
 475      * We must flush CS when changing it if the buffer is referenced. */
 476     if (cs && radeon_bo_is_referenced_by_cs(cs, bo)) {
 477         cs->flush_cs(cs->flush_data, 0);
 478     }
 479
 480     while (p_atomic_read(&bo->num_active_ioctls)) {
 481         sched_yield();
 482     }
 483
 484     if (microtiled == RADEON_LAYOUT_TILED)
 485         args.tiling_flags |= RADEON_BO_FLAGS_MICRO_TILE;
 486     else if (microtiled == RADEON_LAYOUT_SQUARETILED)
 487         args.tiling_flags |= RADEON_BO_FLAGS_MICRO_TILE_SQUARE;
 488
 489     if (macrotiled == RADEON_LAYOUT_TILED)
 490         args.tiling_flags |= RADEON_BO_FLAGS_MACRO_TILE;
 491
 492     args.handle = bo->handle;
 493     args.pitch = pitch;
 494
 495     drmCommandWriteRead(bo->rws->fd,
 496                         DRM_RADEON_GEM_SET_TILING,
 497                         &args,
 498                         sizeof(args));
 499 }
 500
 501 static struct radeon_winsys_cs_handle *radeon_drm_get_cs_handle(
 502         struct pb_buffer *_buf)
 503 {
 504     /* return radeon_bo. */
 505     return (struct radeon_winsys_cs_handle*)get_radeon_bo(_buf);
 506 }
 507
 508 static unsigned get_pb_usage_from_create_flags(enum radeon_bo_domain domain)
 509 {
 510     unsigned res = 0;
 511
 512     if (domain & RADEON_DOMAIN_GTT)
 513         res |= RADEON_PB_USAGE_DOMAIN_GTT;
 514
 515     if (domain & RADEON_DOMAIN_VRAM)
 516         res |= RADEON_PB_USAGE_DOMAIN_VRAM;
 517
 518     return res;
 519 }
 520
 521 static struct pb_buffer *
 522 radeon_winsys_bo_create(struct radeon_winsys *rws,
 523                         unsigned size,
 524                         unsigned alignment,
 525                         unsigned bind,
 526                         enum radeon_bo_domain domain)
 527 {
 528     struct radeon_drm_winsys *ws = radeon_drm_winsys(rws);
 529     struct pb_desc desc;
 530     struct pb_manager *provider;
 531     struct pb_buffer *buffer;
 532
 533     memset(&desc, 0, sizeof(desc));
 534     desc.alignment = alignment;
 535     desc.usage = get_pb_usage_from_create_flags(domain);
 536
 537     /* Assign a buffer manager. */
 538     if (bind & (PIPE_BIND_VERTEX_BUFFER | PIPE_BIND_INDEX_BUFFER |
 539                 PIPE_BIND_CONSTANT_BUFFER))
 540         provider = ws->cman;
 541     else
 542         provider = ws->kman;
 543
 544     buffer = provider->create_buffer(provider, size, &desc);
 545     if (!buffer)
 546         return NULL;
 547
 548     return (struct pb_buffer*)buffer;
 549 }
 550
 551 static struct pb_buffer *radeon_winsys_bo_from_handle(struct radeon_winsys *rws,
 552                                                            struct winsys_handle *whandle,
 553                                                            unsigned *stride,
 554                                                            unsigned *size)
 555 {
 556     struct radeon_drm_winsys *ws = radeon_drm_winsys(rws);
 557     struct radeon_bo *bo;
 558     struct radeon_bomgr *mgr = radeon_bomgr(ws->kman);
 559     struct drm_gem_open open_arg = {};
 560
 561     /* We must maintain a list of pairs <handle, bo>, so that we always return
 562      * the same BO for one particular handle. If we didn't do that and created
 563      * more than one BO for the same handle and then relocated them in a CS,
 564      * we would hit a deadlock in the kernel.
 565      *
 566      * The list of pairs is guarded by a mutex, of course. */
 567     pipe_mutex_lock(mgr->bo_handles_mutex);
 568
 569     /* First check if there already is an existing bo for the handle. */
 570     bo = util_hash_table_get(mgr->bo_handles, (void*)(uintptr_t)whandle->handle);
 571     if (bo) {
 572         /* Increase the refcount. */
 573         struct pb_buffer *b = NULL;
 574         pb_reference(&b, &bo->base);
 575         goto done;
 576     }
 577
 578     /* There isn't, create a new one. */
 579     bo = CALLOC_STRUCT(radeon_bo);
 580     if (!bo) {
 581         goto fail;
 582     }
 583
 584     /* Open the BO. */
 585     open_arg.name = whandle->handle;
 586     if (drmIoctl(ws->fd, DRM_IOCTL_GEM_OPEN, &open_arg)) {
 587         FREE(bo);
 588         goto fail;
 589     }
 590     bo->handle = open_arg.handle;
 591     bo->size = open_arg.size;
 592     bo->name = whandle->handle;
 593
 594     /* Initialize it. */
 595     pipe_reference_init(&bo->base.base.reference, 1);
 596     bo->base.base.alignment = 0;
 597     bo->base.base.usage = PB_USAGE_GPU_WRITE | PB_USAGE_GPU_READ;
 598     bo->base.base.size = bo->size;
 599     bo->base.vtbl = &radeon_bo_vtbl;
 600     bo->mgr = mgr;
 601     bo->rws = mgr->rws;
 602     pipe_mutex_init(bo->map_mutex);
 603
 604     util_hash_table_set(mgr->bo_handles, (void*)(uintptr_t)whandle->handle, bo);
 605
 606 done:
 607     pipe_mutex_unlock(mgr->bo_handles_mutex);
 608
 609     if (stride)
 610         *stride = whandle->stride;
 611     if (size)
 612         *size = bo->base.base.size;
 613
 614     return (struct pb_buffer*)bo;
 615
 616 fail:
 617     pipe_mutex_unlock(mgr->bo_handles_mutex);
 618     return NULL;
 619 }
 620
 621 static boolean radeon_winsys_bo_get_handle(struct pb_buffer *buffer,
 622                                            unsigned stride,
 623                                            struct winsys_handle *whandle)
 624 {
 625     struct drm_gem_flink flink = {};
 626     struct radeon_bo *bo = get_radeon_bo(buffer);
 627
 628     if (whandle->type == DRM_API_HANDLE_TYPE_SHARED) {
 629         if (!bo->flinked) {
 630             flink.handle = bo->handle;
 631
 632             if (ioctl(bo->rws->fd, DRM_IOCTL_GEM_FLINK, &flink)) {
 633                 return FALSE;
 634             }
 635
 636             bo->flinked = TRUE;
 637             bo->flink = flink.name;
 638         }
 639         whandle->handle = bo->flink;
 640     } else if (whandle->type == DRM_API_HANDLE_TYPE_KMS) {
 641         whandle->handle = bo->handle;
 642     }
 643
 644     whandle->stride = stride;
 645     return TRUE;
 646 }
 647
 648 void radeon_bomgr_init_functions(struct radeon_drm_winsys *ws)
 649 {
 650     ws->base.buffer_get_cs_handle = radeon_drm_get_cs_handle;
 651     ws->base.buffer_set_tiling = radeon_bo_set_tiling;
 652     ws->base.buffer_get_tiling = radeon_bo_get_tiling;
 653     ws->base.buffer_map = radeon_bo_map;
 654     ws->base.buffer_unmap = pb_unmap;
 655     ws->base.buffer_wait = radeon_bo_wait;
 656     ws->base.buffer_is_busy = radeon_bo_is_busy;
 657     ws->base.buffer_create = radeon_winsys_bo_create;
 658     ws->base.buffer_from_handle = radeon_winsys_bo_from_handle;
 659     ws->base.buffer_get_handle = radeon_winsys_bo_get_handle;
 660 }